models: Remove generated C files
These files are generated while running proprietary firmware, but once
they are added to coreboot they are no longer needed. They also quickly
become stale as the files are always changed in coreboot.
find models/ -name gpio.h -exec rm {} \;
find models/ -name hda_verb.c -exec rm {} \;
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Jeremy Soller
Jeremy Soller
parent
e4960f163e
commit
77581d11fc
@@ -1,297 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#define DGPU_RST_N GPP_F8
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#define DGPU_PWR_EN GPP_F9
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#define DGPU_GC6 GPP_K11
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#ifndef __ACPI__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_GPO(DGPU_RST_N, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(DGPU_PWR_EN, 0, DEEP), // DGPU_PWR_EN
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};
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
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PAD_CFG_GPI(GPD2, NATIVE, PWROK),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
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PAD_CFG_GPI(GPD7, NONE, PWROK),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
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PAD_CFG_GPO(GPD9, 0, PWROK),
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
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PAD_CFG_GPI(GPD11, NONE, PWROK),
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_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A14, NONE, DEEP),
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
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PAD_CFG_GPI(GPP_B1, NONE, DEEP),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP),
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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PAD_CFG_GPI(GPP_B4, NONE, DEEP),
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PAD_CFG_GPI(GPP_B5, NONE, DEEP),
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PAD_CFG_GPI(GPP_B6, NONE, DEEP),
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_B8, NONE, DEEP),
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PAD_CFG_GPI(GPP_B9, NONE, DEEP),
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PAD_CFG_GPI(GPP_B10, NONE, DEEP),
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PAD_CFG_GPI(GPP_B11, NONE, DEEP),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_B15, 1, DEEP),
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PAD_CFG_GPI(GPP_B16, NONE, DEEP),
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PAD_CFG_GPI(GPP_B17, NONE, DEEP),
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PAD_CFG_GPI(GPP_B18, NONE, DEEP),
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PAD_CFG_GPI(GPP_B19, NONE, DEEP),
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PAD_CFG_GPI(GPP_B20, NONE, DEEP),
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PAD_CFG_GPI(GPP_B21, NONE, DEEP),
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PAD_CFG_GPI(GPP_B22, NONE, DEEP),
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PAD_CFG_GPI(GPP_B23, NONE, DEEP),
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_C2, NONE, DEEP),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
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PAD_CFG_GPI(GPP_C5, NONE, DEEP),
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PAD_CFG_GPI(GPP_C6, NONE, DEEP),
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PAD_CFG_GPI(GPP_C7, NONE, DEEP),
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PAD_CFG_GPI(GPP_C8, NONE, DEEP),
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PAD_CFG_GPI(GPP_C9, NONE, DEEP),
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PAD_CFG_GPI(GPP_C10, NONE, DEEP),
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PAD_CFG_GPI(GPP_C11, NONE, DEEP),
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PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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PAD_CFG_GPI(GPP_C13, NONE, DEEP),
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PAD_CFG_GPI(GPP_C14, NONE, DEEP),
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PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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PAD_CFG_GPI(GPP_C21, NONE, DEEP),
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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PAD_CFG_GPI(GPP_C23, NONE, DEEP),
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/* ------- GPIO Group GPP_D ------- */
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PAD_CFG_GPI(GPP_D0, NONE, DEEP),
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PAD_CFG_GPI(GPP_D1, NONE, DEEP),
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PAD_CFG_GPI(GPP_D2, NONE, DEEP),
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PAD_CFG_GPI(GPP_D3, NONE, DEEP),
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PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
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PAD_CFG_GPI(GPP_D7, NONE, DEEP),
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PAD_CFG_GPI(GPP_D8, NONE, DEEP),
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
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PAD_CFG_GPI(GPP_D12, NONE, DEEP),
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PAD_CFG_GPI(GPP_D13, NONE, DEEP),
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PAD_CFG_GPI(GPP_D14, NONE, DEEP),
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PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_D16, NONE, DEEP),
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PAD_CFG_GPI(GPP_D17, NONE, DEEP),
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PAD_CFG_GPI(GPP_D18, NONE, DEEP),
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PAD_CFG_GPI(GPP_D19, NONE, DEEP),
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PAD_CFG_GPI(GPP_D20, NONE, DEEP),
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PAD_CFG_GPI(GPP_D21, NONE, DEEP),
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PAD_CFG_GPI(GPP_D22, NONE, DEEP),
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PAD_CFG_GPO(GPP_D23, 1, DEEP),
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPI(GPP_E0, NONE, DEEP),
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PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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PAD_CFG_GPI(GPP_E4, NONE, DEEP),
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PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
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PAD_CFG_GPI(GPP_E6, NONE, DEEP),
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_E9, NONE, DEEP),
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
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PAD_CFG_GPO(GPP_F1, 1, DEEP),
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PAD_CFG_GPO(GPP_F2, 1, PLTRST),
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PAD_CFG_GPO(GPP_F3, 0, PLTRST),
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PAD_CFG_GPO(GPP_F4, 1, DEEP),
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_F6, 1, DEEP),
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PAD_CFG_GPO(GPP_F7, 0, DEEP),
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PAD_CFG_GPO(GPP_F8, 1, DEEP),
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PAD_CFG_GPO(GPP_F9, 1, DEEP),
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PAD_CFG_GPI(GPP_F10, NONE, DEEP),
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PAD_CFG_GPI(GPP_F11, NONE, DEEP),
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PAD_CFG_GPI(GPP_F12, NONE, DEEP),
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PAD_CFG_GPI(GPP_F13, NONE, DEEP),
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PAD_CFG_GPI(GPP_F14, NONE, DEEP),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP),
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PAD_CFG_GPI(GPP_F16, NONE, DEEP),
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PAD_CFG_GPO(GPP_F17, 1, DEEP),
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PAD_CFG_GPO(GPP_F18, 1, DEEP),
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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PAD_NC(GPP_F22, NONE),
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PAD_CFG_GPO(GPP_F23, 1, PLTRST),
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/* ------- GPIO Group GPP_G ------- */
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PAD_CFG_GPI(GPP_G0, NONE, DEEP),
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PAD_CFG_GPI(GPP_G1, NONE, DEEP),
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PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
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PAD_CFG_GPI(GPP_G3, NONE, DEEP),
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PAD_CFG_GPI(GPP_G4, NONE, DEEP),
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PAD_CFG_GPI(GPP_G5, NONE, DEEP),
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PAD_CFG_GPO(GPP_G6, 1, DEEP),
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PAD_CFG_GPO(GPP_G7, 1, DEEP),
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PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
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PAD_CFG_GPI(GPP_G9, NONE, DEEP),
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PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
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PAD_CFG_GPI(GPP_G11, NONE, DEEP),
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PAD_NC(GPP_G12, NATIVE),
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PAD_NC(GPP_G13, NATIVE),
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PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
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PAD_CFG_GPI(GPP_G15, NONE, DEEP),
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_H5, NONE, DEEP),
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PAD_CFG_GPI(GPP_H6, NONE, DEEP),
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PAD_CFG_GPI(GPP_H7, NONE, DEEP),
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PAD_CFG_GPI(GPP_H8, NONE, DEEP),
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PAD_CFG_GPI(GPP_H9, NONE, DEEP),
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PAD_CFG_GPI(GPP_H10, NONE, DEEP),
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PAD_CFG_GPI(GPP_H11, NONE, DEEP),
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PAD_CFG_GPI(GPP_H12, NONE, DEEP),
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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PAD_CFG_GPI(GPP_H14, NONE, DEEP),
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PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
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PAD_CFG_GPI(GPP_H16, NONE, DEEP),
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PAD_CFG_GPO(GPP_H17, 1, DEEP),
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PAD_CFG_GPI(GPP_H18, NONE, DEEP),
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PAD_CFG_GPI(GPP_H19, NONE, DEEP),
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PAD_CFG_GPI(GPP_H20, NONE, DEEP),
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PAD_CFG_GPI(GPP_H21, NONE, DEEP),
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PAD_CFG_GPI(GPP_H22, NONE, DEEP),
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PAD_CFG_GPO(GPP_H23, 1, DEEP),
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/* ------- GPIO Group GPP_I ------- */
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PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
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_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
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PAD_CFG_GPI(GPP_I4, NONE, DEEP),
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PAD_CFG_GPI(GPP_I5, NONE, DEEP),
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PAD_CFG_GPI(GPP_I6, NONE, DEEP),
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PAD_CFG_GPI(GPP_I7, NONE, DEEP),
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PAD_CFG_GPI(GPP_I8, NONE, DEEP),
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PAD_CFG_GPO(GPP_I9, 1, DEEP),
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PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
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PAD_CFG_GPI(GPP_I11, NONE, PLTRST),
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PAD_CFG_GPI(GPP_I12, NONE, PLTRST),
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PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
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PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
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/* ------- GPIO Group GPP_J ------- */
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PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
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PAD_CFG_GPI(GPP_J9, NONE, DEEP),
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/* ------- GPIO Group GPP_K ------- */
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PAD_CFG_GPO(GPP_K0, 0, DEEP),
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PAD_CFG_GPI(GPP_K1, NONE, DEEP),
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PAD_CFG_GPI(GPP_K2, NONE, DEEP),
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PAD_CFG_GPI(GPP_K3, NONE, DEEP),
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PAD_CFG_GPI(GPP_K4, NONE, DEEP),
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PAD_CFG_GPI(GPP_K5, NONE, DEEP),
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PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_K7, NONE, DEEP),
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PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_K10, NONE, DEEP),
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PAD_CFG_GPI(GPP_K11, NONE, PLTRST),
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/* ------- GPIO Group GPP_R ------- */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_R6, NONE, DEEP),
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PAD_CFG_GPI(GPP_R7, NONE, DEEP),
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PAD_CFG_GPI(GPP_R8, NONE, DEEP),
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PAD_CFG_GPI(GPP_R9, NONE, DEEP),
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PAD_CFG_GPI(GPP_R10, NONE, DEEP),
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PAD_CFG_GPI(GPP_R11, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
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PAD_CFG_GPI(GPP_R13, NONE, DEEP),
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PAD_CFG_GPI(GPP_R14, NONE, DEEP),
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PAD_CFG_GPI(GPP_R15, NONE, DEEP),
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PAD_CFG_GPI(GPP_R16, NONE, DEEP),
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PAD_CFG_GPI(GPP_R17, NONE, DEEP),
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PAD_CFG_GPI(GPP_R18, NONE, DEEP),
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PAD_CFG_GPI(GPP_R19, NONE, DEEP),
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/* ------- GPIO Group GPP_S ------- */
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PAD_CFG_GPI(GPP_S0, NONE, DEEP),
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PAD_CFG_GPI(GPP_S1, NONE, DEEP),
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PAD_CFG_GPI(GPP_S2, NONE, DEEP),
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PAD_CFG_GPI(GPP_S3, NONE, DEEP),
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PAD_CFG_GPI(GPP_S4, NONE, DEEP),
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PAD_CFG_GPI(GPP_S5, NONE, DEEP),
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PAD_CFG_GPI(GPP_S6, NONE, DEEP),
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PAD_CFG_GPI(GPP_S7, NONE, DEEP),
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};
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#endif
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#endif
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@@ -1,48 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* Realtek, ALC1220 */
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0x10ec1220, /* Vendor ID */
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0x155867f1, /* Subsystem ID */
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12, /* Number of entries */
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AZALIA_SUBVENDOR(0, 0x155867f1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9eHDMI/DP */
|
||||
0x10de009e, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
Reference in New Issue
Block a user