Update coreboot and coreboot configs

This commit is contained in:
Jeremy Soller
2020-06-04 09:23:05 -06:00
parent 66c2261af1
commit 7a2dadb3e9
9 changed files with 450 additions and 315 deletions

View File

@@ -242,8 +242,8 @@ CONFIG_SOC_INTEL_COMETLAKE=y
CONFIG_MAX_ROOT_PORTS=16
CONFIG_MAX_PCIE_CLOCKS=6
# CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE is not set
# CONFIG_USE_CANNONLAKE_CAR_NEM_ENHANCED is not set
CONFIG_USE_CANNONLAKE_FSP_CAR=y
CONFIG_USE_CANNONLAKE_CAR_NEM_ENHANCED=y
# CONFIG_USE_CANNONLAKE_FSP_CAR is not set
CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=0
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
CONFIG_UART_PCI_ADDR=0x0
@@ -259,10 +259,10 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_CAR is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
# CONFIG_INTEL_CAR_NEM is not set
# CONFIG_INTEL_CAR_CQOS is not set
# CONFIG_INTEL_CAR_NEM_ENHANCED is not set
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
@@ -384,8 +384,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
# CONFIG_TSC_SYNC_LFENCE is not set
# CONFIG_TSC_SYNC_MFENCE is not set
# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
CONFIG_XIP_ROM_SIZE=0x10000
CONFIG_NO_FIXED_XIP_ROM_SIZE=y
CONFIG_LOGICAL_CPUS=y
CONFIG_HAVE_SMI_HANDLER=y
# CONFIG_NO_SMM is not set
@@ -625,10 +624,8 @@ CONFIG_FSP_USE_REPO=y
CONFIG_PLATFORM_USES_FSP2_0=y
# CONFIG_PLATFORM_USES_FSP2_1 is not set
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_FSP_T_CBFS="fspt.bin"
CONFIG_FSP_T_FILE="$(obj)/Fsp_T.fd"
CONFIG_FSP_CAR=y
CONFIG_FSP_T_XIP=y
# CONFIG_FSP_CAR is not set
# CONFIG_FSP_T_XIP is not set
CONFIG_FSP_USES_CB_STACK=y
CONFIG_HAVE_FSP_LOGO_SUPPORT=y
# CONFIG_FSP2_0_DISPLAY_LOGO is not set