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Update coreboot and configs to fix darp6 MTRR allocation

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This commit is contained in:
Jeremy Soller
2020-09-22 11:25:42 -06:00
parent f10af76b9b
commit 904cee45c1
15 changed files with 47 additions and 47 deletions
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10
models/galp3-c/coreboot.config
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@@ -164,11 +164,10 @@ CONFIG_HEAP_SIZE=0x8000
# CONFIG_BOARD_SYSTEM76_THELIO_B1 is not set
CONFIG_BOARD_SYSTEM76_GALP3_C=y
# CONFIG_BOARD_SYSTEM76_DARP5 is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
CONFIG_SUBSYSTEM_DEVICE_ID=0x1323
CONFIG_FSP_M_XIP=y
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Include/"
CONFIG_FSP_FD_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd"
CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
CONFIG_SUBSYSTEM_DEVICE_ID=0x1323
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
@@ -549,8 +548,8 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_INTEL_GMA_HAVE_VBT=y
@@ -637,6 +636,7 @@ CONFIG_PLATFORM_USES_FSP2_0=y
# CONFIG_PLATFORM_USES_FSP2_2 is not set
CONFIG_HAVE_INTEL_FSP_REPO=y
# CONFIG_FSP_CAR is not set
CONFIG_FSP_M_XIP=y
# CONFIG_FSP_T_XIP is not set
CONFIG_FSP_USES_CB_STACK=y
CONFIG_HAVE_FSP_LOGO_SUPPORT=y