diff --git a/CHANGELOG.md b/CHANGELOG.md
index 7138a86..e9a1b08 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,6 +4,16 @@ Changes are identified by the date of the released firmware including them. If
you are running System76 Open Firmware, opening the boot menu will show this
date followed by an underscore and a short git revision.
+## 2021-07-20
+
+- gaze16: Release of open firmware with System76 EC
+- Improved thermals by syncing CPU and GPU fans
+- Enabled fan speed interpolation
+- Fixed ACPI timeout on S3 resume if a key is held
+- Fixed keyboard responsiveness when touchpad uses wrong protocol
+- Fixed entering firmware-setup due to missed keystrokes on boot
+- Added scroll lock to default keyboard layouts
+
## 2021-04-07
- darp7, galp5, lemp10: Update microcode
diff --git a/FSP b/FSP
index 6879b89..3826abd 160000
--- a/FSP
+++ b/FSP
@@ -1 +1 @@
-Subproject commit 6879b89ae02ad9079c6d7334e4d6a3dff15d649e
+Subproject commit 3826abd02b466dc7c0c83133627dd6ca7946a7c9
diff --git a/apps/firmware-update b/apps/firmware-update
index 92f09b5..b1b153d 160000
--- a/apps/firmware-update
+++ b/apps/firmware-update
@@ -1 +1 @@
-Subproject commit 92f09b565b11732a5d7daeb4671c77de0a4724b5
+Subproject commit b1b153df137f8ba0e566ad91e99c210b57e7150f
diff --git a/coreboot b/coreboot
index 03f477d..f1caea8 160000
--- a/coreboot
+++ b/coreboot
@@ -1 +1 @@
-Subproject commit 03f477d39513da7984046f84efa0115e04d70ba5
+Subproject commit f1caea884c49bebd657631bcbf8859ad9aac740b
diff --git a/ec b/ec
index 16778e4..ff53939 160000
--- a/ec
+++ b/ec
@@ -1 +1 @@
-Subproject commit 16778e4a41477498eaf5791cae57ae404515973e
+Subproject commit ff53939a5667c9ba05e5f478653913f695530363
diff --git a/models/README.md b/models/README.md
index a84d262..cb18f36 100644
--- a/models/README.md
+++ b/models/README.md
@@ -14,11 +14,11 @@
- [galp3-c](./galp3-c) - System76 Galago Pro (galp3-c)
- [galp4](./galp4) - System76 Galago Pro (galp4)
- [galp5](./galp5) - System76 Galago Pro (galp5)
-- [gaze14_1650_15](./gaze14_1650_15) - System76 Gazelle (gaze14)
-- [gaze14_1650_17](./gaze14_1650_17) - System76 Gazelle (gaze14)
-- [gaze14_1660ti_15](./gaze14_1660ti_15) - System76 Gazelle (gaze14)
-- [gaze14_1660ti_17](./gaze14_1660ti_17) - System76 Gazelle (gaze14)
+- [gaze14_1650](./gaze14_1650) - System76 Gazelle (gaze14)
+- [gaze14_1660ti](./gaze14_1660ti) - System76 Gazelle (gaze14)
- [gaze15](./gaze15) - System76 Gazelle (gaze15)
+- [gaze16-3050](./gaze16-3050) - System76 Gazelle (gaze16)
+- [gaze16-3060](./gaze16-3060) - System76 Gazelle (gaze16)
- [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
- [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
- [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
diff --git a/models/gaze16-3050/FSP/Fsp_M.fd b/models/gaze16-3050/FSP/Fsp_M.fd
new file mode 100644
index 0000000..c149193
--- /dev/null
+++ b/models/gaze16-3050/FSP/Fsp_M.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c23a3ca630e362b25ec84024423756eb1d48be3c00d08b9f718eeb9533a809f4
+size 651264
diff --git a/models/gaze16-3050/FSP/Fsp_S.fd b/models/gaze16-3050/FSP/Fsp_S.fd
new file mode 100644
index 0000000..6233dc9
--- /dev/null
+++ b/models/gaze16-3050/FSP/Fsp_S.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:53c9c9d8dc4db35612fc60e74f5461f55aa157e0943c53a0120f0764bd8396a4
+size 368640
diff --git a/models/gaze16-3050/FSP/Fsp_T.fd b/models/gaze16-3050/FSP/Fsp_T.fd
new file mode 100644
index 0000000..c8c54aa
--- /dev/null
+++ b/models/gaze16-3050/FSP/Fsp_T.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2c17e3dfb42354917778fb079c1d72aaca09086ebc94fcbe2904449195ceaa5b
+size 28672
diff --git a/models/gaze16-3050/FSP/Include/FirmwareVersionInfoHob.h b/models/gaze16-3050/FSP/Include/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..2bb248b
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FirmwareVersionInfoHob.h
@@ -0,0 +1,62 @@
+/** @file
+ Header file for Firmware Version Information
+
+ @copyright
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include
+#include
+#include
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/models/gaze16-3050/FSP/Include/FspInfoHob.h b/models/gaze16-3050/FSP/Include/FspInfoHob.h
new file mode 100644
index 0000000..b64ad27
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FspInfoHob.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP Information HOB.
+
+@copyright
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _FSP_INFO_HOB_H_
+#define _FSP_INFO_HOB_H_
+
+extern EFI_GUID gFspInfoGuid;
+
+#pragma pack (push, 1)
+
+typedef struct {
+UINT8 SiliconInitVersionMajor;
+UINT8 SiliconInitVersionMinor;
+UINT8 SiliconInitVersionRevision;
+UINT8 SiliconInitVersionBuild;
+UINT8 FspVersionRevision;
+UINT8 FspVersionBuild;
+UINT8 TimeStamp [12];
+UINT8 FspVersionMinor;
+} FSP_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _FSP_INFO_HOB_H_
diff --git a/models/gaze16-3050/FSP/Include/FspUpd.h b/models/gaze16-3050/FSP/Include/FspUpd.h
new file mode 100644
index 0000000..850d04b
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FspUpd.h
@@ -0,0 +1,27 @@
+/** @file FspUpd.h
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4754 /* 'TGLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4754 /* 'TGLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4754 /* 'TGLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3050/FSP/Include/FspmUpd.h b/models/gaze16-3050/FSP/Include/FspmUpd.h
new file mode 100644
index 0000000..eee8f4c
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FspmUpd.h
@@ -0,0 +1,3615 @@
+/** @file FspmUpd.h
+
+ @copyright
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+#include
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0048 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x004A - Enable above 4GB MMIO resource support
+ Enable/disable above 4GB MMIO resource support
+ $EN_DIS
+**/
+ UINT8 EnableAbove4GBMmio;
+
+/** Offset 0x004B - Enable/Disable CrashLog Device 10
+ Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogDevice;
+
+/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr00]
+**/
+ UINT32 MemorySpdPtr000;
+
+/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr01]
+**/
+ UINT32 MemorySpdPtr001;
+
+/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr02]
+**/
+ UINT32 MemorySpdPtr010;
+
+/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr03]
+**/
+ UINT32 MemorySpdPtr011;
+
+/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr04]
+**/
+ UINT32 MemorySpdPtr020;
+
+/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr05]
+**/
+ UINT32 MemorySpdPtr021;
+
+/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr06]
+**/
+ UINT32 MemorySpdPtr030;
+
+/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr07]
+**/
+ UINT32 MemorySpdPtr031;
+
+/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr08]
+**/
+ UINT32 MemorySpdPtr100;
+
+/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr09]
+**/
+ UINT32 MemorySpdPtr101;
+
+/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr10]
+**/
+ UINT32 MemorySpdPtr110;
+
+/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr11]
+**/
+ UINT32 MemorySpdPtr111;
+
+/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr12]
+**/
+ UINT32 MemorySpdPtr120;
+
+/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr13]
+**/
+ UINT32 MemorySpdPtr121;
+
+/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr14]
+**/
+ UINT32 MemorySpdPtr130;
+
+/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr15]
+**/
+ UINT32 MemorySpdPtr131;
+
+/** Offset 0x008C - RcompResistor settings
+ Indicates RcompResistor settings: Board-dependent
+**/
+ UINT16 RcompResistor;
+
+/** Offset 0x008E - RcompTarget settings
+ RcompTarget settings: board-dependent
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh0]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch0[2];
+
+/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh1]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch1[2];
+
+/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh2]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch2[2];
+
+/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh3]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch3[2];
+
+/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh4]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch0[2];
+
+/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh5]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch1[2];
+
+/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh6]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch2[2];
+
+/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh7]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch3[2];
+
+/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh0]
+**/
+ UINT8 DqMapCpu2DramMc0Ch0[16];
+
+/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh1]
+**/
+ UINT8 DqMapCpu2DramMc0Ch1[16];
+
+/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh2]
+**/
+ UINT8 DqMapCpu2DramMc0Ch2[16];
+
+/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh3]
+**/
+ UINT8 DqMapCpu2DramMc0Ch3[16];
+
+/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh4]
+**/
+ UINT8 DqMapCpu2DramMc1Ch0[16];
+
+/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh5]
+**/
+ UINT8 DqMapCpu2DramMc1Ch1[16];
+
+/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh6]
+**/
+ UINT8 DqMapCpu2DramMc1Ch2[16];
+
+/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh7]
+**/
+ UINT8 DqMapCpu2DramMc1Ch3[16];
+
+/** Offset 0x0128 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x0129 - Smram Mask
+ The SMM Regions AB-SEG and/or H-SEG reserved
+ 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+ UINT8 SmramMask;
+
+/** Offset 0x012A - MRC Fast Boot
+ Enables/Disable the MRC fast path thru the MRC
+ $EN_DIS
+**/
+ UINT8 MrcFastBoot;
+
+/** Offset 0x012B - Rank Margin Tool per Task
+ This option enables the user to execute Rank Margin Tool per major training step
+ in the MRC.
+ $EN_DIS
+**/
+ UINT8 RmtPerTask;
+
+/** Offset 0x012C - Training Trace
+ This option enables the trained state tracing feature in MRC. This feature will
+ print out the key training parameters state across major training steps.
+ $EN_DIS
+**/
+ UINT8 TrainTrace;
+
+/** Offset 0x012D
+**/
+ UINT8 UnusedUpdSpace0[3];
+
+/** Offset 0x0130 - Intel Enhanced Debug
+ @deprecated - Not used and has no effect
+ 0 : Disable, 0x400000 : Enable
+**/
+ UINT32 IedSize;
+
+/** Offset 0x0134 - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x0138 - MMIO Size
+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+ UINT16 MmioSize;
+
+/** Offset 0x013A - Probeless Trace
+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+ This also requires IED to be enabled.
+ $EN_DIS
+**/
+ UINT8 ProbelessTrace;
+
+/** Offset 0x013B - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x013C - Spd Address Tabl
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[16];
+
+/** Offset 0x014C - Platform Debug Consent
+ To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
+ Enabling this BIOS option may alter the default value of other debug-related BIOS
+ options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
+ policies, but the user must set each debug option manually, aimed at advanced users.\n
+ Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
+**/
+ UINT8 PlatformDebugConsent;
+
+/** Offset 0x014D - DCI Enable
+ Determine if to enable DCI debug from host
+ $EN_DIS
+**/
+ UINT8 DciEn;
+
+/** Offset 0x014E - DCI DbC Mode
+ Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
+ Set both USB2/3DBCEN; No Change: Comply with HW value
+ 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
+**/
+ UINT8 DciDbcMode;
+
+/** Offset 0x014F - Enable DCI ModPHY Power Gate
+ Enable ModPHY Power Gate when DCI is enabled
+ $EN_DIS
+**/
+ UINT8 DciModphyPg;
+
+/** Offset 0x0150 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
+ This BIOS option enables kernel and platform debug for USB3 interface over a UFP
+ Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DciUsb3TypecUfpDbg;
+
+/** Offset 0x0151 - PCH Trace Hub Mode
+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+ 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+**/
+ UINT8 PchTraceHubMode;
+
+/** Offset 0x0152 - PCH Trace Hub Memory Region 0 buffer Size
+ Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg0Size;
+
+/** Offset 0x0153 - PCH Trace Hub Memory Region 1 buffer Size
+ Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg1Size;
+
+/** Offset 0x0154 - HD Audio DMIC Link Clock Select
+ Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB
+ 0: Both, 1: ClkA, 2: ClkB
+**/
+ UINT8 PchHdaAudioLinkDmicClockSelect[2];
+
+/** Offset 0x0156 - PchPreMemRsvd
+ Reserved for PCH Pre-Mem Reserved
+ $EN_DIS
+**/
+ UINT8 PchPreMemRsvd[5];
+
+/** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 X2ApicOptOut;
+
+/** Offset 0x015C - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 DmaControlGuarantee;
+
+/** Offset 0x015D
+**/
+ UINT8 UnusedUpdSpace1[3];
+
+/** Offset 0x0160 - Base addresses for VT-d function MMIO access
+ Base addresses for VT-d MMIO access per VT-d engine
+**/
+ UINT32 VtdBaseAddress[9];
+
+/** Offset 0x0184 - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x0185 - Vtd Programming for Igd
+ 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIgdEnable;
+
+/** Offset 0x0186 - Vtd Programming for Ipu
+ 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIpuEnable;
+
+/** Offset 0x0187 - Vtd Programming for Iop
+ 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIopEnable;
+
+/** Offset 0x0188 - Vtd Programming for ITbt
+ 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdItbtEnable;
+
+/** Offset 0x0189 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
+ 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
+ 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x018A - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGfx;
+
+/** Offset 0x018B - Aperture Size
+ Select the Aperture Size.
+ 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB
+**/
+ UINT8 ApertureSize;
+
+/** Offset 0x018C - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x018D
+**/
+ UINT8 UnusedUpdSpace2;
+
+/** Offset 0x018E - DDR Frequency Limit
+ Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+ 2133, 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 DdrFreqLimit;
+
+/** Offset 0x0190 - SA GV
+ System Agent dynamic frequency support and when enabled memory will be training
+ at three different frequencies.
+ 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x0191 - Memory Test on Warm Boot
+ Run Base Memory Test on Warm Boot
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemTestOnWarmBoot;
+
+/** Offset 0x0192 - DDR Speed Control
+ DDR Frequency and Gear control for all SAGV points.
+ 0:Auto, 1:Manual
+**/
+ UINT8 DdrSpeedControl;
+
+/** Offset 0x0193 - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x0194 - Controller 0 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh0]
+**/
+ UINT8 DisableDimmMc0Ch0;
+
+/** Offset 0x0195 - Controller 0 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh1]
+**/
+ UINT8 DisableDimmMc0Ch1;
+
+/** Offset 0x0196 - Controller 0 Channel 2 DIMM Control
+ Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh2]
+**/
+ UINT8 DisableDimmMc0Ch2;
+
+/** Offset 0x0197 - Controller 0 Channel 3 DIMM Control
+ Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh3]
+**/
+ UINT8 DisableDimmMc0Ch3;
+
+/** Offset 0x0198 - Controller 1 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh4]
+**/
+ UINT8 DisableDimmMc1Ch0;
+
+/** Offset 0x0199 - Controller 1 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh5]
+**/
+ UINT8 DisableDimmMc1Ch1;
+
+/** Offset 0x019A - Controller 1 Channel 2 DIMM Control
+ Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh6]
+**/
+ UINT8 DisableDimmMc1Ch2;
+
+/** Offset 0x019B - Controller 1 Channel 3 DIMM Control
+ Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh7]
+**/
+ UINT8 DisableDimmMc1Ch3;
+
+/** Offset 0x019C - Scrambler Support
+ This option enables data scrambling in memory.
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x019D - SPD Profile Selected
+ Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+ Profile 1, 3=XMP Profile 2
+ 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
+**/
+ UINT8 SpdProfileSelected;
+
+/** Offset 0x019E - Memory Reference Clock
+ 100MHz, 133MHz.
+ 0:133MHz, 1:100MHz
+**/
+ UINT8 RefClk;
+
+/** Offset 0x019F
+**/
+ UINT8 UnusedUpdSpace3;
+
+/** Offset 0x01A0 - Memory Voltage
+ DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
+ chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
+ 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+ Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+ UINT16 VddVoltage;
+
+/** Offset 0x01A2 - Memory Ratio
+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+ recalculate memory timings listed below.
+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 Ratio;
+
+/** Offset 0x01A3 - tCL
+ CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCL;
+
+/** Offset 0x01A4 - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCWL;
+
+/** Offset 0x01A5
+**/
+ UINT8 UnusedUpdSpace4;
+
+/** Offset 0x01A6 - tFAW
+ Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tFAW;
+
+/** Offset 0x01A8 - tRAS
+ RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRAS;
+
+/** Offset 0x01AA - tRCD/tRP
+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used
+ if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+ UINT8 tRCDtRP;
+
+/** Offset 0x01AB
+**/
+ UINT8 UnusedUpdSpace5;
+
+/** Offset 0x01AC - tREFI
+ Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tREFI;
+
+/** Offset 0x01AE - tRFC
+ Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRFC;
+
+/** Offset 0x01B0 - tRRD
+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRRD;
+
+/** Offset 0x01B1 - tRTP
+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
+ values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRTP;
+
+/** Offset 0x01B2 - tWR
+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+ 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+ 34:34, 40:40
+**/
+ UINT8 tWR;
+
+/** Offset 0x01B3 - tWTR
+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tWTR;
+
+/** Offset 0x01B4 - NMode
+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+ UINT8 NModeSupport;
+
+/** Offset 0x01B5 - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x01B6 - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x01B7 - CPU Trace Hub Mode
+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+ 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
+**/
+ UINT8 CpuTraceHubMode;
+
+/** Offset 0x01B8 - CPU Trace Hub Memory Region 0
+ CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg0Size;
+
+/** Offset 0x01B9 - CPU Trace Hub Memory Region 1
+ CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg1Size;
+
+/** Offset 0x01BA - SAGV Gear Ratio
+ Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 SaGvGear[4];
+
+/** Offset 0x01BE - SAGV Frequency
+ SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
+**/
+ UINT16 SaGvFreq[4];
+
+/** Offset 0x01C6 - SAGV Disabled Gear Ratio
+ Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 GearRatio;
+
+/** Offset 0x01C7 - HECI Timeouts
+ 0: Disable, 1: Enable (Default) timeout check for HECI
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
+/** Offset 0x01C8 - HECI1 BAR address
+ BAR address of HECI1
+**/
+ UINT32 Heci1BarAddress;
+
+/** Offset 0x01CC - HECI2 BAR address
+ BAR address of HECI2
+**/
+ UINT32 Heci2BarAddress;
+
+/** Offset 0x01D0 - HECI3 BAR address
+ BAR address of HECI3
+**/
+ UINT32 Heci3BarAddress;
+
+/** Offset 0x01D4 - HG dGPU Power Delay
+ HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
+ 300=300 microseconds
+**/
+ UINT16 HgDelayAfterPwrEn;
+
+/** Offset 0x01D6 - HG dGPU Reset Delay
+ HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
+ microseconds
+**/
+ UINT16 HgDelayAfterHoldReset;
+
+/** Offset 0x01D8 - MMIO size adjustment for AUTO mode
+ Positive number means increasing MMIO size, Negative value means decreasing MMIO
+ size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+ UINT16 MmioSizeAdjustment;
+
+/** Offset 0x01DA - PCIe ASPM programming will happen in relation to the Oprom
+ Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
+ Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
+ Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
+ 0:Before, 1:After
+**/
+ UINT8 InitPcieAspmAfterOprom;
+
+/** Offset 0x01DB - Selection of the primary display device
+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics
+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics
+**/
+ UINT8 PrimaryDisplay;
+
+/** Offset 0x01DC - Selection of PSMI Region size
+ 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
+ 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
+**/
+ UINT8 PsmiRegionSize;
+
+/** Offset 0x01DD
+**/
+ UINT8 UnusedUpdSpace6[3];
+
+/** Offset 0x01E0 - Temporary MMIO address for GMADR
+ Obsolete field now and it has been extended to 64 bit address, used GmAdr64
+**/
+ UINT32 GmAdr;
+
+/** Offset 0x01E4 - Temporary MMIO address for GTTMMADR
+ The reference code will use this as Temporary MMIO address space to access GTTMMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+ UINT32 GttMmAdr;
+
+/** Offset 0x01E8 - Selection of iGFX GTT Memory size
+ 1=2MB, 2=4MB, 3=8MB, Default is 3
+ 1:2MB, 2:4MB, 3:8MB
+**/
+ UINT16 GttSize;
+
+/** Offset 0x01EA
+**/
+ UINT8 UnusedUpdSpace7[2];
+
+/** Offset 0x01EC - Hybrid Graphics GPIO information for PEG 0
+ Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie0Rtd3Gpio[24];
+
+/** Offset 0x024C - Enable/Disable MRC TXT dependency
+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+ $EN_DIS
+**/
+ UINT8 TxtImplemented;
+
+/** Offset 0x024D - Enable/Disable SA OcSupport
+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+ $EN_DIS
+**/
+ UINT8 SaOcSupport;
+
+/** Offset 0x024E - GT slice Voltage Mode
+ 0(Default): Adaptive, 1: Override
+ 0: Adaptive, 1: Override
+**/
+ UINT8 GtVoltageMode;
+
+/** Offset 0x024F - Maximum GTs turbo ratio override
+ 0(Default)=Minimal/Auto, 60=Maximum
+**/
+ UINT8 GtMaxOcRatio;
+
+/** Offset 0x0250 - The voltage offset applied to GT slice
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 GtVoltageOffset;
+
+/** Offset 0x0252 - The GT slice voltage override which is applied to the entire range of GT frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtVoltageOverride;
+
+/** Offset 0x0254 - adaptive voltage applied during turbo frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtExtraTurboVoltage;
+
+/** Offset 0x0256 - voltage offset applied to the SA
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 SaVoltageOffset;
+
+/** Offset 0x0258 - PCIe root port Function number for Hybrid Graphics dGPU
+ Root port Index number to indicate which PCIe root port has dGPU
+**/
+ UINT8 RootPortIndex;
+
+/** Offset 0x0259 - Realtime Memory Timing
+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+ realtime memory timing changes after MRC_DONE.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 RealtimeMemoryTiming;
+
+/** Offset 0x025A - iTBT PCIe Multiple Segment setting
+ When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
+ TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieMultipleSegmentEnabled;
+
+/** Offset 0x025B - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
+**/
+ UINT8 SaIpuEnable;
+
+/** Offset 0x025C - IPU IMR Configuration
+ 0:IPU Camera, 1:IPU Gen Default is 0
+ 0:IPU Camera, 1:IPU Gen
+**/
+ UINT8 SaIpuImrConfiguration;
+
+/** Offset 0x025D - IMGU CLKOUT Configuration
+ The configuration of IMGU CLKOUT, 0: Disable;1: Enable.
+ $EN_DIS
+**/
+ UINT8 ImguClkOutEn[6];
+
+/** Offset 0x0263
+**/
+ UINT8 UnusedUpdSpace8;
+
+/** Offset 0x0264 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 CpuPcieRpEnableMask;
+
+/** Offset 0x0268 - Assertion on Link Down GPIOs
+ GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
+ GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
+ 0:Disable, 1:Enable
+**/
+ UINT8 CpuPcieRpLinkDownGpios;
+
+/** Offset 0x0269 - Enable ClockReq Messaging
+ ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default):
+ Enable ClockReq Messaging [ALIAS_NAME RpClockReqMsgEnable]
+ 0:Disable, 1:Enable
+**/
+ UINT8 CpuPcieRpClockReqMsgEnable;
+
+/** Offset 0x026A - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
+ 4: Gen4 (see: CPU_PCIE_SPEED). [ALIAS_NAME RpPcieThresholdBytes]
+**/
+ UINT8 CpuPcieRpPcieSpeed[4];
+
+/** Offset 0x026E - Selection of PSMI Support On/Off
+ 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
+ $EN_DIS
+**/
+ UINT8 GtPsmiSupport;
+
+/** Offset 0x026F - Selection of DiSM Region Size
+ DiSM Size to be allocated for 2LM Sku Default is 0
+ 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB
+**/
+ UINT8 DismSize;
+
+/** Offset 0x0270 - Enable Display memory map programming for DFD Restore
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DfdRestoreEnable;
+
+/** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device
+ 0=Disabled,1(Default)=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortAConfig;
+
+/** Offset 0x0272 - Program GPIOs for LFP on DDI port-B device
+ 0(Default)=Disabled,1=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortBConfig;
+
+/** Offset 0x0273 - Enable or disable HPD of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortAHpd;
+
+/** Offset 0x0274 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x0275 - Enable or disable HPD of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x0276 - Enable or disable HPD of DDI port 1
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Hpd;
+
+/** Offset 0x0277 - Enable or disable HPD of DDI port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Hpd;
+
+/** Offset 0x0278 - Enable or disable HPD of DDI port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Hpd;
+
+/** Offset 0x0279 - Enable or disable HPD of DDI port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Hpd;
+
+/** Offset 0x027A - Enable or disable DDC of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortADdc;
+
+/** Offset 0x027B - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x027C - Enable or disable DDC of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x027D - Enable DDC setting of DDI Port 1
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Ddc;
+
+/** Offset 0x027E - Enable DDC setting of DDI Port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Ddc;
+
+/** Offset 0x027F - Enable DDC setting of DDI Port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Ddc;
+
+/** Offset 0x0280 - Enable DDC setting of DDI Port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Ddc;
+
+/** Offset 0x0281 - Enable Gt CLOS
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 GtClosEnable;
+
+/** Offset 0x0282
+**/
+ UINT8 UnusedUpdSpace9[6];
+
+/** Offset 0x0288 - Temporary MMIO address for GMADR
+ The reference code will use this as Temporary MMIO address space to access GMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+ (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
+ - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB)
+**/
+ UINT64 GmAdr64;
+
+/** Offset 0x0290 - Hybrid Graphics Slot Selection
+ PEG or PCH Slot Selection for Hybrid Graphics
+**/
+ UINT8 HgSlot;
+
+/** Offset 0x0291 - DMI ASPM Configuration:{Combo
+ Set ASPM Configuration
+ 0:Disabled, 1:L0s, 2:L1, 3:L1L0s
+**/
+ UINT8 DmiAspm;
+
+/** Offset 0x0292 - DMI ASPM Control Configuration:{Combo
+ Set ASPM Control configuration
+ 0:Disabled, 1:L0s, 2:L1, 3:L1L0s
+**/
+ UINT8 DmiAspmCtrl;
+
+/** Offset 0x0293 - DMI ASPM L1 exit Latency
+ Range: 0-7, 4 is default L1 exit Latency
+**/
+ UINT8 DmiAspmL1ExitLatency;
+
+/** Offset 0x0294 - Per-core HT Disable
+ Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
+ 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value
+ of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have
+ HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1.
+**/
+ UINT16 PerCoreHtDisable;
+
+/** Offset 0x0296 - DEKEL CDR Relock
+ Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieRpCdrRelock[4];
+
+/** Offset 0x029A - Realtime Memory OverClock
+ Disable/Enables Realtime Memory OverClock
+ $EN_DIS
+**/
+ UINT8 RealtimeMemoryOC;
+
+/** Offset 0x029B - Xl1el
+ Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieNewFom[4];
+
+/** Offset 0x029F - Xl1el
+ Enable/Disable NewFomDisable. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieIotgMode[4];
+
+/** Offset 0x02A3 - SaPreMemProductionRsvd
+ Reserved for SA Pre-Mem Production
+ $EN_DIS
+**/
+ UINT8 SaPreMemProductionRsvd[87];
+
+/** Offset 0x02FA - DMI Max Link Speed
+ Auto (0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2):
+ Limit Link to Gen2 Speed, (Default) Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 DmiMaxLinkSpeed;
+
+/** Offset 0x02FB - DMI Equalization Phase 2
+ DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
+ AUTO - Use the current default method
+ 0:Disable phase2, 1:Enable phase2, 2:Auto
+**/
+ UINT8 DmiGen3EqPh2Enable;
+
+/** Offset 0x02FC - DMI Gen3 Equalization Phase3
+ DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 DmiGen3EqPh3Method;
+
+/** Offset 0x02FD - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+ Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiGen3ProgramStaticEq;
+
+/** Offset 0x02FE - DeEmphasis control for DMI
+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+ 0: -6dB, 1: -3.5dB
+**/
+ UINT8 DmiDeEmphasis;
+
+/** Offset 0x02FF - DMI Gen3 Root port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 DmiGen3RootPortPreset[8];
+
+/** Offset 0x0307 - DMI Gen3 End port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+ UINT8 DmiGen3EndPointPreset[8];
+
+/** Offset 0x030F - DMI Gen3 End port Hint values per lane
+ Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 DmiGen3EndPointHint[8];
+
+/** Offset 0x0317 - DMI Gen3 RxCTLEp per-Bundle control
+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
+**/
+ UINT8 DmiGen3RxCtlePeaking[4];
+
+/** Offset 0x031B - BIST on Reset
+ Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 BistOnReset;
+
+/** Offset 0x031C - Skip Stop PBET Timer Enable/Disable
+ Skip Stop PBET Timer; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 SkipStopPbet;
+
+/** Offset 0x031D - C6DRAM power gating feature
+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature.
+ $EN_DIS
+**/
+ UINT8 EnableC6Dram;
+
+/** Offset 0x031E - Over clocking support
+ Over clocking support; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcSupport;
+
+/** Offset 0x031F - Over clocking Lock
+ Over clocking Lock Enable/Disable; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcLock;
+
+/** Offset 0x0320 - Maximum Core Turbo Ratio Override
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the
+ fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85
+**/
+ UINT8 CoreMaxOcRatio;
+
+/** Offset 0x0321 - Core voltage mode
+ Core voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 CoreVoltageMode;
+
+/** Offset 0x0322 - Maximum clr turbo ratio override
+ Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+ fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85
+**/
+ UINT8 RingMaxOcRatio;
+
+/** Offset 0x0323 - Hyper Threading Enable/Disable
+ Enable or Disable Hyper Threading; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 HyperThreading;
+
+/** Offset 0x0324 - Enable or Disable CPU Ratio Override
+ Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CpuRatioOverride;
+
+/** Offset 0x0325 - CPU ratio value
+ CPU ratio value. Valid Range 0 to 63
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x0326 - Boot frequency
+ Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.
+ 1: Maximum non-turbo performance. 2: Turbo performance
+ 0:0, 1:1, 2:2
+**/
+ UINT8 BootFrequency;
+
+/** Offset 0x0327 - Number of active cores
+ Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2:
+ 2 ;3: 3
+ 0:All, 1:1, 2:2, 3:3
+**/
+ UINT8 ActiveCoreCount;
+
+/** Offset 0x0328 - Processor Early Power On Configuration FCLK setting
+ 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.-
+ 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x0329 - Set JTAG power in C10 and deeper power states
+ False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
+ and deeper power states for debug purpose. 0: False; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 JtagC10PowerGateDisable;
+
+/** Offset 0x032A - Enable or Disable VMX
+ Enable or Disable VMX; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x032B - AVX2 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx2RatioOffset;
+
+/** Offset 0x032C - AVX3 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx3RatioOffset;
+
+/** Offset 0x032D - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0:
+ Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
+/** Offset 0x032E - core voltage override
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageOverride;
+
+/** Offset 0x0330 - Core Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageAdaptive;
+
+/** Offset 0x0332 - Core Turbo voltage Offset
+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+ UINT16 CoreVoltageOffset;
+
+/** Offset 0x0334 - Core PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 CorePllVoltageOffset;
+
+/** Offset 0x0335 - Ring Downbin
+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+ lower than the core ratio.0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 RingDownBin;
+
+/** Offset 0x0336 - Ring voltage mode
+ Ring voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 RingVoltageMode;
+
+/** Offset 0x0337 - TjMax Offset
+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+ UINT8 TjMaxOffset;
+
+/** Offset 0x0338 - Ring voltage override
+ The ring voltage override which is applied to the entire range of cpu ring frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageOverride;
+
+/** Offset 0x033A - Ring Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageAdaptive;
+
+/** Offset 0x033C - Ring Turbo voltage Offset
+ The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
+**/
+ UINT16 RingVoltageOffset;
+
+/** Offset 0x033E - Enable or Disable TME
+ Enable or Disable TME; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TmeEnable;
+
+/** Offset 0x033F - Enable CPU CrashLog
+ Enable or Disable CPU CrashLog; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
+
+/** Offset 0x0340 - ElixirSpringsPatchAddr
+ DEPRECATED
+**/
+ UINT32 ElixirSpringsPatchAddr;
+
+/** Offset 0x0344 - ElixirSpringsPatchSize
+ DEPRECATED
+**/
+ UINT32 ElixirSpringsPatchSize;
+
+/** Offset 0x0348 - CPU Run Control
+ Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2:
+ No Change
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DebugInterfaceEnable;
+
+/** Offset 0x0349 - CPU Run Control Lock
+ Lock or Unlock CPU Run Control; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceLockEnable;
+
+/** Offset 0x034A - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x034B
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x034C - EnableSgx
+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
+ 0: Disable, 1: Enable, 2: Software Control
+**/
+ UINT8 EnableSgx;
+
+/** Offset 0x034D - Txt
+ Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 Txt;
+
+/** Offset 0x034E
+**/
+ UINT8 UnusedUpdSpace10[2];
+
+/** Offset 0x0350 - PrmrrSize
+ Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x0354 - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x0358 - TxtDprMemoryBase
+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+ UINT64 TxtDprMemoryBase;
+
+/** Offset 0x0360 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x0364 - TxtDprMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x0368 - BiosAcmBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 BiosAcmBase;
+
+/** Offset 0x036C - BiosAcmSize
+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+ UINT32 BiosAcmSize;
+
+/** Offset 0x0370 - ApStartupBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 ApStartupBase;
+
+/** Offset 0x0374 - TgaSize
+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+ UINT32 TgaSize;
+
+/** Offset 0x0378 - TxtLcpPdBase
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+ UINT64 TxtLcpPdBase;
+
+/** Offset 0x0380 - TxtLcpPdSize
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+ UINT64 TxtLcpPdSize;
+
+/** Offset 0x0388 - IsTPMPresence
+ IsTPMPresence default values
+**/
+ UINT8 IsTPMPresence;
+
+/** Offset 0x0389 - Configuration for boot TDP selection
+ Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP
+ Up;0xFF : Deactivate
+**/
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x038A - ReservedSecurityPreMem
+ Reserved for Security Pre-Mem
+ $EN_DIS
+**/
+ UINT8 ReservedSecurityPreMem[5];
+
+/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
+ Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtleEnable[24];
+
+/** Offset 0x03A7 - PCH HSIO PCIE Rx Set Ctle Value
+ PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtle[24];
+
+/** Offset 0x03BF - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
+
+/** Offset 0x03D7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
+
+/** Offset 0x03EF - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
+
+/** Offset 0x0407 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
+
+/** Offset 0x041F - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
+
+/** Offset 0x0437 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
+
+/** Offset 0x044F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
+
+/** Offset 0x0467 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+ PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmph[24];
+
+/** Offset 0x047F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
+
+/** Offset 0x0497 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
+
+/** Offset 0x04AF - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
+
+/** Offset 0x04C7 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
+
+/** Offset 0x04DF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
+
+/** Offset 0x04E7 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMag[8];
+
+/** Offset 0x04EF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
+
+/** Offset 0x04F7 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMag[8];
+
+/** Offset 0x04FF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
+
+/** Offset 0x0507 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMag[8];
+
+/** Offset 0x050F - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
+
+/** Offset 0x0517 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmp[8];
+
+/** Offset 0x051F - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
+
+/** Offset 0x0527 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmp[8];
+
+/** Offset 0x052F - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
+
+/** Offset 0x0537 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmp[8];
+
+/** Offset 0x053F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DeEmphEnable[8];
+
+/** Offset 0x0547 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen1DeEmph[8];
+
+/** Offset 0x054F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DeEmphEnable[8];
+
+/** Offset 0x0557 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen2DeEmph[8];
+
+/** Offset 0x055F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DeEmphEnable[8];
+
+/** Offset 0x0567 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen3DeEmph[8];
+
+/** Offset 0x056F - PCH LPC Enhanced Port 80 Decoding
+ Original LPC only decodes one byte of port 80h.
+ $EN_DIS
+**/
+ UINT8 PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x0570 - PCH Port80 Route
+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+ 0:LPC, 1:PCI
+**/
+ UINT8 PchPort80Route;
+
+/** Offset 0x0571 - Enable SMBus ARP support
+ Enable SMBus ARP support.
+ $EN_DIS
+**/
+ UINT8 SmbusArpEnable;
+
+/** Offset 0x0572 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0573
+**/
+ UINT8 UnusedUpdSpace11;
+
+/** Offset 0x0574 - SMBUS Base Address
+ SMBUS Base Address (IO space).
+**/
+ UINT16 PchSmbusIoBase;
+
+/** Offset 0x0576 - Enable SMBus Alert Pin
+ Enable SMBus Alert Pin.
+ $EN_DIS
+**/
+ UINT8 PchSmbAlertEnable;
+
+/** Offset 0x0577 - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+ (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[16];
+
+/** Offset 0x0587 - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[16];
+
+/** Offset 0x0597
+**/
+ UINT8 UnusedUpdSpace12;
+
+/** Offset 0x0598 - Point of RsvdSmbusAddressTable
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+ UINT32 RsvdSmbusAddressTablePtr;
+
+/** Offset 0x059C - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x05A0 - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x05A1 - Serial Io Uart Debug Controller Number
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 SerialIoUartDebugControllerNumber;
+
+/** Offset 0x05A2 - Serial Io Uart Debug Auto Flow
+ Enables UART hardware flow control, CTS and RTS lines.
+ $EN_DIS
+**/
+ UINT8 SerialIoUartDebugAutoFlow;
+
+/** Offset 0x05A3
+**/
+ UINT8 UnusedUpdSpace13;
+
+/** Offset 0x05A4 - Serial Io Uart Debug BaudRate
+ Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+ 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+ UINT32 SerialIoUartDebugBaudRate;
+
+/** Offset 0x05A8 - Serial Io Uart Debug Parity
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartDebugParity;
+
+/** Offset 0x05A9 - Serial Io Uart Debug Stop Bits
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 SerialIoUartDebugStopBits;
+
+/** Offset 0x05AA - Serial Io Uart Debug Data Bits
+ Set default word length. 0: Default, 5,6,7,8
+ 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+ UINT8 SerialIoUartDebugDataBits;
+
+/** Offset 0x05AB
+**/
+ UINT8 UnusedUpdSpace14;
+
+/** Offset 0x05AC - Serial Io Uart Debug Mmio Base
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 SerialIoUartDebugMmioBase;
+
+/** Offset 0x05B0 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x05B1 - GT PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 GtPllVoltageOffset;
+
+/** Offset 0x05B2 - Ring PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 RingPllVoltageOffset;
+
+/** Offset 0x05B3 - System Agent PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 SaPllVoltageOffset;
+
+/** Offset 0x05B4 - Memory Controller PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 McPllVoltageOffset;
+
+/** Offset 0x05B5 - MRC Safe Config
+ Enables/Disable MRC Safe Config
+ $EN_DIS
+**/
+ UINT8 MrcSafeConfig;
+
+/** Offset 0x05B6 - TCSS Thunderbolt PCIE Root Port 0 Enable
+ Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie0En;
+
+/** Offset 0x05B7 - TCSS Thunderbolt PCIE Root Port 1 Enable
+ Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie1En;
+
+/** Offset 0x05B8 - TCSS Thunderbolt PCIE Root Port 2 Enable
+ Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie2En;
+
+/** Offset 0x05B9 - TCSS Thunderbolt PCIE Root Port 3 Enable
+ Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie3En;
+
+/** Offset 0x05BA - TCSS USB HOST (xHCI) Enable
+ Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
+ $EN_DIS
+**/
+ UINT8 TcssXhciEn;
+
+/** Offset 0x05BB - TCSS USB DEVICE (xDCI) Enable
+ Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
+ $EN_DIS
+**/
+ UINT8 TcssXdciEn;
+
+/** Offset 0x05BC - TCSS DMA0 Enable
+ Set TCSS DMA0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma0En;
+
+/** Offset 0x05BD - TCSS DMA1 Enable
+ Set TCSS DMA1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma1En;
+
+/** Offset 0x05BE - PcdSerialDebugBaudRate
+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+ 3:9600, 4:19200, 6:56700, 7:115200
+**/
+ UINT8 PcdSerialDebugBaudRate;
+
+/** Offset 0x05BF - HobBufferSize
+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+ total HOB size).
+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+ UINT8 HobBufferSize;
+
+/** Offset 0x05C0 - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x05C1 - SenseAmp Offset Training
+ Enables/Disable SenseAmp Offset Training
+ $EN_DIS
+**/
+ UINT8 SOT;
+
+/** Offset 0x05C2 - Early ReadMPR Timing Centering 2D
+ Enables/Disable Early ReadMPR Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDMPRTC2D;
+
+/** Offset 0x05C3 - Read MPR Training
+ Enables/Disable Read MPR Training
+ $EN_DIS
+**/
+ UINT8 RDMPRT;
+
+/** Offset 0x05C4 - Receive Enable Training
+ Enables/Disable Receive Enable Training
+ $EN_DIS
+**/
+ UINT8 RCVET;
+
+/** Offset 0x05C5 - Jedec Write Leveling
+ Enables/Disable Jedec Write Leveling
+ $EN_DIS
+**/
+ UINT8 JWRL;
+
+/** Offset 0x05C6 - Early Write Time Centering 2D
+ Enables/Disable Early Write Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 EWRTC2D;
+
+/** Offset 0x05C7 - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDTC2D;
+
+/** Offset 0x05C8 - Write Timing Centering 1D
+ Enables/Disable Write Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRTC1D;
+
+/** Offset 0x05C9 - Write Voltage Centering 1D
+ Enables/Disable Write Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRVC1D;
+
+/** Offset 0x05CA - Read Timing Centering 1D
+ Enables/Disable Read Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDTC1D;
+
+/** Offset 0x05CB - Dimm ODT Training
+ Enables/Disable Dimm ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTT;
+
+/** Offset 0x05CC - DIMM RON Training
+ Enables/Disable DIMM RON Training
+ $EN_DIS
+**/
+ UINT8 DIMMRONT;
+
+/** Offset 0x05CD - Write Drive Strength/Equalization 2D
+ Enables/Disable Write Drive Strength/Equalization 2D
+ $EN_DIS
+**/
+ UINT8 WRDSEQT;
+
+/** Offset 0x05CE - Write Slew Rate Training
+ Enables/Disable Write Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 WRSRT;
+
+/** Offset 0x05CF - Read ODT Training
+ Enables/Disable Read ODT Training
+ $EN_DIS
+**/
+ UINT8 RDODTT;
+
+/** Offset 0x05D0 - Read Equalization Training
+ Enables/Disable Read Equalization Training
+ $EN_DIS
+**/
+ UINT8 RDEQT;
+
+/** Offset 0x05D1 - Read Amplifier Training
+ Enables/Disable Read Amplifier Training
+ $EN_DIS
+**/
+ UINT8 RDAPT;
+
+/** Offset 0x05D2 - Write Timing Centering 2D
+ Enables/Disable Write Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRTC2D;
+
+/** Offset 0x05D3 - Read Timing Centering 2D
+ Enables/Disable Read Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDTC2D;
+
+/** Offset 0x05D4 - Write Voltage Centering 2D
+ Enables/Disable Write Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRVC2D;
+
+/** Offset 0x05D5 - Read Voltage Centering 2D
+ Enables/Disable Read Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDVC2D;
+
+/** Offset 0x05D6 - Command Voltage Centering
+ Enables/Disable Command Voltage Centering
+ $EN_DIS
+**/
+ UINT8 CMDVC;
+
+/** Offset 0x05D7 - Late Command Training
+ Enables/Disable Late Command Training
+ $EN_DIS
+**/
+ UINT8 LCT;
+
+/** Offset 0x05D8 - Round Trip Latency Training
+ Enables/Disable Round Trip Latency Training
+ $EN_DIS
+**/
+ UINT8 RTL;
+
+/** Offset 0x05D9 - Turn Around Timing Training
+ Enables/Disable Turn Around Timing Training
+ $EN_DIS
+**/
+ UINT8 TAT;
+
+/** Offset 0x05DA - Memory Test
+ Enables/Disable Memory Test
+ $EN_DIS
+**/
+ UINT8 MEMTST;
+
+/** Offset 0x05DB - DIMM SPD Alias Test
+ Enables/Disable DIMM SPD Alias Test
+ $EN_DIS
+**/
+ UINT8 ALIASCHK;
+
+/** Offset 0x05DC - Receive Enable Centering 1D
+ Enables/Disable Receive Enable Centering 1D
+ $EN_DIS
+**/
+ UINT8 RCVENC1D;
+
+/** Offset 0x05DD - Retrain Margin Check
+ Enables/Disable Retrain Margin Check
+ $EN_DIS
+**/
+ UINT8 RMC;
+
+/** Offset 0x05DE - Write Drive Strength Up/Dn independently
+ Enables/Disable Write Drive Strength Up/Dn independently
+ $EN_DIS
+**/
+ UINT8 WRDSUDT;
+
+/** Offset 0x05DF - ECC Support
+ Enables/Disable ECC Support
+ $EN_DIS
+**/
+ UINT8 EccSupport;
+
+/** Offset 0x05E0 - Ibecc
+ In-Band ECC Support
+ $EN_DIS
+**/
+ UINT8 Ibecc;
+
+/** Offset 0x05E1 - IbeccParity
+ In-Band ECC Parity Control
+ $EN_DIS
+**/
+ UINT8 IbeccParity;
+
+/** Offset 0x05E2 - IbeccOperationMode
+ In-Band ECC Operation Mode
+ 0:Protect base on address range, 1: Non-protected, 2: All protected
+**/
+ UINT8 IbeccOperationMode;
+
+/** Offset 0x05E3 - IbeccProtectedRegionEnable
+ In-Band ECC Protected Region Enable
+ $EN_DIS
+**/
+ UINT8 IbeccProtectedRegionEnable[8];
+
+/** Offset 0x05EB
+**/
+ UINT8 UnusedUpdSpace15[1];
+
+/** Offset 0x05EC - IbeccProtectedRegionBases
+ IBECC Protected Region Bases
+**/
+ UINT16 IbeccProtectedRegionBase[8];
+
+/** Offset 0x05FC - IbeccProtectedRegionMasks
+ IBECC Protected Region Masks
+**/
+ UINT16 IbeccProtectedRegionMask[8];
+
+/** Offset 0x060C - Memory Remap
+ Enables/Disable Memory Remap
+ $EN_DIS
+**/
+ UINT8 RemapEnable;
+
+/** Offset 0x060D - Rank Interleave support
+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+ the same time.
+ $EN_DIS
+**/
+ UINT8 RankInterleave;
+
+/** Offset 0x060E - Enhanced Interleave support
+ Enables/Disable Enhanced Interleave support
+ $EN_DIS
+**/
+ UINT8 EnhancedInterleave;
+
+/** Offset 0x060F - Ch Hash Support
+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT8 ChHashEnable;
+
+/** Offset 0x0610 - Extern Therm Status
+ Enables/Disable Extern Therm Status
+ $EN_DIS
+**/
+ UINT8 EnableExtts;
+
+/** Offset 0x0611 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDn;
+
+/** Offset 0x0612 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDnLpddr;
+
+/** Offset 0x0613 - SelfRefresh Enable
+ Enables/Disable SelfRefresh Enable
+ $EN_DIS
+**/
+ UINT8 SrefCfgEna;
+
+/** Offset 0x0614 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x0615 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeat;
+
+/** Offset 0x0616 - Enable RH Prevention
+ Enables/Disable RH Prevention
+ $EN_DIS
+**/
+ UINT8 RhPrevention;
+
+/** Offset 0x0617 - Exit On Failure (MRC)
+ Enables/Disable Exit On Failure (MRC)
+ $EN_DIS
+**/
+ UINT8 ExitOnFailure;
+
+/** Offset 0x0618 - New Features 1 - MRC
+ New Feature Enabling 1, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 NewFeatureEnable1;
+
+/** Offset 0x0619 - New Features 2 - MRC
+ New Feature Enabling 2, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 NewFeatureEnable2;
+
+/** Offset 0x061A - Duty Cycle Correction Training
+ Enable/Disable Duty Cycle Correction Training
+ $EN_DIS
+**/
+ UINT8 DCC;
+
+/** Offset 0x061B - Read Voltage Centering 1D
+ Enable/Disable Read Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDVC1D;
+
+/** Offset 0x061C - TxDqTCO Comp Training
+ Enable/Disable TxDqTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCO;
+
+/** Offset 0x061D - ClkTCO Comp Training
+ Enable/Disable ClkTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 CLKTCO;
+
+/** Offset 0x061E - CMD Slew Rate Training
+ Enable/Disable CMD Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 CMDSR;
+
+/** Offset 0x061F - CMD Drive Strength and Tx Equalization
+ Enable/Disable CMD Drive Strength and Tx Equalization
+ $EN_DIS
+**/
+ UINT8 CMDDSEQ;
+
+/** Offset 0x0620 - DIMM CA ODT Training
+ Enable/Disable DIMM CA ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTCA;
+
+/** Offset 0x0621 - TxDqsTCO Comp Training
+ Enable/Disable TxDqsTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCODQS;
+
+/** Offset 0x0622 - CMD/CTL Drive Strength Up/Dn 2D
+ Enable/Disable CMD/CTL Drive Strength Up/Dn 2D
+ $EN_DIS
+**/
+ UINT8 CMDDRUD;
+
+/** Offset 0x0623 - VccDLL Bypass Training
+ Enable/Disable VccDLL Bypass Training
+ $EN_DIS
+**/
+ UINT8 VCCDLLBP;
+
+/** Offset 0x0624 - PanicVttDnLp Training
+ Enable/Disable PanicVttDnLp Training
+ $EN_DIS
+**/
+ UINT8 PVTTDNLP;
+
+/** Offset 0x0625 - Read Vref Decap Training*
+ Enable/Disable Read Vref Decap Training*
+ $EN_DIS
+**/
+ UINT8 RDVREFDC;
+
+/** Offset 0x0626 - Vddq Training
+ Enable/Disable Vddq Training
+ $EN_DIS
+**/
+ UINT8 VDDQT;
+
+/** Offset 0x0627 - Rank Margin Tool Per Bit
+ Enable/Disable Rank Margin Tool Per Bit
+ $EN_DIS
+**/
+ UINT8 RMTBIT;
+
+/** Offset 0x0628 - Override Performance Downgrade for Mixed Memory
+ Disable/Enables Override Performance Downgrade for Mixed Memory
+ $EN_DIS
+**/
+ UINT8 OverrideDowngradeForMixedMemory;
+
+/** Offset 0x0629
+**/
+ UINT8 Reserved2[1];
+
+/** Offset 0x062A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedClock;
+
+/** Offset 0x062B - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedZq;
+
+/** Offset 0x062C - Ch Hash Interleaved Bit
+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+ UINT8 ChHashInterleaveBit;
+
+/** Offset 0x062D
+**/
+ UINT8 UnusedUpdSpace16;
+
+/** Offset 0x062E - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6] Default is 0x0830
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x0630 - Base reference clock value
+ Base reference clock value, in Hertz(Default is 100Hz)
+ 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
+**/
+ UINT32 BClkFrequency;
+
+/** Offset 0x0634 - EPG DIMM Idd3N
+ Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
+ a per DIMM basis. Default is 26
+**/
+ UINT16 Idd3n;
+
+/** Offset 0x0636 - EPG DIMM Idd3P
+ Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
+ on a per DIMM basis. Default is 11
+**/
+ UINT16 Idd3p;
+
+/** Offset 0x0638 - RH Activation Probability
+ RH Activation Probability, Probability value is 1/2^(inputvalue)
+**/
+ UINT8 RhActProbability;
+
+/** Offset 0x0639 - Idle Energy Mc0Ch0Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch0Dimm0;
+
+/** Offset 0x063A - Idle Energy Mc0Ch0Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch0Dimm1;
+
+/** Offset 0x063B - Idle Energy Mc0Ch1Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch1Dimm0;
+
+/** Offset 0x063C - Idle Energy Mc0Ch1Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch1Dimm1;
+
+/** Offset 0x063D - Idle Energy Mc1Ch0Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch0Dimm0;
+
+/** Offset 0x063E - Idle Energy Mc1Ch0Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch0Dimm1;
+
+/** Offset 0x063F - Idle Energy Mc1Ch1Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0640 - Idle Energy Mc1Ch1Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0641 - PowerDown Energy Mc0Ch0Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch0Dimm0;
+
+/** Offset 0x0642 - PowerDown Energy Mc0Ch0Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch0Dimm1;
+
+/** Offset 0x0643 - PowerDown Energy Mc0Ch1Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch1Dimm0;
+
+/** Offset 0x0644 - PowerDown Energy Mc0Ch1Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch1Dimm1;
+
+/** Offset 0x0645 - PowerDown Energy Mc1Ch0Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch0Dimm0;
+
+/** Offset 0x0646 - PowerDown Energy Mc1Ch0Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch0Dimm1;
+
+/** Offset 0x0647 - PowerDown Energy Mc1Ch1Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0648 - PowerDown Energy Mc1Ch1Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0649 - Activate Energy Mc0Ch0Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch0Dimm0;
+
+/** Offset 0x064A - Activate Energy Mc0Ch0Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch0Dimm1;
+
+/** Offset 0x064B - Activate Energy Mc0Ch1Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch1Dimm0;
+
+/** Offset 0x064C - Activate Energy Mc0Ch1Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch1Dimm1;
+
+/** Offset 0x064D - Activate Energy Mc1Ch0Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch0Dimm0;
+
+/** Offset 0x064E - Activate Energy Mc1Ch0Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch0Dimm1;
+
+/** Offset 0x064F - Activate Energy Mc1Ch1Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0650 - Activate Energy Mc1Ch1Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0651 - Read Energy Mc0Ch0Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch0Dimm0;
+
+/** Offset 0x0652 - Read Energy Mc0Ch0Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch0Dimm1;
+
+/** Offset 0x0653 - Read Energy Mc0Ch1Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch1Dimm0;
+
+/** Offset 0x0654 - Read Energy Mc0Ch1Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch1Dimm1;
+
+/** Offset 0x0655 - Read Energy Mc1Ch0Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch0Dimm0;
+
+/** Offset 0x0656 - Read Energy Mc1Ch0Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch0Dimm1;
+
+/** Offset 0x0657 - Read Energy Mc1Ch1Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0658 - Read Energy Mc1Ch1Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0659 - Write Energy Mc0Ch0Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch0Dimm0;
+
+/** Offset 0x065A - Write Energy Mc0Ch0Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch0Dimm1;
+
+/** Offset 0x065B - Write Energy Mc0Ch1Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch1Dimm0;
+
+/** Offset 0x065C - Write Energy Mc0Ch1Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch1Dimm1;
+
+/** Offset 0x065D - Write Energy Mc1Ch0Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch0Dimm0;
+
+/** Offset 0x065E - Write Energy Mc1Ch0Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch0Dimm1;
+
+/** Offset 0x065F - Write Energy Mc1Ch1Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0660 - Write Energy Mc1Ch1Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0661 - Throttler CKEMin Timer
+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+ Dfault is 0x00
+**/
+ UINT8 ThrtCkeMinTmr;
+
+/** Offset 0x0662 - Rapl Power Floor Ch0
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh0;
+
+/** Offset 0x0663 - Rapl Power Floor Ch1
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh1;
+
+/** Offset 0x0664 - Command Rate Support
+ CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
+ 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
+**/
+ UINT8 EnCmdRate;
+
+/** Offset 0x0665 - REFRESH_2X_MODE
+ 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
+ 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
+**/
+ UINT8 Refresh2X;
+
+/** Offset 0x0666 - Energy Performance Gain
+ Enable/disable(default) Energy Performance Gain.
+ $EN_DIS
+**/
+ UINT8 EpgEnable;
+
+/** Offset 0x0667 - Row Hammer Solution
+ Type of method used to prevent Row Hammer. Default is Hardware RHP
+ 0:Hardware RHP, 1:2x Refresh
+**/
+ UINT8 RhSolution;
+
+/** Offset 0x0668 - User Manual Threshold
+ Disabled: Predefined threshold will be used.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserThresholdEnable;
+
+/** Offset 0x0669 - User Manual Budget
+ Disabled: Configuration of memories will defined the Budget value.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserBudgetEnable;
+
+/** Offset 0x066A - Power Down Mode
+ This option controls command bus tristating during idle periods
+ 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
+**/
+ UINT8 PowerDownMode;
+
+/** Offset 0x066B - Pwr Down Idle Timer
+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+ AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+ UINT8 PwdwnIdleCounter;
+
+/** Offset 0x066C - Page Close Idle Timeout
+ This option controls Page Close Idle Timeout
+ 0:Enabled, 1:Disabled
+**/
+ UINT8 DisPgCloseIdleTimeout;
+
+/** Offset 0x066D - Bitmask of ranks that have CA bus terminated
+ Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default,
+ Rank0 is terminating and Rank1 is non-terminating
+**/
+ UINT8 CmdRanksTerminated;
+
+/** Offset 0x066E - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x066F - Fivr Faults
+ Fivr Faults; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 FivrFaults;
+
+/** Offset 0x0670 - Fivr Efficiency
+ Fivr Efficiency Management; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 FivrEfficiency;
+
+/** Offset 0x0671 - Safe Mode Support
+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+ $EN_DIS
+**/
+ UINT8 SafeMode;
+
+/** Offset 0x0672 - Ask MRC to clear memory content
+ Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x0673 - LpDdrDqDqsReTraining
+ Enables/Disable LpDdrDqDqsReTraining
+ $EN_DIS
+**/
+ UINT8 LpDdrDqDqsReTraining;
+
+/** Offset 0x0674 - TCSS USB Port Enable
+ Bitmap for per port enabling
+**/
+ UINT8 UsbTcPortEnPreMem;
+
+/** Offset 0x0675
+**/
+ UINT8 UnusedUpdSpace17;
+
+/** Offset 0x0676 - Post Code Output Port
+ This option configures Post Code Output Port
+**/
+ UINT16 PostCodeOutputPort;
+
+/** Offset 0x0678 - RMTLoopCount
+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+ UINT8 RMTLoopCount;
+
+/** Offset 0x0679 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
+/** Offset 0x067A - WRC Feature
+ Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports
+ IO devices allocating onto the ring and into LLC. WRC is fused on by default.
+ $EN_DIS
+**/
+ UINT8 WrcFeatureEnable;
+
+/** Offset 0x067B
+**/
+ UINT8 UnusedUpdSpace18[1];
+
+/** Offset 0x067C - BCLK RFI Frequency
+ Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No
+ RFI Tuning. Range is 98Mhz-100Mhz.
+**/
+ UINT32 BclkRfiFreq[4];
+
+/** Offset 0x068C - Size of PCIe IMR.
+ Size of PCIe IMR in megabytes
+**/
+ UINT16 PcieImrSize;
+
+/** Offset 0x068E - Enable PCIe IMR
+ 0: Disable(AUTO), 1: Enable
+ $EN_DIS
+**/
+ UINT8 PcieImrEnabled;
+
+/** Offset 0x068F - Enable PCIe IMR
+ 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
+ the Root port location from PCH PCIe or SA PCIe
+ $EN_DIS
+**/
+ UINT8 PcieImrRpLocation;
+
+/** Offset 0x0690 - Root port number for IMR.
+ Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
+ from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
+**/
+ UINT8 PcieImrRpSelection;
+
+/** Offset 0x0691 - SerialDebugMrcLevel
+ MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 SerialDebugMrcLevel;
+
+/** Offset 0x0692 - Mem Boot Mode
+ 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
+ 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
+**/
+ UINT8 MemBootMode;
+
+/** Offset 0x0693 - PCIe ASPM programming will happen in relation to the Oprom
+ This option is specifically needed for ASPM configuration in 2LM feature
+ 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto
+**/
+ UINT8 Peg3Aspm;
+
+/** Offset 0x0694 - MFVC WRR VC Arbitration
+ 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES
+ 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES
+**/
+ UINT8 MfvcWrrArb;
+
+/** Offset 0x0695 - BZM Support
+ 1: enable, 0: disable(Default), Enable/disable setting for Boot-time Zero Memory support
+ $EN_DIS
+**/
+ UINT8 BzmSupport;
+
+/** Offset 0x0696 - VcId_7_0 values
+ Select VC ID for arbitration
+**/
+ UINT8 VcId_7_0[16];
+
+/** Offset 0x06A6 - Set Hw Parameters enable/disable
+ 1: enable, 0: disable, Enable/disable setting of HW parameters
+ $EN_DIS
+**/
+ UINT8 SetHwParameters;
+
+/** Offset 0x06A7
+**/
+ UINT8 UnusedUpdSpace19;
+
+/** Offset 0x06A8 - LTR L1.2 Threshold Value
+ LTR L1.2 Threshold Value
+**/
+ UINT16 Ltr_L1D2_ThVal;
+
+/** Offset 0x06AA - LTR L1.2 Threshold Scale
+ LTR L1.2 Threshold Scale
+**/
+ UINT8 Ltr_L1D2_ThScale;
+
+/** Offset 0x06AB - system power state
+ system power state indicates the platform power state
+**/
+ UINT8 SysPwrState;
+
+/** Offset 0x06AC - Media Death Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Media Death Notification
+ $EN_DIS
+**/
+ UINT8 MediaDeathNotification;
+
+/** Offset 0x06AD - Health Log Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Health Log Notification
+ $EN_DIS
+**/
+ UINT8 HealthLogNotification;
+
+/** Offset 0x06AE - Temp crosses below TempThrottle Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification
+ $EN_DIS
+**/
+ UINT8 TempBelowThrottleNotification;
+
+/** Offset 0x06AF - Temp crosses above TempThrottle Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification
+ $EN_DIS
+**/
+ UINT8 TempAboveThrottleNotification;
+
+/** Offset 0x06B0 - Missing Commit Bit Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification
+ $EN_DIS
+**/
+ UINT8 MissingCommitBitNotification;
+
+/** Offset 0x06B1 - NVMeHoldDisableBit
+ 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit
+ $EN_DIS
+**/
+ UINT8 NVMeHoldDisableBit;
+
+/** Offset 0x06B2 - Ddr4OneDpc
+ DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+ or on both (default)
+ 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
+**/
+ UINT8 Ddr4OneDpc;
+
+/** Offset 0x06B3 - Ch Hash Override POR settings
+ Enable/Disable Override Channel Hash Support POR values
+ $EN_DIS
+**/
+ UINT8 ChHashOverride;
+
+/** Offset 0x06B4 - PDA Enumeration
+ Enables/Disable PDA Enumeration
+ $EN_DIS
+**/
+ UINT8 PDA;
+
+/** Offset 0x06B5 - DPin Policy
+ Set DPin Policy. Internal Only:All display ports are for internal only. External
+ First:All display ports are for external only, if there is no External DP-In presence
+ presents then IOM will use all ports internal only
+ 0: Internal Only, 1: External First
+**/
+ UINT8 DpInExternalEn;
+
+/** Offset 0x06B6 - DPin External Ports Number
+ Total number of External Gfx DpIn Port present on Board. Currently hardware wise
+ max 0x04 DpIn port supported, however DpIn module can handle upto 0x08 DpIn ports
+**/
+ UINT8 NumberOfDpInPort;
+
+/** Offset 0x06B7 - DPin External Port Connect Map
+ Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port.
+**/
+ UINT8 DpInPortConnectMap;
+
+/** Offset 0x06B8 - Command Pins Mapping
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
+**/
+ UINT8 Lp5CccConfig[4];
+
+/** Offset 0x06BC - Command Pins Mirrored
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+**/
+ UINT32 CmdMirror[1];
+
+/** Offset 0x06C0 - CPU BCLK SSC Enable
+ Enable/Disable CPU BCLK Spread Spectrum. Default is Enabled.
+ $EN_DIS
+**/
+ UINT8 CpuBclkSpread;
+
+/** Offset 0x06C1 - McParity
+ CMI/MC Parity Control
+ $EN_DIS
+**/
+ UINT8 McParity;
+
+/** Offset 0x06C2 - Vddq Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 VddqVoltageOverride;
+
+/** Offset 0x06C4 - Extended Bank Hashing
+ Eanble/Disable ExtendedBankHashing
+ $EN_DIS
+**/
+ UINT8 ExtendedBankHashing;
+
+/** Offset 0x06C5 - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x06C6 - Generate BIOS Data ACPI Table
+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+ $EN_DIS
+**/
+ UINT8 BdatEnable;
+
+/** Offset 0x06C7 - Detect External Graphics device for LegacyOpROM
+ Detect and report if external graphics device only support LegacyOpROM or not (to
+ support CSM auto-enable). Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 ScanExtGfxForLegacyOpRom;
+
+/** Offset 0x06C8 - Lock PCU Thermal Management registers
+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 LockPTMregs;
+
+/** Offset 0x06C9 - Rsvd
+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+ peak values unmodified
+ $EN_DIS
+**/
+ UINT8 PegGen3Rsvd;
+
+/** Offset 0x06CA - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x06CB - BdatTestType
+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+ 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+ UINT8 BdatTestType;
+
+/** Offset 0x06CC - PMR Size
+ Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
+**/
+ UINT32 DmaBufferSize;
+
+/** Offset 0x06D0 - VT-d/IOMMU Boot Policy
+ BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
+**/
+ UINT8 PreBootDmaMask;
+
+/** Offset 0x06D1 - Enable/Disable DMI GEN3 Hardware Eq
+ Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default):
+ Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiHweq;
+
+/** Offset 0x06D2 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass
+ CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
+ Enable Phase 23 Bypass
+ $EN_DIS
+**/
+ UINT8 Gen3EqPhase23Bypass;
+
+/** Offset 0x06D3 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass
+ CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
+ Enable Phase 3 Bypass
+ $EN_DIS
+**/
+ UINT8 Gen3EqPhase3Bypass;
+
+/** Offset 0x06D4 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+ Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
+ Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter
+ Coefficient Override
+ $EN_DIS
+**/
+ UINT8 Gen3LtcoEnable;
+
+/** Offset 0x06D5 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+ Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+ Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote
+ Transmitter Coefficient/Preset Override
+ $EN_DIS
+**/
+ UINT8 Gen3RtcoRtpoEnable;
+
+/** Offset 0x06D6 - DMI Gen3 Transmitter Pre-Cursor Coefficient
+ Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+ 2 is default for each lane
+**/
+ UINT8 DmiGen3Ltcpre[8];
+
+/** Offset 0x06DE - DMI Gen3 Transmitter Post-Cursor Coefficient
+ Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
+ for each lane
+**/
+ UINT8 DmiGen3Ltcpo[8];
+
+/** Offset 0x06E6 - PCIE Hw Eq Gen3 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuDmiHwEqGen3CoeffListCm[8];
+
+/** Offset 0x06EE - PCIE Hw Eq Gen3 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuDmiHwEqGen3CoeffListCp[8];
+
+/** Offset 0x06F6 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
+ Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
+ Manual(0x1): Enable DmiGen3DsPresetEnable
+ $EN_DIS
+**/
+ UINT8 DmiGen3DsPresetEnable;
+
+/** Offset 0x06F7 - DMI Gen3 Root port preset Rx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
+ for each lane
+**/
+ UINT8 DmiGen3DsPortRxPreset[8];
+
+/** Offset 0x06FF - DMI Gen3 Root port preset Tx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
+ for each lane
+**/
+ UINT8 DmiGen3DsPortTxPreset[8];
+
+/** Offset 0x0707 - Program DMI GEN3 Extended number of VC
+ (DEPRECATED)
+**/
+ UINT8 DmiGen3MultiVC;
+
+/** Offset 0x0708 - Enable/Disable DMI GEN3 DmiGen3Vc1Control
+ (DEPRECATED)
+ $EN_DIS
+**/
+ UINT8 DmiGen3Vc1Control;
+
+/** Offset 0x0709 - Enable/Disable DMI GEN3 DmiGen3VcMControl
+ (DEPRECATED)
+ $EN_DIS
+**/
+ UINT8 DmiGen3VcMControl;
+
+/** Offset 0x070A - DMI Secure Register Lock:{Combo
+ (DEPRECATED)
+ 0:Disable, 1:Enable
+**/
+ UINT8 DmiSrl;
+
+/** Offset 0x070B - DMI Scramble Enable:{Combo
+ (DEPRECATED)
+ 0:Disable, 1:Enable
+**/
+ UINT8 DmiScramble;
+
+/** Offset 0x070C - DMI Max Payload Size:{Combo
+ (DEPRECATED)
+ 0:Auto, 1:128 TLP, 2:256 TLP
+**/
+ UINT8 DmiMaxPayload;
+
+/** Offset 0x070D - DPin Dynamic Switch Policy
+ Dynamic one-time switch from iGFx to dGFx after boot to OS
+ 0: Disble, 1: Enable
+**/
+ UINT8 DPinDynamicSwitch;
+
+/** Offset 0x070E - Delay before sending commn
+ Delay before sending dynamic one-time switch cmd to IOM, ACPI BIOS consumes this
+ value and proceed delay when _DSM is invoked: 0=Minimal, 5000=Maximum, default
+ is 0 second
+**/
+ UINT16 DPinDynamicSwitchDelay0;
+
+/** Offset 0x0710 - Delay before IOM de-assert HPD
+ Delay before IOM de-assert HPD, ACPI BIOS passes this value to IOM when sending
+ dynamic one-time switch command: 1000=Minimal, 5000=Maximum, default is 1000 = 1 second
+**/
+ UINT16 DPinDynamicSwitchDelay1;
+
+/** Offset 0x0712 - SaPreMemTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPreMemTestRsvd[28];
+
+/** Offset 0x072E - TotalFlashSize
+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+ UINT16 TotalFlashSize;
+
+/** Offset 0x0730 - BiosSize
+ The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
+ 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
+ Range) so that a BIOS Update Script can be stored in the DPR.
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x0732 - SecurityTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SecurityTestRsvd[12];
+
+/** Offset 0x073E - Smbus dynamic power gating
+ Disable or Enable Smbus dynamic power gating.
+ $EN_DIS
+**/
+ UINT8 SmbusDynamicPowerGating;
+
+/** Offset 0x073F - Disable and Lock Watch Dog Register
+ Set 1 to clear WDT status, then disable and lock WDT registers.
+ $EN_DIS
+**/
+ UINT8 WdtDisableAndLock;
+
+/** Offset 0x0740 - SMBUS SPD Write Disable
+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+ Disable bit. For security recommendations, SPD write disable bit must be set.
+ $EN_DIS
+**/
+ UINT8 SmbusSpdWriteDisable;
+
+/** Offset 0x0741 - VC Type
+ Virtual Channel Type Select: 0: VC0, 1: VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 PchHdaVcType;
+
+/** Offset 0x0742 - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
+
+/** Offset 0x0743 - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x0744 - Enable HDA SDI lanes
+ Enable/disable HDA SDI lanes.
+**/
+ UINT8 PchHdaSdiEnable[2];
+
+/** Offset 0x0746 - HDA Power/Clock Gating (PGD/CGD)
+ Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
+ FORCE_ENABLE, 2: FORCE_DISABLE.
+ 0: POR, 1: Force Enable, 2: Force Disable
+**/
+ UINT8 PchHdaTestPowerClockGating;
+
+/** Offset 0x0747 - Enable HD Audio DMIC_N Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+ UINT8 PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x0749
+**/
+ UINT8 UnusedUpdSpace20[3];
+
+/** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number)
+ Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x0754 - DMIC ClkB Pin Muxing
+ Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
+
+/** Offset 0x075C - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x075D
+**/
+ UINT8 UnusedUpdSpace21[3];
+
+/** Offset 0x0760 - DMIC Data Pin Muxing
+ Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*
+**/
+ UINT32 PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x0768 - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+ UINT8 PchHdaAudioLinkSspEnable[6];
+
+/** Offset 0x076E - Enable HD Audio SoundWire#N Link
+ Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+ UINT8 PchHdaAudioLinkSndwEnable[4];
+
+/** Offset 0x0772 - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x0773 - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T(Default), 4: 16T
+ 0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x0774 - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x0775 - Force ME DID Init Status
+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+ ME DID init stat value
+ $EN_DIS
+**/
+ UINT8 DidInitStat;
+
+/** Offset 0x0776 - CPU Replaced Polling Disable
+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+ $EN_DIS
+**/
+ UINT8 DisableCpuReplacedPolling;
+
+/** Offset 0x0777 - ME DID Message
+ (DEPRECATED)Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable
+ will prevent the DID message from being sent)
+ $EN_DIS
+**/
+ UINT8 SendDidMsg;
+
+/** Offset 0x0778 - Check HECI message before send
+ Test, 0: disable, 1: enable, Enable/Disable message check.
+ $EN_DIS
+**/
+ UINT8 DisableMessageCheck;
+
+/** Offset 0x0779 - Skip MBP HOB
+ Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
+ $EN_DIS
+**/
+ UINT8 SkipMbpHob;
+
+/** Offset 0x077A - HECI2 Interface Communication
+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+ $EN_DIS
+**/
+ UINT8 HeciCommunication2;
+
+/** Offset 0x077B - Enable KT device
+ Test, 0: disable, 1: enable, Enable or Disable KT device.
+ $EN_DIS
+**/
+ UINT8 KtDeviceEnable;
+
+/** Offset 0x077C - Hybrid Graphics GPIO information for PEG 1
+ Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie1Rtd3Gpio[24];
+
+/** Offset 0x07DC - Hybrid Graphics GPIO information for PEG 2
+ Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie2Rtd3Gpio[24];
+
+/** Offset 0x083C - Hybrid Graphics GPIO information for PEG 3
+ Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie3Rtd3Gpio[24];
+
+/** Offset 0x089C - Skip CPU replacement check
+ Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+ $EN_DIS
+**/
+ UINT8 SkipCpuReplacementCheck;
+
+/** Offset 0x089D - PCI Express Dekel Workaround
+ Select the 1 to 9 for Dekel registers endpoint programming: 1=Minimal, 9=Maximum,
+ default is 2
+**/
+ UINT8 CpuPcieRpDekelSquelchWa;
+
+/** Offset 0x089E - Serial Io Uart Debug Mode
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartDebugMode;
+
+/** Offset 0x089F
+**/
+ UINT8 UnusedUpdSpace22;
+
+/** Offset 0x08A0 - SerialIoUartDebugRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugRxPinMux;
+
+/** Offset 0x08A4 - SerialIoUartDebugTxPinMux - FSPM
+ Select TX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugTxPinMux;
+
+/** Offset 0x08A8 - SerialIoUartDebugRtsPinMux - FSPM
+ Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugRtsPinMux;
+
+/** Offset 0x08AC - SerialIoUartDebugCtsPinMux - FSPM
+ Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugCtsPinMux;
+
+/** Offset 0x08B0 - Avx2 Voltage Guardband Scaling Factor
+ AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
+ 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+ UINT8 Avx2VoltageScaleFactor;
+
+/** Offset 0x08B1 - Avx512 Voltage Guardband Scaling Factor
+ AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
+ in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+ UINT8 Avx512VoltageScaleFactor;
+
+/** Offset 0x08B2 - Lane Used of CSI port
+ Lane Used of each CSI port
+ 1:x1, 2:x2, 3:x3, 4:x4, 8:x8
+**/
+ UINT8 IpuLaneUsed[8];
+
+/** Offset 0x08BA - Lane Used of CSI port
+ Speed of each CSI port
+ 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps
+**/
+ UINT8 CsiSpeed[8];
+
+/** Offset 0x08C2 - DPmem Support
+ 1: enable, 0: disable(Default), Enable/disable setting for Dynamic Persistent Memory support
+ $EN_DIS
+**/
+ UINT8 DpmemSupport;
+
+/** Offset 0x08C3 - Core VF Point Offset Mode
+ Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes;
+ 0: Legacy; 1: Selection.
+ 0:Legacy, 1:Selection
+**/
+ UINT8 CoreVfPointOffsetMode;
+
+/** Offset 0x08C4 - Core VF Point Offset
+ Array used to specifies the Offset Voltage applied to the each selected Core VF
+ Point. This voltage is specified in millivolts.
+**/
+ UINT16 CoreVfPointOffset[15];
+
+/** Offset 0x08E2 - Core VF Point Offset Prefix
+ Sets the CoreVfPointOffset value as positive or negative for corresponding core
+ VF Point; 0: Positive ; 1: Negative.
+ 0:Positive, 1:Negative
+**/
+ UINT8 CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x08F1 - Core VF Point Ratio
+ Array for the each selected Core VF Point to display the ration.
+**/
+ UINT8 CoreVfPointRatio[15];
+
+/** Offset 0x0900 - Core VF Point Count
+ Number of supported Core Voltage & Frequency Point Offset
+**/
+ UINT8 CoreVfPointCount;
+
+/** Offset 0x0901 - Enable CPU CrashLog GPRs dump
+ Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only
+ disable Smm GPRs dump
+ 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
+**/
+ UINT8 CrashLogGprs;
+
+/** Offset 0x0902
+**/
+ UINT8 UnusedUpdSpace23[2];
+
+/** Offset 0x0904 - Bitmask of disable cores
+ Core mask is a bitwise indication of which core should be disabled. 0x00=Default;
+ Bit 0 - core 0, bit 7 - core 7.
+**/
+ UINT32 DisableCoreMask;
+
+/** Offset 0x0908 - REFRESH_PANIC_WM
+ @deprecated - Not used and has no effect, Please use RefreshWm
+**/
+ UINT8 RefreshPanicWm;
+
+/** Offset 0x0909 - REFRESH_HP_WM
+ @deprecated - Not used and has no effect, Please use RefreshWm
+**/
+ UINT8 RefreshHpWm;
+
+/** Offset 0x090A - Support Unlimited ICCMAX
+ Support Unlimited ICCMAX more than maximum value 255.75A; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 UnlimitedIccMax;
+
+/** Offset 0x090B - Per Core Max Ratio override
+ Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
+ favored core ratio to each Core. 0: Disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PerCoreRatioOverride;
+
+/** Offset 0x090C - Per Core Current Max Ratio
+ Array for the Per Core Max Ratio
+**/
+ UINT8 PerCoreRatio[10];
+
+/** Offset 0x0916 - Margin Limit Check
+ Margin Limit Check. Choose level of margin check
+ 0:Disable, 1:L1, 2:L2, 3:Both
+**/
+ UINT8 MarginLimitCheck;
+
+/** Offset 0x0917
+**/
+ UINT8 UnusedUpdSpace24;
+
+/** Offset 0x0918 - Margin Limit L2
+ % of L1 check for margin limit check
+**/
+ UINT16 MarginLimitL2;
+
+/** Offset 0x091A - Iotg Pll SscEn
+ Enable or disable CPU SSC. 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 IotgPllSscEn;
+
+/** Offset 0x091B - GPIO Override
+ Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+ before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level
+ 2 - skips GpioSetNativePadByFunction and GpioSetPadMode
+**/
+ UINT8 GpioOverride;
+
+/** Offset 0x091C - Write0 enabling
+ Enable/Disable Write0
+ $EN_DIS
+**/
+ UINT8 WRITE0;
+
+/** Offset 0x091D
+**/
+ UINT8 UnusedUpdSpace25[3];
+
+/** Offset 0x0920
+**/
+ UINT32 VccInVoltageOverride;
+
+/** Offset 0x0924 - Dynamic Memory Timings Changes
+ Dynamic Memory Timings Changes; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 DynamicMemoryChange;
+
+/** Offset 0x0925 - IbeccErrorInj
+ In-Band ECC Error Injection NOTE: For Debug or Development purposes only! Disable
+ this option for production systems.
+ $EN_DIS
+**/
+ UINT8 IbeccErrorInj;
+
+/** Offset 0x0926 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
+ Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable,
+ Manual(0x1): Enable DmiGen3UsPresetEnable
+ $EN_DIS
+**/
+ UINT8 DmiGen3UsPresetEnable;
+
+/** Offset 0x0927 - DMI Gen3 Root port preset Rx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
+ for each lane
+**/
+ UINT8 DmiGen3UsPortRxPreset[8];
+
+/** Offset 0x092F - DMI Gen3 Root port preset Tx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
+ for each lane
+**/
+ UINT8 DmiGen3UsPortTxPreset[8];
+
+/** Offset 0x0937 - BCLK Frequency Source
+ Clock source of BCLK OC frequency, 0:CPU BCLK, 1:PCH BCLK, 2:External CLK
+ 0:CPU BCLK, 1:PCH BCLK, 2:External CLK
+**/
+ UINT8 BclkSource;
+
+/** Offset 0x0938 - CPU BCLK OC Frequency
+ CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0
+ - Auto. Range is 8000-50000 (10KHz).
+**/
+ UINT32 CpuBclkOcFrequency;
+
+/** Offset 0x093C - Ring CCF Auto Gv Disable Down
+ Ring CCF Auto Gv Disable Down, 0: Disabled, 1:Fused default
+ 0:Disabled, 1:Fused default
+**/
+ UINT8 RingCcfAutoGvDisable;
+
+/** Offset 0x093D - SA/Uncore voltage mode
+ SA/Uncore voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 SaVoltageMode;
+
+/** Offset 0x093E - SA/Uncore Voltage Override
+ The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
+ mode. Valid Range 0 to 2000
+**/
+ UINT16 SaVoltageOverride;
+
+/** Offset 0x0940 - SA/Uncore Extra Turbo voltage
+ Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 SaExtraTurboVoltage;
+
+/** Offset 0x0942 - DdrMemoryDown
+ DDR Memory Down Support.
+ $EN_DIS
+**/
+ UINT8 DdrMemoryDown;
+
+/** Offset 0x0943
+**/
+ UINT8 UnusedUpdSpace26;
+
+/** Offset 0x0944 - The VccIn Max Voltage Limit
+ This will override maximum VCCIN voltage limit to the voltage value specified. 0
+ - no override Valid Range 0 to 3000mV
+**/
+ UINT16 VccInMaxLimit;
+
+/** Offset 0x0946 - VccIO Voltage Override
+ This will override VccIO output voltage level to the voltage value specified. Valid
+ Range 0 to 2000
+**/
+ UINT16 VccIoVoltageOverride;
+
+/** Offset 0x0948 - Boost VRef Voltage
+ Default: 0: 0.7V 1: 1.0V to support the high frequencies needed for BCLK OC.
+ 0: 0.7V , 1:1.0V
+**/
+ UINT8 BoostRefVoltage;
+
+/** Offset 0x0949 - Pcie Ref Pll SSC
+ Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%,
+ 0x5: 0.5%, 0xFE: Disable, 0xFF: Auto
+**/
+ UINT8 PcieRefPllSsc;
+
+/** Offset 0x094A - Refresh Watermarks
+ Refresh Watermark, High, Low
+ 1:Enable Refresh Watermark High (Default), 0:Enable Refresh Watermark Low
+**/
+ UINT8 RefreshWm;
+
+/** Offset 0x094B
+**/
+ UINT8 UnusedUpdSpace27[4];
+
+/** Offset 0x094F
+**/
+ UINT8 ReservedFspmUpd2[1];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0950
+**/
+ UINT8 UnusedUpdSpace28[6];
+
+/** Offset 0x0956
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3050/FSP/Include/FspsUpd.h b/models/gaze16-3050/FSP/Include/FspsUpd.h
new file mode 100644
index 0000000..e8a4982
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FspsUpd.h
@@ -0,0 +1,4203 @@
+/** @file FspsUpd.h
+
+ @copyright
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - Logo Pointer
+ Points to PEI Display Logo Image
+**/
+ UINT32 LogoPtr;
+
+/** Offset 0x0024 - Logo Size
+ Size of PEI Display Logo Image
+**/
+ UINT32 LogoSize;
+
+/** Offset 0x0028 - Blt Buffer Address
+ Address of Blt buffer
+**/
+ UINT32 BltBufferAddress;
+
+/** Offset 0x002C - Blt Buffer Size
+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+**/
+ UINT32 BltBufferSize;
+
+/** Offset 0x0030 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x0034 - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x0035 - Show SPI controller
+ Enable/disable to show SPI controller.
+ $EN_DIS
+**/
+ UINT8 ShowSpiController;
+
+/** Offset 0x0036
+**/
+ UINT8 UnusedUpdSpace0[2];
+
+/** Offset 0x0038 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x003C - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0040 - Turbo Mode
+ Enable/Disable Turbo mode. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 TurboMode;
+
+/** Offset 0x0041 - Enable SATA SALP Support
+ Enable/disable SATA Aggressive Link Power Management.
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0042 - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+ and so on.
+**/
+ UINT8 SataPortsEnable[8];
+
+/** Offset 0x004A - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+ port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlp[8];
+
+/** Offset 0x0052 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x0062 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x006C - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x006D
+**/
+ UINT8 UnusedUpdSpace1[3];
+
+/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+ UINT32 DevIntConfigPtr;
+
+/** Offset 0x0074 - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
+**/
+ UINT8 NumOfDevIntConfig;
+
+/** Offset 0x0075 - PIRQx to IRQx Map Config
+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
+ 8259 PCI mode.
+**/
+ UINT8 PxRcConfig[8];
+
+/** Offset 0x007D - Select GPIO IRQ Route
+ GPIO IRQ Select. The valid value is 14 or 15.
+**/
+ UINT8 GpioIrqRoute;
+
+/** Offset 0x007E - Select SciIrqSelect
+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+ UINT8 SciIrqSelect;
+
+/** Offset 0x007F - Select TcoIrqSelect
+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+ UINT8 TcoIrqSelect;
+
+/** Offset 0x0080 - Enable/Disable Tco IRQ
+ Enable/disable TCO IRQ
+ $EN_DIS
+**/
+ UINT8 TcoIrqEnable;
+
+/** Offset 0x0081 - PCH HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ UINT8 PchHdaVerbTableEntryNum;
+
+/** Offset 0x0082
+**/
+ UINT8 UnusedUpdSpace2[2];
+
+/** Offset 0x0084 - PCH HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ UINT32 PchHdaVerbTablePtr;
+
+/** Offset 0x0088 - PCH HDA Codec Sx Wake Capability
+ Capability to detect wake initiated by a codec in Sx
+**/
+ UINT8 PchHdaCodecSxWakeCapability;
+
+/** Offset 0x0089 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ UINT8 SataEnable;
+
+/** Offset 0x008A - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x008B - SPIn Device Mode
+ Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+ modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
+**/
+ UINT8 SerialIoSpiMode[7];
+
+/** Offset 0x0092 - SPI Chip Select Polarity
+ Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
+ 1:SerialIoSpiCsActiveHigh
+**/
+ UINT8 SerialIoSpiCsPolarity[14];
+
+/** Offset 0x00A0 - SPI Chip Select Enable
+ 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+ UINT8 SerialIoSpiCsEnable[14];
+
+/** Offset 0x00AE - SPIn Default Chip Select Output
+ Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
+ options: 0:CS0, 1:CS1
+**/
+ UINT8 SerialIoSpiDefaultCsOutput[7];
+
+/** Offset 0x00B5 - SPIn Default Chip Select Mode HW/SW
+ Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+ SPI1, ... Available options: 0:HW, 1:SW
+**/
+ UINT8 SerialIoSpiCsMode[7];
+
+/** Offset 0x00BC - SPIn Default Chip Select State Low/High
+ Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+ Available options: 0:Low, 1:High
+**/
+ UINT8 SerialIoSpiCsState[7];
+
+/** Offset 0x00C3 - UARTn Device Mode
+ Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+ modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartMode[7];
+
+/** Offset 0x00CA
+**/
+ UINT8 UnusedUpdSpace3[2];
+
+/** Offset 0x00CC - Default BaudRate for each Serial IO UART
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 SerialIoUartBaudRate[7];
+
+/** Offset 0x00E8 - Default ParityType for each Serial IO UART
+ Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartParity[7];
+
+/** Offset 0x00EF - Default DataBits for each Serial IO UART
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 SerialIoUartDataBits[7];
+
+/** Offset 0x00F6 - Default StopBits for each Serial IO UART
+ Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+ TwoStopBits
+**/
+ UINT8 SerialIoUartStopBits[7];
+
+/** Offset 0x00FD - Power Gating mode for each Serial IO UART that works in COM mode
+ Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+ UINT8 SerialIoUartPowerGating[7];
+
+/** Offset 0x0104 - Enable Dma for each Serial IO UART that supports it
+ Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+ UINT8 SerialIoUartDmaEnable[7];
+
+/** Offset 0x010B - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS lines.
+**/
+ UINT8 SerialIoUartAutoFlow[7];
+
+/** Offset 0x0112
+**/
+ UINT8 UnusedUpdSpace4[2];
+
+/** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0130 - SerialIoUartCtsPinMuxPolicy
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartCtsPinMuxPolicy[7];
+
+/** Offset 0x014C - SerialIoUartRxPinMuxPolicy
+ Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+ possible values.
+**/
+ UINT32 SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x0168 - SerialIoUartTxPinMuxPolicy
+ Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+ possible values.
+**/
+ UINT32 SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x0184 - UART Number For Debug Purpose
+ UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
+ 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
+ for debug purpose.
+ 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
+**/
+ UINT8 SerialIoDebugUartNumber;
+
+/** Offset 0x0185 - Serial IO UART DBG2 table
+ Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable;
+ 1: Enable.
+**/
+ UINT8 SerialIoUartDbg2[7];
+
+/** Offset 0x018C - I2Cn Device Mode
+ Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+ modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+ UINT8 SerialIoI2cMode[8];
+
+/** Offset 0x0194 - Serial IO I2C SDA Pin Muxing
+ Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x01B4 - Serial IO I2C SCL Pin Muxing
+ Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x01D4 - PCH SerialIo I2C Pads Termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+**/
+ UINT8 PchSerialIoI2cPadsTermination[8];
+
+/** Offset 0x01DC - ISH GP GPIO Pin Muxing
+ Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
+**/
+ UINT32 IshGpGpioPinMuxing[8];
+
+/** Offset 0x01FC - ISH UART Rx Pin Muxing
+ Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
+**/
+ UINT32 IshUartRxPinMuxing[3];
+
+/** Offset 0x0208 - ISH UART Tx Pin Muxing
+ Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
+**/
+ UINT32 IshUartTxPinMuxing[3];
+
+/** Offset 0x0214 - ISH UART Rts Pin Muxing
+ Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
+**/
+ UINT32 IshUartRtsPinMuxing[3];
+
+/** Offset 0x0220 - ISH UART Rts Pin Muxing
+ Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
+**/
+ UINT32 IshUartCtsPinMuxing[3];
+
+/** Offset 0x022C - ISH I2C SDA Pin Muxing
+ Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
+**/
+ UINT32 IshI2cSdaPinMuxing[3];
+
+/** Offset 0x0238 - ISH I2C SCL Pin Muxing
+ Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
+**/
+ UINT32 IshI2cSclPinMuxing[3];
+
+/** Offset 0x0244 - ISH SPI MOSI Pin Muxing
+ Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
+**/
+ UINT32 IshSpiMosiPinMuxing[2];
+
+/** Offset 0x024C - ISH SPI MISO Pin Muxing
+ Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
+**/
+ UINT32 IshSpiMisoPinMuxing[2];
+
+/** Offset 0x0254 - ISH SPI CLK Pin Muxing
+ Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
+**/
+ UINT32 IshSpiClkPinMuxing[2];
+
+/** Offset 0x025C - ISH SPI CS#N Pin Muxing
+ Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible
+ values. N-SPI number, 0-1.
+**/
+ UINT32 IshSpiCsPinMuxing[4];
+
+/** Offset 0x026C - ISH GP GPIO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
+ respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
+ 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31
+**/
+ UINT8 IshGpGpioPadTermination[8];
+
+/** Offset 0x0274 - ISH UART Rx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
+ Rx, and so on.
+**/
+ UINT8 IshUartRxPadTermination[3];
+
+/** Offset 0x0277 - ISH UART Tx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
+ Tx, and so on.
+**/
+ UINT8 IshUartTxPadTermination[3];
+
+/** Offset 0x027A - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
+ Rts, and so on.
+**/
+ UINT8 IshUartRtsPadTermination[3];
+
+/** Offset 0x027D - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
+ Cts, and so on.
+**/
+ UINT8 IshUartCtsPadTermination[3];
+
+/** Offset 0x0280 - ISH I2C SDA Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+ and so on.
+**/
+ UINT8 IshI2cSdaPadTermination[3];
+
+/** Offset 0x0283 - ISH I2C SCL Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+ and so on.
+**/
+ UINT8 IshI2cSclPadTermination[3];
+
+/** Offset 0x0286 - ISH SPI MOSI Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
+ Mosi, and so on.
+**/
+ UINT8 IshSpiMosiPadTermination[2];
+
+/** Offset 0x0288 - ISH SPI MISO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
+ Miso, and so on.
+**/
+ UINT8 IshSpiMisoPadTermination[2];
+
+/** Offset 0x028A - ISH SPI CLK Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
+ and so on.
+**/
+ UINT8 IshSpiClkPadTermination[2];
+
+/** Offset 0x028C - ISH SPI CS#N Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
+ respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
+ Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3
+**/
+ UINT8 IshSpiCsPadTermination[4];
+
+/** Offset 0x0290 - Enable PCH ISH SPI Cs#N pins assigned
+ Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
+ number: 0-1
+**/
+ UINT8 PchIshSpiCsEnable[4];
+
+/** Offset 0x0294 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2PhyPetxiset[16];
+
+/** Offset 0x02A4 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2PhyTxiset[16];
+
+/** Offset 0x02B4 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2PhyPredeemp[16];
+
+/** Offset 0x02C4 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2PhyPehalfbit[16];
+
+/** Offset 0x02D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x02DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x02E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x02F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default
+ = 00h. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x02FC
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
+
+/** Offset 0x0306
+**/
+ UINT8 PchUsb3HsioFilterSelNEnable[10];
+
+/** Offset 0x0310
+**/
+ UINT8 PchUsb3HsioFilterSelPEnable[10];
+
+/** Offset 0x031A
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
+
+/** Offset 0x0324
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
+
+/** Offset 0x032E
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
+
+/** Offset 0x0338
+**/
+ UINT8 PchUsb3HsioFilterSelN[10];
+
+/** Offset 0x0342
+**/
+ UINT8 PchUsb3HsioFilterSelP[10];
+
+/** Offset 0x034C - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x034D - Enable PCH TSN
+ Enable/disable TSN on the PCH.
+ $EN_DIS
+**/
+ UINT8 PchTsnEnable;
+
+/** Offset 0x034E - TSN Link Speed
+ Set TSN Link Speed.
+ 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
+**/
+ UINT8 PchTsnLinkSpeed;
+
+/** Offset 0x034F
+**/
+ UINT8 UnusedUpdSpace5;
+
+/** Offset 0x0350 - PCH TSN0 MAC Address High Bits
+ Set TSN0 MAC Address High.
+**/
+ UINT32 PchTsn0MacAddressHigh;
+
+/** Offset 0x0354 - PCH TSN0 MAC Address Low Bits
+ Set TSN0 MAC Address Low.
+**/
+ UINT32 PchTsn0MacAddressLow;
+
+/** Offset 0x0358 - PCIe PTM enable/disable
+ Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+ UINT8 PciePtm[24];
+
+/** Offset 0x0370 - PCIe DPC enable/disable
+ Enable/disable Downstream Port Containment for PCIE Root Ports.
+**/
+ UINT8 PcieDpc[24];
+
+/** Offset 0x0388 - PCIe DPC extensions enable/disable
+ Enable/disable Downstream Port Containment Extensions for PCIE Root Ports.
+**/
+ UINT8 PcieEdpc[24];
+
+/** Offset 0x03A0 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x03A1
+**/
+ UINT8 UnusedUpdSpace6[3];
+
+/** Offset 0x03A4 - Power button debounce configuration
+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+ UINT32 PmcPowerButtonDebounce;
+
+/** Offset 0x03A8 - PCH eSPI Master and Slave BME enabled
+ PCH eSPI Master and Slave BME enabled
+ $EN_DIS
+**/
+ UINT8 PchEspiBmeMasterSlaveEnabled;
+
+/** Offset 0x03A9 - PCH SATA use RST Legacy OROM
+ Use PCH SATA RST Legacy OROM when CSM is Enabled
+ $EN_DIS
+**/
+ UINT8 SataRstLegacyOrom;
+
+/** Offset 0x03AA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+ Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtV1p05RailEnabledStates;
+
+/** Offset 0x03AB - Mask to enable the platform configuration of external V1p05 VR rail
+ External V1P05 Rail Supported Configuration
+**/
+ UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
+
+/** Offset 0x03AC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtV1p05RailVoltage;
+
+/** Offset 0x03AE - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtV1p05RailIccMax;
+
+/** Offset 0x03AF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+ Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailEnabledStates;
+
+/** Offset 0x03B0 - Mask to enable the platform configuration of external Vnn VR rail
+ External Vnn Rail Supported Configuration
+**/
+ UINT8 PchFivrExtVnnRailSupportedVoltageStates;
+
+/** Offset 0x03B1
+**/
+ UINT8 UnusedUpdSpace7;
+
+/** Offset 0x03B2 - External Vnn Voltage Value that will be used in S0ix/Sx states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
+**/
+ UINT16 PchFivrExtVnnRailVoltage;
+
+/** Offset 0x03B4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailIccMax;
+
+/** Offset 0x03B5 - Mask to enable the usage of external Vnn VR rail in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
+ Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailSxEnabledStates;
+
+/** Offset 0x03B6 - External Vnn Voltage Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
+ (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtVnnRailSxVoltage;
+
+/** Offset 0x03B8 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailSxIccMax;
+
+/** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to low current mode voltage.
+**/
+ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x03BA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x03BB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
+
+/** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x03BE
+**/
+ UINT8 UnusedUpdSpace8[2];
+
+/** Offset 0x03C0 - Trace Hub Memory Base
+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
+ memory is configured properly.
+**/
+ UINT32 TraceHubMemBase;
+
+/** Offset 0x03C4 - PMC Debug Message Enable
+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
+ $EN_DIS
+**/
+ UINT8 PmcDbgMsgEn;
+
+/** Offset 0x03C5
+**/
+ UINT8 UnusedUpdSpace9[3];
+
+/** Offset 0x03C8 - Pointer of ChipsetInit Binary
+ ChipsetInit Binary Pointer.
+**/
+ UINT32 ChipsetInitBinPtr;
+
+/** Offset 0x03CC - Length of ChipsetInit Binary
+ ChipsetInit Binary Length.
+**/
+ UINT32 ChipsetInitBinLen;
+
+/** Offset 0x03D0 - FIVR Dynamic Power Management
+ Enable/Disable FIVR Dynamic Power Management.
+ $EN_DIS
+**/
+ UINT8 PchFivrDynPm;
+
+/** Offset 0x03D1
+**/
+ UINT8 UnusedUpdSpace10;
+
+/** Offset 0x03D2 - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtV1p05RailIccMaximum;
+
+/** Offset 0x03D4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailIccMaximum;
+
+/** Offset 0x03D6 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailSxIccMaximum;
+
+/** Offset 0x03D8 - PCH eSPI Link Configuration Lock (SBLCL)
+ Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves
+ addresseses from range 0x0 - 0x7FF
+ $EN_DIS
+**/
+ UINT8 PchEspiLockLinkConfiguration;
+
+/** Offset 0x03D9 - Extented BIOS Direct Read Decode enable
+ Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
+ 0: disabled (default), 1: enabled
+ $EN_DIS
+**/
+ UINT8 PchSpiExtendedBiosDecodeRangeEnable;
+
+/** Offset 0x03DA - Enforce Enhanced Debug Mode
+ Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 EnforceEDebugMode;
+
+/** Offset 0x03DB - PchPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 PchPostMemRsvd[1];
+
+/** Offset 0x03DC - Extended BIOS Direct Read Decode Range base
+ Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
+**/
+ UINT32 PchSpiExtendedBiosDecodeRangeBase;
+
+/** Offset 0x03E0 - Extended BIOS Direct Read Decode Range limit
+ Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
+**/
+ UINT32 PchSpiExtendedBiosDecodeRangeLimit;
+
+/** Offset 0x03E4 - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x03E5 - CNVi BT Core
+ Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtCore;
+
+/** Offset 0x03E6 - CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtAudioOffload;
+
+/** Offset 0x03E7
+**/
+ UINT8 UnusedUpdSpace11;
+
+/** Offset 0x03E8 - CNVi RF_RESET pin muxing
+ Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default)
+ or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+ UINT32 CnviRfResetPinMux;
+
+/** Offset 0x03EC - CNVi CLKREQ pin muxing
+ Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default)
+ or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in
+ GpioPins*.h.
+**/
+ UINT32 CnviClkreqPinMux;
+
+/** Offset 0x03F0 - Enable Host C10 reporting through eSPI
+ Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire.
+ $EN_DIS
+**/
+ UINT8 PchEspiHostC10ReportEnable;
+
+/** Offset 0x03F1 - PCH USB2 PHY Power Gating enable
+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+ Sus Well PG
+ $EN_DIS
+**/
+ UINT8 PmcUsb2PhySusPgEnable;
+
+/** Offset 0x03F2 - PCH USB OverCurrent mapping enable
+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+ mapping allow for NOA usage of OC pins
+ $EN_DIS
+**/
+ UINT8 PchUsbOverCurrentEnable;
+
+/** Offset 0x03F3 - Espi Lgmr Memory Range decode
+ This option enables or disables espi lgmr
+ $EN_DIS
+**/
+ UINT8 PchEspiLgmrEnable;
+
+/** Offset 0x03F4 - External V1P05 Control Ramp Timer value
+ Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtV1p05RailCtrlRampTmr;
+
+/** Offset 0x03F5 - External VNN Control Ramp Timer value
+ Hold off time to be used when changing the vnn_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtVnnRailCtrlRampTmr;
+
+/** Offset 0x03F6 - Set SATA DEVSLP GPIO Reset Config
+ Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
+ 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
+ for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlpResetConfig[8];
+
+/** Offset 0x03FE - HECI3 state
+ The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
+ DEPRECATED 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 Heci3Enabled;
+
+/** Offset 0x03FF - PCHHOT# pin
+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchHotEnable;
+
+/** Offset 0x0400 - SATA LED
+ SATA LED indicating SATA controller activity. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 SataLedEnable;
+
+/** Offset 0x0401 - VRAlert# Pin
+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmVrAlert;
+
+/** Offset 0x0402 - AMT Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+ $EN_DIS
+**/
+ UINT8 AmtEnabled;
+
+/** Offset 0x0403 - WatchDog Timer Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 WatchDogEnabled;
+
+/** Offset 0x0404 - Manageability Mode set by Mebx
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
+ $EN_DIS
+**/
+ UINT8 ManageabilityMode;
+
+/** Offset 0x0405 - PET Progress
+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
+ PET Events. Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 FwProgress;
+
+/** Offset 0x0406 - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+ Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtSolEnabled;
+
+/** Offset 0x0407
+**/
+ UINT8 UnusedUpdSpace12;
+
+/** Offset 0x0408 - OS Timer
+ 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerOs;
+
+/** Offset 0x040A - BIOS Timer
+ 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerBios;
+
+/** Offset 0x040C - Remote Assistance Trigger Availablilty
+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
+ $EN_DIS
+**/
+ UINT8 RemoteAssistance;
+
+/** Offset 0x040D - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtKvmEnabled;
+
+/** Offset 0x040E - Force MEBX execution
+ Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
+ $EN_DIS
+**/
+ UINT8 ForcMebxSyncUp;
+
+/** Offset 0x040F - PCH PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 PcieRpSlotImplemented[24];
+
+/** Offset 0x0427 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 PcieRpAcsEnabled[24];
+
+/** Offset 0x043F - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 PcieRpEnableCpm[24];
+
+/** Offset 0x0457
+**/
+ UINT8 UnusedUpdSpace13[1];
+
+/** Offset 0x0458 - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x0488 - ModPHY SUS Power Domain Dynamic Gating
+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+ PCH-H. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcModPhySusPgEnable;
+
+/** Offset 0x0489 - V1p05-PHY supply external FET control
+ Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05PhyExtFetControlEn;
+
+/** Offset 0x048A - V1p05-IS supply external FET control
+ Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05IsExtFetControlEn;
+
+/** Offset 0x048B - Enable/Disable PavpEnable
+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+ $EN_DIS
+**/
+ UINT8 PavpEnable;
+
+/** Offset 0x048C - CdClock Frequency selection
+ 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
+ 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+ 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
+ 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x048D - Enable/Disable PeiGraphicsPeimInit
+ Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+ Disable: FSP will NOT initialize the framebuffer.
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x048E - Enable D3 Hot in TCSS
+ This policy will enable/disable D3 hot support in IOM
+ $EN_DIS
+**/
+ UINT8 D3HotEnable;
+
+/** Offset 0x048F - Enable or disable GNA device
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 GnaEnable;
+
+/** Offset 0x0490 - TypeC port GPIO setting
+ GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Tgl
+ = TigerLake)
+**/
+ UINT32 IomTypeCPortPadCfg[8];
+
+/** Offset 0x04B0 - CPU USB3 Port Over Current Pin
+ Describe the specific over current pin number of USBC Port N.
+**/
+ UINT8 CpuUsb3OverCurrentPin[8];
+
+/** Offset 0x04B8 - Enable D3 Cold in TCSS
+ This policy will enable/disable D3 cold support in IOM
+ $EN_DIS
+**/
+ UINT8 D3ColdEnable;
+
+/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4
+ Enable/Disable PCIe tunneling for USB4, default is enable
+ $EN_DIS
+**/
+ UINT8 ITbtPcieTunnelingForUsb4;
+
+/** Offset 0x04BA - Enable/Disable SkipFspGop
+ Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
+ $EN_DIS
+**/
+ UINT8 SkipFspGop;
+
+/** Offset 0x04BB - TC State in TCSS
+ This TC C-State Limit in IOM
+**/
+ UINT8 TcCstateLimit;
+
+/** Offset 0x04BC - Disable TC code On USB Connect
+ Enable: Unsupported TC cold capability on Usb Connected, Disable(default): Supported
+ TC cold On Usb Connected
+ $EN_DIS
+**/
+ UINT8 DisableTccoldOnUsbConnected;
+
+/** Offset 0x04BD - Set Iom stay in TC cold seconds in TCSS
+ Set Iom stay in TC cold seconds in IOM
+**/
+ UINT8 IomStayInTCColdeSeconds;
+
+/** Offset 0x04BE - Set Iom before entering TC cold seconds in TCSS
+ Set Iom before entering TC cold seconds in IOM
+**/
+ UINT8 IomBeforeEnteringTCCodeSeconds;
+
+/** Offset 0x04BF - SaPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 SaPostMemRsvd[2];
+
+/** Offset 0x04C1 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 VmdEnable;
+
+/** Offset 0x04C2 - Enable VMD portA Support
+ Enable/disable to VMD portA Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortA;
+
+/** Offset 0x04C3 - Enable VMD portB Support
+ Enable/disable to VMD portB Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortB;
+
+/** Offset 0x04C4 - Enable VMD portC Support
+ Enable/disable to VMD portC Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortC;
+
+/** Offset 0x04C5 - Enable VMD portD Support
+ Enable/disable to VMD portD Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortD;
+
+/** Offset 0x04C6 - VMD Config Bar size
+ Set The VMD Config Bar Size.
+**/
+ UINT8 VmdCfgBarSize;
+
+/** Offset 0x04C7 - VMD Config Bar Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default)
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdCfgBarAttr;
+
+/** Offset 0x04C8 - VMD Mem Bar1 size
+ Set The VMD Mem Bar1 Size.
+**/
+ UINT8 VmdMemBarSize1;
+
+/** Offset 0x04C9 - VMD Mem Bar1 Attributes
+ 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar1Attr;
+
+/** Offset 0x04CA - VMD Mem Bar2 size
+ Set The VMD Mem Bar2 Size.
+**/
+ UINT8 VmdMemBarSize2;
+
+/** Offset 0x04CB - VMD Mem Bar2 Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar2Attr;
+
+/** Offset 0x04CC - Enable/Disable PMC-PD Solution
+ This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
+ $EN_DIS
+**/
+ UINT8 PmcPdEnable;
+
+/** Offset 0x04CD
+**/
+ UINT8 UnusedUpdSpace14;
+
+/** Offset 0x04CE - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x04D0 - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x04D2 - USB override in IOM
+ This policy will enable/disable USB Connect override in IOM
+ $EN_DIS
+**/
+ UINT8 UsbOverride;
+
+/** Offset 0x04D3 - TCSS USB Port Enable
+ Bits 0, 1, ... max Type C port control enables
+**/
+ UINT8 UsbTcPortEn;
+
+/** Offset 0x04D4 - ITBT Root Port Enable
+ ITBT Root Port Enable, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 ITbtPcieRootPortEn[4];
+
+/** Offset 0x04D8 - ITBTForcePowerOn Timeout value
+ ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
+ 100 = 100 ms.
+**/
+ UINT16 ITbtForcePowerOnTimeoutInMs;
+
+/** Offset 0x04DA - ITbtConnectTopology Timeout value
+ ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+ is 0-10000. 100 = 100 ms.
+**/
+ UINT16 ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x04DC - VCCST request for IOM
+ This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
+ $EN_DIS
+**/
+ UINT8 VccSt;
+
+/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable
+ Used by IOM FW to skip powering down the PHY at the end of disconnect flow
+ $EN_DIS
+**/
+ UINT8 Usb3ComplModeEnable;
+
+/** Offset 0x04DE - ITBT DMA LTR
+ TCSS DMA1, DMA2 LTR value
+**/
+ UINT16 ITbtDmaLtr[2];
+
+/** Offset 0x04E2 - Enable/Disable CrashLog
+ Deprecated. Move to PreMem
+ $EN_DIS
+**/
+ UINT8 DeprecatedCpuCrashLogEnable;
+
+/** Offset 0x04E3 - Enable/Disable PTM
+ This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+ $EN_DIS
+**/
+ UINT8 PtmEnabled[4];
+
+/** Offset 0x04E7 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 SaPcieItbtRpLtrEnable[4];
+
+/** Offset 0x04EB - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x04EF - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x04F3
+**/
+ UINT8 UnusedUpdSpace15[1];
+
+/** Offset 0x04F4 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x04FC - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0500 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0504 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x050C - Force LTR Override
+ Force LTR Override.
+**/
+ UINT8 SaPcieItbtRpForceLtrOverride[4];
+
+/** Offset 0x0510 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 SaPcieItbtRpLtrConfigLock[4];
+
+/** Offset 0x0514 - Advanced Encryption Standard (AES) feature
+ Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 AesEnable;
+
+/** Offset 0x0515 - Power State 3 enable/disable
+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.
+ For all VR Indexes
+**/
+ UINT8 Psi3Enable[5];
+
+/** Offset 0x051A - Power State 4 enable/disable
+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 Psi4Enable[5];
+
+/** Offset 0x051F
+**/
+ UINT8 UnusedUpdSpace16[1];
+
+/** Offset 0x0520 - Imon slope correction
+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+ Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes
+**/
+ UINT16 ImonSlope[5];
+
+/** Offset 0x052A - Imon offset correction
+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
+**/
+ UINT16 ImonOffset[5];
+
+/** Offset 0x0534 - Enable/Disable BIOS configuration of VR
+ Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes
+**/
+ UINT8 VrConfigEnable[5];
+
+/** Offset 0x0539 - Thermal Design Current enable/disable
+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1:
+ Enable.For all VR Indexes
+**/
+ UINT8 TdcEnable[5];
+
+/** Offset 0x053E - Thermal Design Current time window
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ DEPRECATED. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 -
+ 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Index
+**/
+ UINT8 TdcTimeWindow[5];
+
+/** Offset 0x0543 - Thermal Design Current Lock
+ PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 TdcLock[5];
+
+/** Offset 0x0548 - Platform Psys slope correction
+ PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in
+ 1/100 increment values. Range is 0-200. 125 = 1.25
+**/
+ UINT8 PsysSlope;
+
+/** Offset 0x0549
+**/
+ UINT8 PsysOffset;
+
+/** Offset 0x054A - Acoustic Noise Mitigation feature
+ Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 AcousticNoiseMitigation;
+
+/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. 0: False; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisable[5];
+
+/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains
+ Slew Rate configuration for Deep Package C States for VR domains based on Acoustic
+ Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRate[5];
+
+/** Offset 0x0555 - Enable multi phases silicon initialization
+ A switch to determine MultiPhaseSiInit will be executed or not
+ $EN_DIS
+**/
+ UINT8 EnableMultiPhaseSiliconInit;
+
+/** Offset 0x0556 - Thermal Design Current current limit
+ PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
+ Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes
+**/
+ UINT16 TdcCurrentLimit[5];
+
+/** Offset 0x0560 - AcLoadline
+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249. Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 AcLoadline[5];
+
+/** Offset 0x056A - DcLoadline
+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249.Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 DcLoadline[5];
+
+/** Offset 0x0574 - Power State 1 Threshold current
+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi1Threshold[5];
+
+/** Offset 0x057E - Power State 2 Threshold current
+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi2Threshold[5];
+
+/** Offset 0x0588 - Power State 3 Threshold current
+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi3Threshold[5];
+
+/** Offset 0x0592 - Icc Max limit
+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
+**/
+ UINT16 IccMax[5];
+
+/** Offset 0x059C - VR Voltage Limit
+ PCODE MMIO Mailbox: VR Voltage Limit. DEPRECATED, Range is 0-7999mV.
+**/
+ UINT16 VrVoltageLimit[5];
+
+/** Offset 0x05A6 - Enable VR specific mailbox command
+ VR specific mailbox commands. 00b - no VR specific command sent. 01b - A
+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
+ command sent for PS4 exit issue. 11b - Reserved.
+ $EN_DIS
+**/
+ UINT8 SendVrMbxCmd;
+
+/** Offset 0x05A7 - Reserved
+ Reserved
+**/
+ UINT8 Reserved2;
+
+/** Offset 0x05A8 - Enable or Disable TXT
+ Enable or Disable TXT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TxtEnable;
+
+/** Offset 0x05A9 - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. 0: Initialize; 1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x05AA - FIVR RFI Frequency
+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0:
+ Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
+ 0-1535 (Up to 153.5MHz) for 19MHz clock.
+**/
+ UINT16 FivrRfiFrequency;
+
+/** Offset 0x05AC - FIVR RFI Spread Spectrum
+ Set the Spread Spectrum Range. 1.5%; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%,
+ 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1%
+ = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+**/
+ UINT8 FivrSpreadSpectrum;
+
+/** Offset 0x05AD
+**/
+ UINT8 UnusedUpdSpace17[3];
+
+/** Offset 0x05B0 - CpuBistData
+ Pointer CPU BIST Data
+**/
+ UINT32 CpuBistData;
+
+/** Offset 0x05B4 - CpuMpPpi
+ Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+ If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+ See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+ UINT32 CpuMpPpi;
+
+/** Offset 0x05B8 - CpuMpHob
+ @deprecated This is not needed in current version of FSP.
+**/
+ UINT32 CpuMpHob;
+
+/** Offset 0x05BC - RFI Mitigation
+ Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1:
+ Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
+ $EN_DIS
+**/
+ UINT8 RfiMitigation;
+
+/** Offset 0x05BD - FIVR RFI Spread Spectrum Enable or disable
+ Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable
+**/
+ UINT8 FivrSpectrumEnable;
+
+/** Offset 0x05BE - Pre Wake Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled. Range 0-255 0.
+**/
+ UINT8 PreWake;
+
+/** Offset 0x05BF - Ramp Up Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 0.
+**/
+ UINT8 RampUp;
+
+/** Offset 0x05C0 - Ramp Down Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 0.
+**/
+ UINT8 RampDown;
+
+/** Offset 0x05C1
+**/
+ UINT8 CpuPostMemRsvd[11];
+
+/** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number
+ Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
+ flag is set) for PPIN Support
+ 0: Disable, 1: Enable, 2: Auto
+**/
+ UINT8 PpinSupport;
+
+/** Offset 0x05CD - Enable or Disable Minimum Voltage Override
+ Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 EnableMinVoltageOverride;
+
+/** Offset 0x05CE - Min Voltage for Runtime
+ PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride
+ = 1. Range 0 to 1999mV. 0: 0mV
+**/
+ UINT16 MinVoltageRuntime;
+
+/** Offset 0x05D0 - Base of memory region allocated for Processor Trace
+ Base address of memory region allocated for Processor Trace. Processor Trace requires
+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable
+**/
+ UINT64 ProcessorTraceMemBase;
+
+/** Offset 0x05D8 - Memory region allocation for Processor Trace
+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable
+**/
+ UINT32 ProcessorTraceMemLength;
+
+/** Offset 0x05DC - Min Voltage for C8
+ PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
+ 1. Range 0 to 1999mV. 0: 0mV
+**/
+ UINT16 MinVoltageC8;
+
+/** Offset 0x05DE - Platform Psys offset correction
+ PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000,
+ Range 0-63999. For an offset of 25.348, enter 25348.
+**/
+ UINT16 PsysOffset1;
+
+/** Offset 0x05E0 - Smbios Type4 Max Speed Override
+ Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
+ If this value is not zero, it dominates the field.
+**/
+ UINT16 SmbiosType4MaxSpeedOverride;
+
+/** Offset 0x05E2 - AvxDisable
+ Enable or Disable AVX Support.
+ 0: Enable, 1: Disable
+**/
+ UINT8 AvxDisable;
+
+/** Offset 0x05E3 - Avx3Disable
+ Enable or Disable AVX3 Support
+ 0: Enable, 1: Disable
+**/
+ UINT8 Avx3Disable;
+
+/** Offset 0x05E4 - ReservedCpuPostMemProduction
+ Reserved for CPU Post-Mem Production
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemProduction[4];
+
+/** Offset 0x05E8 - Enable Power Optimizer
+ Enable DMI Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 PchPwrOptEnable;
+
+/** Offset 0x05E9 - PCH Flash Protection Ranges Write Enble
+ Write or erase is blocked by hardware.
+**/
+ UINT8 PchWriteProtectionEnable[5];
+
+/** Offset 0x05EE - PCH Flash Protection Ranges Read Enble
+ Read is blocked by hardware.
+**/
+ UINT8 PchReadProtectionEnable[5];
+
+/** Offset 0x05F3
+**/
+ UINT8 UnusedUpdSpace18[1];
+
+/** Offset 0x05F4 - PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** Offset 0x05FE - PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** Offset 0x0608 - Enable Pme
+ Enable Azalia wake-on-ring.
+ $EN_DIS
+**/
+ UINT8 PchHdaPme;
+
+/** Offset 0x0609 - HD Audio Link Frequency
+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+ UINT8 PchHdaLinkFrequency;
+
+/** Offset 0x060A - PchPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 PchPostMemRsvd4[3];
+
+/** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned
+ Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiCs0Enable[1];
+
+/** Offset 0x060E - Enable PCH Io Apic Entry 24-119
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIoApicEntry24_119;
+
+/** Offset 0x060F - PCH Io Apic ID
+ This member determines IOAPIC ID. Default is 0x02.
+**/
+ UINT8 PchIoApicId;
+
+/** Offset 0x0610 - Enable PCH ISH SPI pins assigned
+ Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiEnable[1];
+
+/** Offset 0x0611 - Enable PCH ISH UART pins assigned
+ Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshUartEnable[2];
+
+/** Offset 0x0613 - Enable PCH ISH I2C pins assigned
+ Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshI2cEnable[3];
+
+/** Offset 0x0616 - Enable PCH ISH GP pins assigned
+ Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshGpEnable[8];
+
+/** Offset 0x061E - PCH ISH PDT Unlock Msg
+ 0: False; 1: True.
+ $EN_DIS
+**/
+ UINT8 PchIshPdtUnlock;
+
+/** Offset 0x061F - Enable PCH Lan LTR capabilty of PCH internal LAN
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchLanLtrEnable;
+
+/** Offset 0x0620 - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x0621 - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x0622 - RTC BIOS Interface Lock
+ Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
+ $EN_DIS
+**/
+ UINT8 RtcBiosInterfaceLock;
+
+/** Offset 0x0623 - RTC Cmos Memory Lock
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 RtcMemoryLock;
+
+/** Offset 0x0624 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[24];
+
+/** Offset 0x063C - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 PcieRpPmSci[24];
+
+/** Offset 0x0654 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 PcieRpTransmitterHalfSwing[24];
+
+/** Offset 0x066C - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[24];
+
+/** Offset 0x0684 - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[24];
+
+/** Offset 0x069C - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 PcieRpUnsupportedRequestReport[24];
+
+/** Offset 0x06B4 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpFatalErrorReport[24];
+
+/** Offset 0x06CC - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpNoFatalErrorReport[24];
+
+/** Offset 0x06E4 - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 PcieRpCorrectableErrorReport[24];
+
+/** Offset 0x06FC - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnFatalError[24];
+
+/** Offset 0x0714 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnNonFatalError[24];
+
+/** Offset 0x072C - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnCorrectableError[24];
+
+/** Offset 0x0744 - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[24];
+
+/** Offset 0x075C - Touch Host Controller Port 0 Assignment
+ Assign THC Port 0
+ 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
+**/
+ UINT8 ThcPort0Assignment;
+
+/** Offset 0x075D
+**/
+ UINT8 UnusedUpdSpace19[3];
+
+/** Offset 0x0760 - THC Port 0 Interrupt Pin Mux
+ Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer
+ to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
+**/
+ UINT32 ThcPort0InterruptPinMuxing;
+
+/** Offset 0x0764 - Touch Host Controller Port 1 Assignment
+ Assign THC Port 1
+ 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcPort1Assignment;
+
+/** Offset 0x0765 - Touch Host Controller Port 1 ReadFrequency
+ Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+ 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+**/
+ UINT8 ThcPort1ReadFrequency;
+
+/** Offset 0x0766 - Touch Host Controller Port 1 WriteFrequency
+ Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+ 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+**/
+ UINT8 ThcPort1WriteFrequency;
+
+/** Offset 0x0767
+**/
+ UINT8 UnusedUpdSpace20;
+
+/** Offset 0x0768 - THC Port 1 Interrupt Pin Mux
+ Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
+ to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
+**/
+ UINT32 ThcPort1InterruptPinMuxing;
+
+/** Offset 0x076C - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+ PCIE_SPEED).
+**/
+ UINT8 PcieRpPcieSpeed[24];
+
+/** Offset 0x0784 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 PcieRpPhysicalSlotNumber[24];
+
+/** Offset 0x079C - PCIE RP Completion Timeout
+ The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PcieCompletionTO_Default.
+**/
+ UINT8 PcieRpCompletionTimeout[24];
+
+/** Offset 0x07B4 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[24];
+
+/** Offset 0x07CC - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[24];
+
+/** Offset 0x07E4 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[24];
+
+/** Offset 0x07FC - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PcieRpLtrConfigLock[24];
+
+/** Offset 0x0814 - PCIe override default settings for EQ
+ Choose PCIe EQ method
+ $EN_DIS
+**/
+ UINT8 PcieEqOverrideDefault;
+
+/** Offset 0x0815 - PCIe choose EQ method
+ Choose PCIe EQ method
+ 0: HardwareEq, 1: FixedEq
+**/
+ UINT8 PcieEqMethod;
+
+/** Offset 0x0816 - PCIe choose EQ mode
+ Choose PCIe EQ mode
+ 0: PresetEq, 1: CoefficientEq
+**/
+ UINT8 PcieEqMode;
+
+/** Offset 0x0817 - PCIe EQ local transmitter override
+ Enable/Disable local transmitter override
+ $EN_DIS
+**/
+ UINT8 PcieEqLocalTransmitterOverrideEnable;
+
+/** Offset 0x0818 - PCIe number of valid list entries
+ Select number of presets or coefficients depending on the mode
+**/
+ UINT8 PcieEqPh3NumberOfPresetsOrCoefficients;
+
+/** Offset 0x0819 - PCIe pre-cursor coefficient list
+ Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PreCursorList[10];
+
+/** Offset 0x0823 - PCIe post-cursor coefficient list
+ Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PostCursorList[10];
+
+/** Offset 0x082D - PCIe preset list
+ Provide a list of presets to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PresetList[11];
+
+/** Offset 0x0838 - PCIe EQ phase 1 downstream transmitter port preset
+ Allows to select the downstream port preset value that will be used during phase
+ 1 of equalization
+**/
+ UINT32 PcieEqPh1DownstreamPortTransmitterPreset;
+
+/** Offset 0x083C - PCIe EQ phase 1 upstream tranmitter port preset
+ Allows to select the upstream port preset value that will be used during phase 1
+ of equalization
+**/
+ UINT32 PcieEqPh1UpstreamPortTransmitterPreset;
+
+/** Offset 0x0840 - PCIe EQ phase 2 local transmitter override preset
+ Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+ UINT8 PcieEqPh2LocalTransmitterOverridePreset;
+
+/** Offset 0x0841 - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePeerMemoryWrite;
+
+/** Offset 0x0842 - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 PcieComplianceTestMode;
+
+/** Offset 0x0843 - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 PcieRpFunctionSwap;
+
+/** Offset 0x0844 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+ Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
+ Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 CpuPcieGen3ProgramStaticEq;
+
+/** Offset 0x0845 - Enable/Disable GEN4 Static EQ Phase1 programming
+ Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
+ Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 CpuPcieGen4ProgramStaticEq;
+
+/** Offset 0x0846 - PCH Pm PME_B0_S5_DIS
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+ $EN_DIS
+**/
+ UINT8 PchPmPmeB0S5Dis;
+
+/** Offset 0x0847 - PCIE IMR
+ Enables Isolated Memory Region for PCIe.
+ $EN_DIS
+**/
+ UINT8 PcieRpImrEnabled;
+
+/** Offset 0x0848 - PCIE IMR port number
+ Selects PCIE root port number for IMR feature.
+**/
+ UINT8 PcieRpImrSelection;
+
+/** Offset 0x0849 - PCH Pm Wol Enable Override
+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolEnableOverride;
+
+/** Offset 0x084A - PCH Pm Pcie Wake From DeepSx
+ Determine if enable PCIe to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmPcieWakeFromDeepSx;
+
+/** Offset 0x084B - PCH Pm WoW lan Enable
+ Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanEnable;
+
+/** Offset 0x084C - PCH Pm WoW lan DeepSx Enable
+ Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
+ PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanDeepSxEnable;
+
+/** Offset 0x084D - PCH Pm Lan Wake From DeepSx
+ Determine if enable LAN to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmLanWakeFromDeepSx;
+
+/** Offset 0x084E - PCH Pm Deep Sx Pol
+ Deep Sx Policy.
+ $EN_DIS
+**/
+ UINT8 PchPmDeepSxPol;
+
+/** Offset 0x084F - PCH Pm Slp S3 Min Assert
+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+ UINT8 PchPmSlpS3MinAssert;
+
+/** Offset 0x0850 - PCH Pm Slp S4 Min Assert
+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+ UINT8 PchPmSlpS4MinAssert;
+
+/** Offset 0x0851 - PCH Pm Slp Sus Min Assert
+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+ UINT8 PchPmSlpSusMinAssert;
+
+/** Offset 0x0852 - PCH Pm Slp A Min Assert
+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+ UINT8 PchPmSlpAMinAssert;
+
+/** Offset 0x0853 - USB Overcurrent Override for DbC
+ This option overrides USB Over Current enablement state that USB OC will be disabled
+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.
+ $EN_DIS
+**/
+ UINT8 PchEnableDbcObs;
+
+/** Offset 0x0854 - PCH Pm Slp Strch Sus Up
+ Enable SLP_X Stretching After SUS Well Power Up.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpStrchSusUp;
+
+/** Offset 0x0855 - PCH Pm Slp Lan Low Dc
+ Enable/Disable SLP_LAN# Low on DC Power.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpLanLowDc;
+
+/** Offset 0x0856 - PCH Pm Pwr Btn Override Period
+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+ UINT8 PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x0857 - PCH Pm Disable Dsx Ac Present Pulldown
+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableDsxAcPresentPulldown;
+
+/** Offset 0x0858 - PCH Pm Disable Native Power Button
+ Power button native mode disable.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableNativePowerButton;
+
+/** Offset 0x0859 - PCH Pm ME_WAKE_STS
+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmMeWakeSts;
+
+/** Offset 0x085A - PCH Pm WOL_OVR_WK_STS
+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolOvrWkSts;
+
+/** Offset 0x085B - PCH Pm Reset Power Cycle Duration
+ Could be customized in the unit of second. Please refer to EDS for all support settings.
+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+ UINT8 PchPmPwrCycDur;
+
+/** Offset 0x085C - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x085D - PCH Legacy IO Low Latency Enable
+ Set to enable low latency of legacy IO. 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchLegacyIoLowLatency;
+
+/** Offset 0x085E - PCH Sata Pwr Opt Enable
+ SATA Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x085F - PCH Sata eSATA Speed Limit
+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+ $EN_DIS
+**/
+ UINT8 EsataSpeedLimit;
+
+/** Offset 0x0860 - PCH Sata Speed Limit
+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
+**/
+ UINT8 SataSpeedLimit;
+
+/** Offset 0x0861 - Enable SATA Port HotPlug
+ Enable SATA Port HotPlug.
+**/
+ UINT8 SataPortsHotPlug[8];
+
+/** Offset 0x0869 - Enable SATA Port Interlock Sw
+ Enable SATA Port Interlock Sw.
+**/
+ UINT8 SataPortsInterlockSw[8];
+
+/** Offset 0x0871 - Enable SATA Port External
+ Enable SATA Port External.
+**/
+ UINT8 SataPortsExternal[8];
+
+/** Offset 0x0879 - Enable SATA Port SpinUp
+ Enable the COMRESET initialization Sequence to the device.
+**/
+ UINT8 SataPortsSpinUp[8];
+
+/** Offset 0x0881 - Enable SATA Port Solid State Drive
+ 0: HDD; 1: SSD.
+**/
+ UINT8 SataPortsSolidStateDrive[8];
+
+/** Offset 0x0889 - Enable SATA Port Enable Dito Config
+ Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+**/
+ UINT8 SataPortsEnableDitoConfig[8];
+
+/** Offset 0x0891 - Enable SATA Port DmVal
+ DITO multiplier. Default is 15.
+**/
+ UINT8 SataPortsDmVal[8];
+
+/** Offset 0x0899
+**/
+ UINT8 UnusedUpdSpace21[1];
+
+/** Offset 0x089A - Enable SATA Port DmVal
+ DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+ UINT16 SataPortsDitoVal[8];
+
+/** Offset 0x08AA - Enable SATA Port ZpOdd
+ Support zero power ODD.
+**/
+ UINT8 SataPortsZpOdd[8];
+
+/** Offset 0x08B2 - PCH Sata Rst Raid Alternate Id
+ Enable RAID Alternate ID.
+ $EN_DIS
+**/
+ UINT8 SataRstRaidDeviceId;
+
+/** Offset 0x08B3 - PCH Sata Rst Raid0
+ RAID0.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid0;
+
+/** Offset 0x08B4 - PCH Sata Rst Raid1
+ RAID1.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid1;
+
+/** Offset 0x08B5 - PCH Sata Rst Raid10
+ RAID10.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid10;
+
+/** Offset 0x08B6 - PCH Sata Rst Raid5
+ RAID5.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid5;
+
+/** Offset 0x08B7 - PCH Sata Rst Irrt
+ Intel Rapid Recovery Technology.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrt;
+
+/** Offset 0x08B8 - PCH Sata Rst Orom Ui Banner
+ OROM UI and BANNER.
+ $EN_DIS
+**/
+ UINT8 SataRstOromUiBanner;
+
+/** Offset 0x08B9 - PCH Sata Rst Orom Ui Delay
+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
+**/
+ UINT8 SataRstOromUiDelay;
+
+/** Offset 0x08BA - PCH Sata Rst Hdd Unlock
+ Indicates that the HDD password unlock in the OS is enabled.
+ $EN_DIS
+**/
+ UINT8 SataRstHddUnlock;
+
+/** Offset 0x08BB - PCH Sata Rst Led Locate
+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
+ enabled on the OS.
+ $EN_DIS
+**/
+ UINT8 SataRstLedLocate;
+
+/** Offset 0x08BC - PCH Sata Rst Irrt Only
+ Allow only IRRT drives to span internal and external ports.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrtOnly;
+
+/** Offset 0x08BD - PCH Sata Rst Smart Storage
+ RST Smart Storage caching Bit.
+ $EN_DIS
+**/
+ UINT8 SataRstSmartStorage;
+
+/** Offset 0x08BE - PCH Sata Rst Pcie Storage Remap enable
+ Enable Intel RST for PCIe Storage remapping.
+**/
+ UINT8 SataRstPcieEnable[3];
+
+/** Offset 0x08C1 - PCH Sata Rst Pcie Storage Port
+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
+**/
+ UINT8 SataRstPcieStoragePort[3];
+
+/** Offset 0x08C4 - PCH Sata Rst Pcie Device Reset Delay
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+**/
+ UINT8 SataRstPcieDeviceResetDelay[3];
+
+/** Offset 0x08C7 - UFS enable/disable
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+ $EN_DIS
+**/
+ UINT8 UfsEnable[2];
+
+/** Offset 0x08C9 - IEH Mode
+ Integrated Error Handler Mode, 0: Bypass, 1: Enable
+ 0: Bypass, 1:Enable
+**/
+ UINT8 IehMode;
+
+/** Offset 0x08CA - Thermal Throttling Custimized T0Level Value
+ Custimized T0Level value.
+**/
+ UINT16 PchT0Level;
+
+/** Offset 0x08CC - Thermal Throttling Custimized T1Level Value
+ Custimized T1Level value.
+**/
+ UINT16 PchT1Level;
+
+/** Offset 0x08CE - Thermal Throttling Custimized T2Level Value
+ Custimized T2Level value.
+**/
+ UINT16 PchT2Level;
+
+/** Offset 0x08D0 - Enable The Thermal Throttle
+ Enable the thermal throttle function.
+ $EN_DIS
+**/
+ UINT8 PchTTEnable;
+
+/** Offset 0x08D1 - PMSync State 13
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+ at least T2 state.
+ $EN_DIS
+**/
+ UINT8 PchTTState13Enable;
+
+/** Offset 0x08D2 - Thermal Throttle Lock
+ Thermal Throttle Lock.
+ $EN_DIS
+**/
+ UINT8 PchTTLock;
+
+/** Offset 0x08D3 - Thermal Throttling Suggested Setting
+ Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 TTSuggestedSetting;
+
+/** Offset 0x08D4 - Enable PCH Cross Throttling
+ Enable/Disable PCH Cross Throttling
+ $EN_DIS
+**/
+ UINT8 TTCrossThrottling;
+
+/** Offset 0x08D5 - DMI Thermal Sensor Autonomous Width Enable
+ DMI Thermal Sensor Autonomous Width Enable.
+ $EN_DIS
+**/
+ UINT8 PchDmiTsawEn;
+
+/** Offset 0x08D6 - DMI Thermal Sensor Suggested Setting
+ DMT thermal sensor suggested representative values.
+ $EN_DIS
+**/
+ UINT8 DmiSuggestedSetting;
+
+/** Offset 0x08D7 - Thermal Sensor 0 Target Width
+ Thermal Sensor 0 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS0TW;
+
+/** Offset 0x08D8 - Thermal Sensor 1 Target Width
+ Thermal Sensor 1 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS1TW;
+
+/** Offset 0x08D9 - Thermal Sensor 2 Target Width
+ Thermal Sensor 2 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS2TW;
+
+/** Offset 0x08DA - Thermal Sensor 3 Target Width
+ Thermal Sensor 3 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS3TW;
+
+/** Offset 0x08DB - Port 0 T1 Multipler
+ Port 0 T1 Multipler.
+**/
+ UINT8 SataP0T1M;
+
+/** Offset 0x08DC - Port 0 T2 Multipler
+ Port 0 T2 Multipler.
+**/
+ UINT8 SataP0T2M;
+
+/** Offset 0x08DD - Port 0 T3 Multipler
+ Port 0 T3 Multipler.
+**/
+ UINT8 SataP0T3M;
+
+/** Offset 0x08DE - Port 0 Tdispatch
+ Port 0 Tdispatch.
+**/
+ UINT8 SataP0TDisp;
+
+/** Offset 0x08DF - Port 1 T1 Multipler
+ Port 1 T1 Multipler.
+**/
+ UINT8 SataP1T1M;
+
+/** Offset 0x08E0 - Port 1 T2 Multipler
+ Port 1 T2 Multipler.
+**/
+ UINT8 SataP1T2M;
+
+/** Offset 0x08E1 - Port 1 T3 Multipler
+ Port 1 T3 Multipler.
+**/
+ UINT8 SataP1T3M;
+
+/** Offset 0x08E2 - Port 1 Tdispatch
+ Port 1 Tdispatch.
+**/
+ UINT8 SataP1TDisp;
+
+/** Offset 0x08E3 - Port 0 Tinactive
+ Port 0 Tinactive.
+**/
+ UINT8 SataP0Tinact;
+
+/** Offset 0x08E4 - Port 0 Alternate Fast Init Tdispatch
+ Port 0 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP0TDispFinit;
+
+/** Offset 0x08E5 - Port 1 Tinactive
+ Port 1 Tinactive.
+**/
+ UINT8 SataP1Tinact;
+
+/** Offset 0x08E6 - Port 1 Alternate Fast Init Tdispatch
+ Port 1 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP1TDispFinit;
+
+/** Offset 0x08E7 - Sata Thermal Throttling Suggested Setting
+ Sata Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 SataThermalSuggestedSetting;
+
+/** Offset 0x08E8 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+ $EN_DIS
+**/
+ UINT8 PchMemoryThrottlingEnable;
+
+/** Offset 0x08E9 - Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPmsyncEnable[2];
+
+/** Offset 0x08EB - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryC0TransmitEnable[2];
+
+/** Offset 0x08ED - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPinSelection[2];
+
+/** Offset 0x08EF
+**/
+ UINT8 UnusedUpdSpace22;
+
+/** Offset 0x08F0 - Thermal Device Temperature
+ Decides the temperature.
+**/
+ UINT16 PchTemperatureHotLevel;
+
+/** Offset 0x08F2 - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x0902 - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x090C - Enable xHCI LTR override
+ Enables override of recommended LTR values for xHCI
+ $EN_DIS
+**/
+ UINT8 PchUsbLtrOverrideEnable;
+
+/** Offset 0x090D
+**/
+ UINT8 UnusedUpdSpace23[3];
+
+/** Offset 0x0910 - xHCI High Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x0914 - xHCI Medium Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x0918 - xHCI Low Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrLowIdleTimeOverride;
+
+/** Offset 0x091C - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x091D - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x091E - PCH Sata Rst Optane Memory
+ Optane Memory
+ $EN_DIS
+**/
+ UINT8 SataRstOptaneMemory;
+
+/** Offset 0x091F - PCH Sata Rst CPU Attached Storage
+ CPU Attached Storage
+ $EN_DIS
+**/
+ UINT8 SataRstCpuAttachedStorage;
+
+/** Offset 0x0920 - Enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+ emulation must be enabled, and WDAT table must not be exposed to the OS.
+ $EN_DIS
+**/
+ UINT8 EnableTcoTimer;
+
+/** Offset 0x0921 - Hybrid Storage Detection and Configuration Mode
+ Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
+ Default is 0: Disabled
+ 0: Disabled, 1: Dynamic Configuration
+**/
+ UINT8 HybridStorageMode;
+
+/** Offset 0x0922
+**/
+ UINT8 UnusedUpdSpace24[6];
+
+/** Offset 0x0928 - BgpdtHash[4]
+ BgpdtHash values
+**/
+ UINT64 BgpdtHash[4];
+
+/** Offset 0x0948 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
+
+/** Offset 0x094C
+**/
+ UINT8 UnusedUpdSpace25[4];
+
+/** Offset 0x0950 - BiosGuardModulePtr
+ BiosGuardModulePtr default values
+**/
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0958 - SendEcCmd
+ SendEcCmd function pointer. \n
+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
+**/
+ UINT64 SendEcCmd;
+
+/** Offset 0x0960 - EcCmdProvisionEav
+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+**/
+ UINT8 EcCmdProvisionEav;
+
+/** Offset 0x0961 - EcCmdLock
+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+**/
+ UINT8 EcCmdLock;
+
+/** Offset 0x0962
+**/
+ UINT8 UnusedUpdSpace26[6];
+
+/** Offset 0x0968 - SgxEpoch0
+ SgxEpoch0 default values
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0970 - SgxEpoch1
+ SgxEpoch1 default values
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x0978 - SgxSinitNvsData
+ SgxSinitNvsData default values
+**/
+ UINT8 SgxSinitNvsData;
+
+/** Offset 0x0979 - Si Config CSM Flag.
+ @deprecated Platform specific common policies that used by several silicon
+ components. CSM status flag.
+ $EN_DIS
+**/
+ UINT8 SiCsmFlag;
+
+/** Offset 0x097A - Skip Ssid Programming.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ $EN_DIS
+**/
+ UINT8 SiSkipSsidProgramming;
+
+/** Offset 0x097B
+**/
+ UINT8 UnusedUpdSpace27;
+
+/** Offset 0x097C - Change Default SVID
+ Change the default SVID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSvid;
+
+/** Offset 0x097E - Change Default SSID
+ Change the default SSID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSsid;
+
+/** Offset 0x0980 - SVID SDID table Poniter.
+ The address of the table of SVID SDID to customize each SVID SDID entry. This is
+ only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT32 SiSsidTablePtr;
+
+/** Offset 0x0984 - Number of ssid table.
+ SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+ This is only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiNumberOfSsidTableEntry;
+
+/** Offset 0x0986 - USB2 Port Reset Message Enable
+ 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
+**/
+ UINT8 PortResetMessageEnable[16];
+
+/** Offset 0x0996 - SATA RST Interrupt Mode
+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
+ 0:Msix, 1:Msi, 2:Legacy
+**/
+ UINT8 SataRstInterrupt;
+
+/** Offset 0x0997 - ME Unconfig on RTC clear
+ 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear.
+ 2: Cmos is clear, status unkonwn. 3: Reserved
+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+ is clear, 3: Reserved
+**/
+ UINT8 MeUnconfigOnRtcClear;
+
+/** Offset 0x0998 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x0999 - Pmc Cpu C10 Gate Pin Enable
+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+ and VccSTG rails instead of SLP_S0# pin.
+ $EN_DIS
+**/
+ UINT8 PmcCpuC10GatePinEnable;
+
+/** Offset 0x099A - Pch Dmi Aspm Ctrl
+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
+**/
+ UINT8 PchDmiAspmCtrl;
+
+/** Offset 0x099B - PchDmiCwbEnable
+ Central Write Buffer feature configurable and enabled by default
+ $EN_DIS
+**/
+ UINT8 PchDmiCwbEnable;
+
+/** Offset 0x099C - OS IDLE Mode Enable
+ Enable/Disable OS Idle Mode
+ $EN_DIS
+**/
+ UINT8 PmcOsIdleEnable;
+
+/** Offset 0x099D - S0ix Auto-Demotion
+ Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
+ $EN_DIS
+**/
+ UINT8 PchS0ixAutoDemotion;
+
+/** Offset 0x099E - Latch Events C10 Exit
+ When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
+ captured on C10 exit (instead of C10 entry which is default)
+ $EN_DIS
+**/
+ UINT8 PchPmLatchEventsC10Exit;
+
+/** Offset 0x099F - PCIE Eq Ph3 Lane Param Cm
+ CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieEqPh3LaneParamCm[32];
+
+/** Offset 0x09BF - PCIE Eq Ph3 Lane Param Cp
+ CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieEqPh3LaneParamCp[32];
+
+/** Offset 0x09DF - PCIE Hw Eq Gen3 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieHwEqGen3CoeffListCm[5];
+
+/** Offset 0x09E4 - PCIE Hw Eq Gen3 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieHwEqGen3CoeffListCp[5];
+
+/** Offset 0x09E9 - PCIE Hw Eq Gen4 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieHwEqGen4CoeffListCm[5];
+
+/** Offset 0x09EE - PCIE Hw Eq Gen4 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieHwEqGen4CoeffListCp[5];
+
+/** Offset 0x09F3 - Gen3 Root port preset values per lane
+ Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen3RootPortPreset[20];
+
+/** Offset 0x0A07 - Pcie Gen4 Root port preset values per lane
+ Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen4RootPortPreset[20];
+
+/** Offset 0x0A1B - Pcie Gen3 End port preset values per lane
+ Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen3EndPointPreset[20];
+
+/** Offset 0x0A2F - Pcie Gen4 End port preset values per lane
+ Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen4EndPointPreset[20];
+
+/** Offset 0x0A43 - Pcie Gen3 End port Hint values per lane
+ Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 CpuPcieGen3EndPointHint[20];
+
+/** Offset 0x0A57 - Pcie Gen4 End port Hint values per lane
+ Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 CpuPcieGen4EndPointHint[20];
+
+/** Offset 0x0A6B - CPU PCIe Fia Programming
+ Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieFiaProgramming;
+
+/** Offset 0x0A6C - CPU PCIe RootPort Clock Gating
+ Describes whether the PCI Express Clock Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieClockGating;
+
+/** Offset 0x0A6D - CPU PCIe RootPort Power Gating
+ Describes whether the PCI Express Power Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPciePowerGating;
+
+/** Offset 0x0A6E - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 CpuPcieComplianceTestMode;
+
+/** Offset 0x0A6F - PCIE Secure Register Lock
+ Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
+ load CpuPcieRpSetSecuredRegisterLock recipe. DEPRECATED 0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 CpuPcieSetSecuredRegisterLock;
+
+/** Offset 0x0A70 - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 CpuPcieEnablePeerMemoryWrite;
+
+/** Offset 0x0A71 - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 CpuPcieRpFunctionSwap;
+
+/** Offset 0x0A72 - PCI Express Slot Selection
+ Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieSlotSelection;
+
+/** Offset 0x0A73
+**/
+ UINT8 UnusedUpdSpace28;
+
+/** Offset 0x0A74 - CPU PCIE device override table pointer
+ The PCIe device table is being used to override PCIe device ASPM settings. This
+ is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
+ refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
+ must be 0.
+**/
+ UINT32 CpuPcieDeviceOverrideTablePtr;
+
+/** Offset 0x0A78 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 CpuPcieRpHotPlug[4];
+
+/** Offset 0x0A7C - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 CpuPcieRpPmSci[4];
+
+/** Offset 0x0A80 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 CpuPcieRpTransmitterHalfSwing[4];
+
+/** Offset 0x0A84 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 CpuPcieRpAcsEnabled[4];
+
+/** Offset 0x0A88 - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 CpuPcieRpEnableCpm[4];
+
+/** Offset 0x0A8C - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 CpuPcieRpAdvancedErrorReporting[4];
+
+/** Offset 0x0A90 - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 CpuPcieRpUnsupportedRequestReport[4];
+
+/** Offset 0x0A94 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 CpuPcieRpFatalErrorReport[4];
+
+/** Offset 0x0A98 - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 CpuPcieRpNoFatalErrorReport[4];
+
+/** Offset 0x0A9C - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 CpuPcieRpCorrectableErrorReport[4];
+
+/** Offset 0x0AA0 - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnFatalError[4];
+
+/** Offset 0x0AA4 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnNonFatalError[4];
+
+/** Offset 0x0AA8 - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnCorrectableError[4];
+
+/** Offset 0x0AAC - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 CpuPcieRpMaxPayload[4];
+
+/** Offset 0x0AB0 - DPC for PCIE RP Mask
+ Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpDpcEnabled[4];
+
+/** Offset 0x0AB4 - DPC Extensions PCIE RP Mask
+ Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
+ for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpDpcExtensionsEnabled[4];
+
+/** Offset 0x0AB8 - CPU PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 CpuPcieRpSlotImplemented[4];
+
+/** Offset 0x0ABC - PCIE RP Gen3 Equalization Phase Method
+ PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+ 1: hardware equalization; 4: Fixed Coeficients.
+**/
+ UINT8 CpuPcieRpGen3EqPh3Method[4];
+
+/** Offset 0x0AC0 - PCIE RP Gen4 Equalization Phase Method
+ PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+ 1: hardware equalization; 4: Fixed Coeficients.
+**/
+ UINT8 CpuPcieRpGen4EqPh3Method[4];
+
+/** Offset 0x0AC4 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 CpuPcieRpPhysicalSlotNumber[4];
+
+/** Offset 0x0AC8 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable;
+ 2: CpuPcieAspmL1(Default)
+**/
+ UINT8 CpuPcieRpAspm[4];
+
+/** Offset 0x0ACC - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL).
+ Default is CpuPcieL1SubstatesL1_1_2.
+**/
+ UINT8 CpuPcieRpL1Substates[4];
+
+/** Offset 0x0AD0 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 CpuPcieRpLtrEnable[4];
+
+/** Offset 0x0AD4 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 CpuPcieRpLtrConfigLock[4];
+
+/** Offset 0x0AD8 - PTM for PCIE RP Mask
+ Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on. [ALIAS_NAME RpPtmBytes]
+**/
+ UINT8 CpuPcieRpPtmEnabled[4];
+
+/** Offset 0x0ADC - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 CpuPcieRpDetectTimeoutMs[4];
+
+/** Offset 0x0AE4 - VC for PCIE RP Mask
+ Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit
+ for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpVcEnabled[4];
+
+/** Offset 0x0AE8 - Multi-VC for PCIE RP Mask
+ Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpMultiVcEnabled[4];
+
+/** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x0AF6 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default
+ = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTran[10];
+
+/** Offset 0x0B00 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x0B0A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x0B14 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x0B1E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x0B28 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x0B32 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x0B3C - Skip PAM regsiter lock
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ $EN_DIS
+**/
+ UINT8 SkipPamLock;
+
+/** Offset 0x0B3D - EDRAM Test Mode
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
+**/
+ UINT8 EdramTestMode;
+
+/** Offset 0x0B3E - Enable/Disable IGFX RenderStandby
+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+ $EN_DIS
+**/
+ UINT8 RenderStandby;
+
+/** Offset 0x0B3F - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x0B40 - Enable/Disable CdynmaxClamp
+ Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
+ $EN_DIS
+**/
+ UINT8 CdynmaxClampEnable;
+
+/** Offset 0x0B41 - GT Frequency Limit
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+**/
+ UINT8 GtFreqMax;
+
+/** Offset 0x0B42 - Disable Turbo GT
+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
+ $EN_DIS
+**/
+ UINT8 DisableTurboGt;
+
+/** Offset 0x0B43 - Enable/Disable CdClock Init
+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
+ CD clock if not initialized by Gfx PEIM
+ $EN_DIS
+**/
+ UINT8 SkipCdClockInit;
+
+/** Offset 0x0B44 - Enable RC1p frequency request to PMA (provided all other conditions are met)
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 RC1pFreqEnable;
+
+/** Offset 0x0B45 - Enable TSN Multi-VC
+ Enable/disable Multi Virtual Channels(VC) in TSN.
+ $EN_DIS
+**/
+ UINT8 PchTsnMultiVcEnable;
+
+/** Offset 0x0B46 - SaPostMemTestRsvd
+ Reserved for SA Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPostMemTestRsvd[13];
+
+/** Offset 0x0B53 - RSR feature
+ Enable or Disable RSR feature; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableRsr;
+
+/** Offset 0x0B54 - 1-Core Ratio Limit
+ 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
+ to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
+**/
+ UINT8 OneCoreRatioLimit;
+
+/** Offset 0x0B55 - 2-Core Ratio Limit
+ 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 TwoCoreRatioLimit;
+
+/** Offset 0x0B56 - 3-Core Ratio Limit
+ 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 ThreeCoreRatioLimit;
+
+/** Offset 0x0B57 - 4-Core Ratio Limit
+ 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 FourCoreRatioLimit;
+
+/** Offset 0x0B58 - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable;
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x0B59 - Hardware Duty Cycle Control
+ Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 HdcControl;
+
+/** Offset 0x0B5A - Package Long duration turbo mode time
+ Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
+ 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PowerLimit1Time;
+
+/** Offset 0x0B5B - Short Duration Turbo Mode
+ Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit2;
+
+/** Offset 0x0B5C - Turbo settings Lock
+ Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable
+ $EN_DIS
+**/
+ UINT8 TurboPowerLimitLock;
+
+/** Offset 0x0B5D - Package PL3 time window
+ Package PL3 time window range for this policy from 0 to 64ms
+**/
+ UINT8 PowerLimit3Time;
+
+/** Offset 0x0B5E - Package PL3 Duty Cycle
+ Package PL3 Duty Cycle; Valid Range is 0 to 100
+**/
+ UINT8 PowerLimit3DutyCycle;
+
+/** Offset 0x0B5F - Package PL3 Lock
+ Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit3Lock;
+
+/** Offset 0x0B60 - Package PL4 Lock
+ Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit4Lock;
+
+/** Offset 0x0B61 - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
+ 10, For all other SKUs the recommended default are 0
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x0B62 - Tcc Offset Clamp Enable/Disable
+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
+ below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled,
+ For all other SKUs the recommended default are 0: Disabled.
+ $EN_DIS
+**/
+ UINT8 TccOffsetClamp;
+
+/** Offset 0x0B63 - Tcc Offset Lock
+ Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+ target; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 TccOffsetLock;
+
+/** Offset 0x0B64 - Custom Ratio State Entries
+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+ ratio table.Sets the number of custom P-states. At least 2 states must be present
+**/
+ UINT8 NumberOfEntries;
+
+/** Offset 0x0B65 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
+**/
+ UINT8 Custom1PowerLimit1Time;
+
+/** Offset 0x0B66 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
+**/
+ UINT8 Custom1TurboActivationRatio;
+
+/** Offset 0x0B67 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom1ConfigTdpControl;
+
+/** Offset 0x0B68 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
+**/
+ UINT8 Custom2PowerLimit1Time;
+
+/** Offset 0x0B69 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
+**/
+ UINT8 Custom2TurboActivationRatio;
+
+/** Offset 0x0B6A - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom2ConfigTdpControl;
+
+/** Offset 0x0B6B - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
+**/
+ UINT8 Custom3PowerLimit1Time;
+
+/** Offset 0x0B6C - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
+**/
+ UINT8 Custom3TurboActivationRatio;
+
+/** Offset 0x0B6D - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom3ConfigTdpControl;
+
+/** Offset 0x0B6E - ConfigTdp mode settings Lock
+ Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ConfigTdpLock;
+
+/** Offset 0x0B6F - Load Configurable TDP SSDT
+ Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ConfigTdpBios;
+
+/** Offset 0x0B70 - PL1 Enable value
+ PL1 Enable value to limit average platform power. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit1;
+
+/** Offset 0x0B71 - PL1 timewindow
+ PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
+ , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PsysPowerLimit1Time;
+
+/** Offset 0x0B72 - PL2 Enable Value
+ PL2 Enable activates the PL2 value to limit average platform power.0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit2;
+
+/** Offset 0x0B73 - Enable or Disable MLC Streamer Prefetcher
+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MlcStreamerPrefetcher;
+
+/** Offset 0x0B74 - Enable or Disable MLC Spatial Prefetcher
+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 MlcSpatialPrefetcher;
+
+/** Offset 0x0B75 - Enable or Disable Monitor /MWAIT instructions
+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x0B76 - Enable or Disable initialization of machine check registers
+ Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MachineCheckEnable;
+
+/** Offset 0x0B77 - AP Idle Manner of waiting for SIPI
+ AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop.
+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop
+**/
+ UINT8 ApIdleManner;
+
+/** Offset 0x0B78 - Control on Processor Trace output scheme
+ Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
+ 0: Single Range Output, 1: ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x0B79 - Enable or Disable Processor Trace feature
+ Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x0B7A - Enable or Disable Intel SpeedStep Technology
+ Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x0B7B - Enable or Disable Energy Efficient P-state
+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
+ 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientPState;
+
+/** Offset 0x0B7C - Enable or Disable Energy Efficient Turbo
+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
+ 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientTurbo;
+
+/** Offset 0x0B7D - Enable or Disable T states
+ Enable or Disable T states; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TStates;
+
+/** Offset 0x0B7E - Enable or Disable Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 BiProcHot;
+
+/** Offset 0x0B7F - Enable or Disable PROCHOT# signal being driven externally
+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableProcHotOut;
+
+/** Offset 0x0B80 - Enable or Disable PROCHOT# Response
+ Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcHotResponse;
+
+/** Offset 0x0B81 - Enable or Disable VR Thermal Alert
+ Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableVrThermalAlert;
+
+/** Offset 0x0B82 - Enable or Disable Thermal Reporting
+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 EnableAllThermalFunctions;
+
+/** Offset 0x0B83 - Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ThermalMonitor;
+
+/** Offset 0x0B84 - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x0B85 - Configure C-State Configuration Lock
+ Configure C-State Configuration Lock; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PmgCstCfgCtrlLock;
+
+/** Offset 0x0B86 - Enable or Disable Enhanced C-states
+ Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x0B87 - Enable or Disable Package Cstate Demotion
+ Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x0B88 - Enable or Disable Package Cstate UnDemotion
+ Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x0B89 - Enable or Disable CState-Pre wake
+ Enable or Disable CState-Pre wake. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 CStatePreWake;
+
+/** Offset 0x0B8A - Enable or Disable TimedMwait Support.
+ Enable or Disable TimedMwait Support. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 TimedMwait;
+
+/** Offset 0x0B8B - Enable or Disable IO to MWAIT redirection
+ Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CstCfgCtrIoMwaitRedirection;
+
+/** Offset 0x0B8C - Set the Max Pkg Cstate
+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x0B8D - TimeUnit for C-State Latency Control0
+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl0TimeUnit;
+
+/** Offset 0x0B8E - TimeUnit for C-State Latency Control1
+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl1TimeUnit;
+
+/** Offset 0x0B8F - TimeUnit for C-State Latency Control2
+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl2TimeUnit;
+
+/** Offset 0x0B90 - TimeUnit for C-State Latency Control3
+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl3TimeUnit;
+
+/** Offset 0x0B91 - TimeUnit for C-State Latency Control4
+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl4TimeUnit;
+
+/** Offset 0x0B92 - TimeUnit for C-State Latency Control5
+ TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl5TimeUnit;
+
+/** Offset 0x0B93 - Interrupt Redirection Mode Select
+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
+ No change.
+**/
+ UINT8 PpmIrmSetting;
+
+/** Offset 0x0B94 - Lock prochot configuration
+ Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ProcHotLock;
+
+/** Offset 0x0B95 - Configuration for boot TDP selection
+ Deprecated. Move to premem.
+**/
+ UINT8 DeprecatedConfigTdpLevel;
+
+/** Offset 0x0B96 - Max P-State Ratio
+ Max P-State Ratio, Valid Range 0 to 0x7F
+**/
+ UINT8 MaxRatio;
+
+/** Offset 0x0B97 - P-state ratios for custom P-state table
+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+ are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatio[40];
+
+/** Offset 0x0BBF - P-state ratios for max 16 version of custom P-state table
+ P-state ratios for max 16 version of custom P-state table. This table is used for
+ OS versions limited to a max of 16 P-States. If the first entry of this table is
+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
+ of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatioMax16[16];
+
+/** Offset 0x0BCF
+**/
+ UINT8 UnusedUpdSpace29;
+
+/** Offset 0x0BD0 - Platform Power Pmax
+ PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments.
+ Range 0-1024 Watts. Value of 800 = 100W
+**/
+ UINT16 PsysPmax;
+
+/** Offset 0x0BD2 - Interrupt Response Time Limit of C-State LatencyContol1
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl1Irtl;
+
+/** Offset 0x0BD4 - Interrupt Response Time Limit of C-State LatencyContol2
+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl2Irtl;
+
+/** Offset 0x0BD6 - Interrupt Response Time Limit of C-State LatencyContol3
+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl3Irtl;
+
+/** Offset 0x0BD8 - Interrupt Response Time Limit of C-State LatencyContol4
+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl4Irtl;
+
+/** Offset 0x0BDA - Interrupt Response Time Limit of C-State LatencyContol5
+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl5Irtl;
+
+/** Offset 0x0BDC - Package Long duration turbo mode power limit
+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ Valid Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit1;
+
+/** Offset 0x0BE0 - Package Short duration turbo mode power limit
+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit2Power;
+
+/** Offset 0x0BE4 - Package PL3 power limit
+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit3;
+
+/** Offset 0x0BE8 - Package PL4 power limit
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit4;
+
+/** Offset 0x0BEC - Tcc Offset Time Window for RATL
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 TccOffsetTimeWindowForRatl;
+
+/** Offset 0x0BF0 - Short term Power Limit value for custom cTDP level 1
+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit1;
+
+/** Offset 0x0BF4 - Long term Power Limit value for custom cTDP level 1
+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit2;
+
+/** Offset 0x0BF8 - Short term Power Limit value for custom cTDP level 2
+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit1;
+
+/** Offset 0x0BFC - Long term Power Limit value for custom cTDP level 2
+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit2;
+
+/** Offset 0x0C00 - Short term Power Limit value for custom cTDP level 3
+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit1;
+
+/** Offset 0x0C04 - Long term Power Limit value for custom cTDP level 3
+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit2;
+
+/** Offset 0x0C08 - Platform PL1 power
+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit1Power;
+
+/** Offset 0x0C0C - Platform PL2 power
+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit2Power;
+
+/** Offset 0x0C10 - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+ through MSR 1FC bit 20)Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x0C11 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents Three
+ Strike counter from incrementing; 0: False; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0C12 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 HwpInterruptControl;
+
+/** Offset 0x0C13 - 5-Core Ratio Limit
+ 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 FiveCoreRatioLimit;
+
+/** Offset 0x0C14 - 6-Core Ratio Limit
+ 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SixCoreRatioLimit;
+
+/** Offset 0x0C15 - 7-Core Ratio Limit
+ 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SevenCoreRatioLimit;
+
+/** Offset 0x0C16 - 8-Core Ratio Limit
+ 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 EightCoreRatioLimit;
+
+/** Offset 0x0C17 - Intel Turbo Boost Max Technology 3.0
+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 EnableItbm;
+
+/** Offset 0x0C18 - Intel Turbo Boost Max Technology 3.0 Driver
+ @Deprecated: Intel Turbo Boost Max Technology 3.0 Driver doesn't support for TGL
+ $EN_DIS
+**/
+ UINT8 EnableItbmDriver;
+
+/** Offset 0x0C19 - Enable or Disable C1 Cstate Demotion
+ Enable or Disable C1 Cstate Demotion. Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1StateAutoDemotion;
+
+/** Offset 0x0C1A - Enable or Disable C1 Cstate UnDemotion
+ Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1StateUnDemotion;
+
+/** Offset 0x0C1B - Minimum Ring ratio limit override
+ Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MinRingRatioLimit;
+
+/** Offset 0x0C1C - Maximum Ring ratio limit override
+ Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MaxRingRatioLimit;
+
+/** Offset 0x0C1D - Enable or Disable Per Core P State OS control
+ Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnablePerCorePState;
+
+/** Offset 0x0C1E - Enable or Disable HwP Autonomous Per Core P State OS control
+ Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1:
+ Enable
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoPerCorePstate;
+
+/** Offset 0x0C1F - Enable or Disable HwP Autonomous EPP Grouping
+ Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoEppGrouping;
+
+/** Offset 0x0C20 - Enable or Disable EPB override over PECI
+ Enable or Disable EPB override over PECI. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableEpbPeciOverride;
+
+/** Offset 0x0C21 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
+ Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableFastMsrHwpReq;
+
+/** Offset 0x0C22 - Enable Configurable TDP
+ Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP;
+ 1: Applies to cTDP
+ $EN_DIS
+**/
+ UINT8 ApplyConfigTdp;
+
+/** Offset 0x0C23 - Enable VccIn Demotion Override Configuration
+ Enable VccIn Demotion Override Configuration. The timing can be configured by VccInDemotionMs.
+ $EN_DIS
+**/
+ UINT8 VccInDemotionOverride;
+
+/** Offset 0x0C24 - Customize the VccIn Demotion in ms.
+ Customize the VccIn Demotion in ms accordingly. Values used by OEM expected to be
+ in lower end of 1-30 ms range. Value 1 means 1ms, value 2 means 2ms, and so on.
+ Value 0 will disable VccIn Demotion knob. It's 30ms by silicon default
+**/
+ UINT32 VccInDemotionMs;
+
+/** Offset 0x0C28 - ReservedCpuPostMemTest
+ Reserved for CPU Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemTest[11];
+
+/** Offset 0x0C33 - SgxSinitDataFromTpm
+ SgxSinitDataFromTpm default values
+**/
+ UINT8 SgxSinitDataFromTpm;
+
+/** Offset 0x0C34
+**/
+ UINT8 SecurityPostMemRsvd[16];
+
+/** Offset 0x0C44 - End of Post message
+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+ UINT8 EndOfPostMessage;
+
+/** Offset 0x0C45 - D0I3 Setting for HECI Disable
+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+ HECI devices
+ $EN_DIS
+**/
+ UINT8 DisableD0I3SettingForHeci;
+
+/** Offset 0x0C46 - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x0C47 - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x0C48 - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x0C49 - PCH Unlock SideBand access
+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+ $EN_DIS
+**/
+ UINT8 PchSbAccessUnlock;
+
+/** Offset 0x0C4A - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x0C7A - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0CAA - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0CC2 - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0CDA - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D0A - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0D22 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0D3A - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D6A - PCIE RP Slot Power Limit Scale
+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+ UINT8 PcieRpSlotPowerLimitScale[24];
+
+/** Offset 0x0D82 - PCIE RP Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+ UINT16 PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0DB2 - PCIE RP Enable Port8xh Decode
+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePort8xhDecode;
+
+/** Offset 0x0DB3 - PCIE Port8xh Decode Port Index
+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
+**/
+ UINT8 PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0DB4 - PCH Energy Reporting
+ Disable/Enable PCH to CPU energy report feature.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableEnergyReport;
+
+/** Offset 0x0DB5 - PCH Sata Test Mode
+ Allow entrance to the PCH SATA test modes.
+ $EN_DIS
+**/
+ UINT8 SataTestMode;
+
+/** Offset 0x0DB6 - PCH USB OverCurrent mapping lock enable
+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+ $EN_DIS
+**/
+ UINT8 PchXhciOcLock;
+
+/** Offset 0x0DB7 - Low Power Mode Enable/Disable config mask
+ Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+ to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+ LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. [ALIAS_NAME LpmStateEnableMask]
+**/
+ UINT8 PmcLpmS0ixSubStateEnableMask;
+
+/** Offset 0x0DB8 - Mctp Broadcast Cycle
+ Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MctpBroadcastCycle;
+
+/** Offset 0x0DB9
+**/
+ UINT8 UnusedUpdSpace30[1];
+
+/** Offset 0x0DBA - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 CpuPcieRpLtrMaxSnoopLatency[4];
+
+/** Offset 0x0DC2 - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4];
+
+/** Offset 0x0DCA - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 CpuPcieRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0DCE - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0DD2 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 CpuPcieRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x0DDA - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0DDE - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0DE2 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x0DEA - PCIE RP Upstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
+**/
+ UINT8 CpuPcieRpGen3Uptp[4];
+
+/** Offset 0x0DEE - PCIE RP Downstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
+**/
+ UINT8 CpuPcieRpGen3Dptp[4];
+
+/** Offset 0x0DF2 - PCIE RP Upstream Port Transmiter Preset
+ Used during Gen4 Link Equalization. Used for all lanes. Default is 8.
+**/
+ UINT8 CpuPcieRpGen4Uptp[4];
+
+/** Offset 0x0DF6 - PCIE RP Downstream Port Transmiter Preset
+ Used during Gen4 Link Equalization. Used for all lanes. Default is 9.
+**/
+ UINT8 CpuPcieRpGen4Dptp[4];
+
+/** Offset 0x0DFA - PMC C10 dynamic threshold dajustment enable
+ Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
+ $EN_DIS
+**/
+ UINT8 PmcC10DynamicThresholdAdjustment;
+
+/** Offset 0x0DFB - FOMS Control Policy
+ Choose the Foms Control Policy, Default = 0
+ 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+ UINT8 CpuPcieFomsCp[4];
+
+/** Offset 0x0DFF
+**/
+ UINT8 UnusedUpdSpace31;
+
+/** Offset 0x0E00 - LogoPixelHeight Address
+ Address of LogoPixelHeight
+**/
+ UINT32 LogoPixelHeight;
+
+/** Offset 0x0E04 - LogoPixelWidth Address
+ Address of LogoPixelWidth
+**/
+ UINT32 LogoPixelWidth;
+
+/** Offset 0x0E08 - P2P mode for PCIE RP
+ Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable.
+ 0: Disable, 1: Enable
+**/
+ UINT8 CpuPcieRpPeerToPeerMode[4];
+
+/** Offset 0x0E0C - Map port under VMD
+ Map/UnMap port under VMD
+ $EN_DIS
+**/
+ UINT8 VmdPort[31];
+
+/** Offset 0x0E2B - VMD Port Device
+ VMD Root port device number.
+**/
+ UINT8 VmdPortDev[31];
+
+/** Offset 0x0E4A - VMD Port Func
+ VMD Root port function number.
+**/
+ UINT8 VmdPortFunc[31];
+
+/** Offset 0x0E69
+**/
+ UINT8 UnusedUpdSpace32[3];
+
+/** Offset 0x0E6C - VMD Variable
+ VMD Variable Pointer.
+**/
+ UINT32 VmdVariablePtr;
+
+/** Offset 0x0E70 - Thermal Design Current time window
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 TdcTimeWindow1[5];
+
+/** Offset 0x0E84 - Temporary CfgBar address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdCfgBarBase;
+
+/** Offset 0x0E88 - Temporary MemBar1 address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdMemBar1Base;
+
+/** Offset 0x0E8C - Temporary MemBar2 address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdMemBar2Base;
+
+/** Offset 0x0E90 - PCH TSN1 MAC Address High Bits
+ Set TSN1 MAC Address High.
+**/
+ UINT32 PchTsn1MacAddressHigh;
+
+/** Offset 0x0E94 - PCH TSN1 MAC Address Low Bits
+ Set TSN1 MAC Address Low.
+**/
+ UINT32 PchTsn1MacAddressLow;
+
+/** Offset 0x0E98 - FspEventHandler
+ Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
+**/
+ UINT32 FspEventHandler;
+
+/** Offset 0x0E9C - Enable VMD Global Mapping
+ Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 VmdGlobalMapping;
+
+/** Offset 0x0E9D - PCH XHCI LTR Mode Enable
+ Enable/Disable PCH XHCI LTR Mode.0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PchXhciLtrModeEnable;
+
+/** Offset 0x0E9E
+**/
+ UINT8 UnusedUpdSpace33[3];
+
+/** Offset 0x0EA1
+**/
+ UINT8 ReservedFspsUpd[7];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0EA8
+**/
+ UINT8 UnusedUpdSpace34[6];
+
+/** Offset 0x0EAE
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3050/FSP/Include/FsptUpd.h b/models/gaze16-3050/FSP/Include/FsptUpd.h
new file mode 100644
index 0000000..e185735
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FsptUpd.h
@@ -0,0 +1,290 @@
+/** @file FsptUpd.h
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionSize;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - PcdSerialIoUartDebugEnable
+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0041 - PcdSerialIoUartNumber
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIoUartNumber;
+
+/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 PcdSerialIoUartMode;
+
+/** Offset 0x0043
+**/
+ UINT8 UnusedUpdSpace0;
+
+/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 PcdSerialIoUartBaudRate;
+
+/** Offset 0x0048 - Pci Express Base Address
+ Base address to be programmed for Pci Express
+**/
+ UINT64 PcdPciExpressBaseAddress;
+
+/** Offset 0x0050 - Pci Express Region Length
+ Region Length to be programmed for Pci Express
+**/
+ UINT32 PcdPciExpressRegionLength;
+
+/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 PcdSerialIoUartParity;
+
+/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 PcdSerialIoUartDataBits;
+
+/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 PcdSerialIoUartStopBits;
+
+/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
+ Enables UART hardware flow control, CTS and RTS lines.
+ 0: Disable, 1:Enable
+**/
+ UINT8 PcdSerialIoUartAutoFlow;
+
+/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 PcdSerialIoUartRxPinMux;
+
+/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
+ Select TX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 PcdSerialIoUartTxPinMux;
+
+/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
+ Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIoUartRtsPinMux;
+
+/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
+ Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIoUartCtsPinMux;
+
+/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 PcdSerialIoUartDebugMmioBase;
+
+/** Offset 0x006C - PcdLpcUartDebugEnable
+ Enable to initialize LPC Uart device in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 PcdLpcUartDebugEnable;
+
+/** Offset 0x006D - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x006E - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x006F - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x0070 - PcdSerialIo2ndUartEnable
+ Enable Additional SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIo2ndUartEnable;
+
+/** Offset 0x0071 - PcdSerialIo2ndUartNumber
+ Select SerialIo Uart Controller Number
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIo2ndUartNumber;
+
+/** Offset 0x0072 - PcdSerialIo2ndUartMode - FSPT
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 PcdSerialIo2ndUartMode;
+
+/** Offset 0x0073
+**/
+ UINT8 UnusedUpdSpace1;
+
+/** Offset 0x0074 - PcdSerialIo2ndUartBaudRate - FSPT
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 PcdSerialIo2ndUartBaudRate;
+
+/** Offset 0x0078 - PcdSerialIo2ndUartParity - FSPT
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 PcdSerialIo2ndUartParity;
+
+/** Offset 0x0079 - PcdSerialIo2ndUartDataBits - FSPT
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 PcdSerialIo2ndUartDataBits;
+
+/** Offset 0x007A - PcdSerialIo2ndUartStopBits - FSPT
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 PcdSerialIo2ndUartStopBits;
+
+/** Offset 0x007B - PcdSerialIo2ndUartAutoFlow - FSPT
+ Enables UART hardware flow control, CTS and RTS lines.
+ 0: Disable, 1:Enable
+**/
+ UINT8 PcdSerialIo2ndUartAutoFlow;
+
+/** Offset 0x007C - PcdSerialIo2ndUartRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART
+**/
+ UINT32 PcdSerialIo2ndUartRxPinMux;
+
+/** Offset 0x0080 - PcdSerialIo2ndUartTxPinMux - FSPT
+ Select TX pin muxing for SerialIo UART
+**/
+ UINT32 PcdSerialIo2ndUartTxPinMux;
+
+/** Offset 0x0084 - PcdSerialIo2ndUartRtsPinMux - FSPT
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIo2ndUartRtsPinMux;
+
+/** Offset 0x0088 - PcdSerialIo2ndUartCtsPinMux - FSPT
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIo2ndUartCtsPinMux;
+
+/** Offset 0x008C - PcdSerialIo2ndUartMmioBase - FSPT
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 PcdSerialIo2ndUartMmioBase;
+
+/** Offset 0x0090
+**/
+ UINT32 TopMemoryCacheSize;
+
+/** Offset 0x0094 - FspDebugHandler
+ Optional pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
+**/
+ UINT32 FspDebugHandler;
+
+/** Offset 0x0098
+**/
+ UINT8 UnusedUpdSpace2[4];
+
+/** Offset 0x009C
+**/
+ UINT8 ReservedFsptUpd1[20];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSP_T_CONFIG FsptConfig;
+
+/** Offset 0x00B0
+**/
+ UINT8 UnusedUpdSpace3[6];
+
+/** Offset 0x00B6
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3050/FSP/Include/FusaInfoHob.h b/models/gaze16-3050/FSP/Include/FusaInfoHob.h
new file mode 100644
index 0000000..279322b
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/FusaInfoHob.h
@@ -0,0 +1,138 @@
+/** @file
+ This file contains definitions required for creation of TGL
+ end-to-end check-the-checker test result hob.
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _FUSA_INFO_HOB_H_
+#define _FUSA_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiFusaInfoGuid;
+
+/**
+ FuSa Info HOB version
+ Use this to compare to the HOB retrieved from the FSP for the
+ exact match
+**/
+#define FUSA_INFO_VERSION 0x00000100
+
+/** Constants used for FUSA_TEST_RESULT->CheckResults[] and
+ * FUSA_TEST_RESULT->TestResult */
+/**@defgroup ResultConstant Check Result Constants*/
+/**@{*/
+#define FUSA_TEST_DEVICE_NOTAVAILABLE 0xFF /**TestNumber will have this value.
+
+ @note While the core4-7 (cbo4-7) that are strictly related to
+ the TGL-H are listed, there are not within the
+ implementation scope and validation scope yet.
+**/
+typedef enum
+{
+ FusaTestNumMc0Cmi = 0, ///
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination and voltage tolerance.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 2;
+ UINT32 RsvdBits : 17; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+
+
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ ///
+ /// Deprecated settings. Maintained only for compatibility.
+ ///
+ GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
+ GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
+ GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
+ GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
+
+ ///
+ /// New GPIO reset configuration options
+ ///
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Set GPIO termination and Pad Tolerance (applicable only for some pads)
+ Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F,
+ GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
+ GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioLockPadConfig and GpioLockOutputState can be OR'ed.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controllable
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad.
+**/
+typedef enum {
+ GpioLockDefault = 0x0, ///< Leave lock setting unmodified
+ GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
+ GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/models/gaze16-3050/FSP/Include/GpioSampleDef.h b/models/gaze16-3050/FSP/Include/GpioSampleDef.h
new file mode 100644
index 0000000..eec4316
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/GpioSampleDef.h
@@ -0,0 +1,359 @@
+/** @file
+
+ @copyright
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __GPIOCONFIG_H__
+#define __GPIOCONFIG_H__
+#include
+#include
+#include
+
+/*
+ SKL LP GPIO pins
+ Use below for functions from PCH GPIO Lib which
+ require GpioPad as argument. Encoding used here
+ has all information required by library functions
+*/
+#define GPIO_SKL_LP_GPP_A0 0x02000000
+#define GPIO_SKL_LP_GPP_A1 0x02000001
+#define GPIO_SKL_LP_GPP_A2 0x02000002
+#define GPIO_SKL_LP_GPP_A3 0x02000003
+#define GPIO_SKL_LP_GPP_A4 0x02000004
+#define GPIO_SKL_LP_GPP_A5 0x02000005
+#define GPIO_SKL_LP_GPP_A6 0x02000006
+#define GPIO_SKL_LP_GPP_A7 0x02000007
+#define GPIO_SKL_LP_GPP_A8 0x02000008
+#define GPIO_SKL_LP_GPP_A9 0x02000009
+#define GPIO_SKL_LP_GPP_A10 0x0200000A
+#define GPIO_SKL_LP_GPP_A11 0x0200000B
+#define GPIO_SKL_LP_GPP_A12 0x0200000C
+#define GPIO_SKL_LP_GPP_A13 0x0200000D
+#define GPIO_SKL_LP_GPP_A14 0x0200000E
+#define GPIO_SKL_LP_GPP_A15 0x0200000F
+#define GPIO_SKL_LP_GPP_A16 0x02000010
+#define GPIO_SKL_LP_GPP_A17 0x02000011
+#define GPIO_SKL_LP_GPP_A18 0x02000012
+#define GPIO_SKL_LP_GPP_A19 0x02000013
+#define GPIO_SKL_LP_GPP_A20 0x02000014
+#define GPIO_SKL_LP_GPP_A21 0x02000015
+#define GPIO_SKL_LP_GPP_A22 0x02000016
+#define GPIO_SKL_LP_GPP_A23 0x02000017
+#define GPIO_SKL_LP_GPP_B0 0x02010000
+#define GPIO_SKL_LP_GPP_B1 0x02010001
+#define GPIO_SKL_LP_GPP_B2 0x02010002
+#define GPIO_SKL_LP_GPP_B3 0x02010003
+#define GPIO_SKL_LP_GPP_B4 0x02010004
+#define GPIO_SKL_LP_GPP_B5 0x02010005
+#define GPIO_SKL_LP_GPP_B6 0x02010006
+#define GPIO_SKL_LP_GPP_B7 0x02010007
+#define GPIO_SKL_LP_GPP_B8 0x02010008
+#define GPIO_SKL_LP_GPP_B9 0x02010009
+#define GPIO_SKL_LP_GPP_B10 0x0201000A
+#define GPIO_SKL_LP_GPP_B11 0x0201000B
+#define GPIO_SKL_LP_GPP_B12 0x0201000C
+#define GPIO_SKL_LP_GPP_B13 0x0201000D
+#define GPIO_SKL_LP_GPP_B14 0x0201000E
+#define GPIO_SKL_LP_GPP_B15 0x0201000F
+#define GPIO_SKL_LP_GPP_B16 0x02010010
+#define GPIO_SKL_LP_GPP_B17 0x02010011
+#define GPIO_SKL_LP_GPP_B18 0x02010012
+#define GPIO_SKL_LP_GPP_B19 0x02010013
+#define GPIO_SKL_LP_GPP_B20 0x02010014
+#define GPIO_SKL_LP_GPP_B21 0x02010015
+#define GPIO_SKL_LP_GPP_B22 0x02010016
+#define GPIO_SKL_LP_GPP_B23 0x02010017
+#define GPIO_SKL_LP_GPP_C0 0x02020000
+#define GPIO_SKL_LP_GPP_C1 0x02020001
+#define GPIO_SKL_LP_GPP_C2 0x02020002
+#define GPIO_SKL_LP_GPP_C3 0x02020003
+#define GPIO_SKL_LP_GPP_C4 0x02020004
+#define GPIO_SKL_LP_GPP_C5 0x02020005
+#define GPIO_SKL_LP_GPP_C6 0x02020006
+#define GPIO_SKL_LP_GPP_C7 0x02020007
+#define GPIO_SKL_LP_GPP_C8 0x02020008
+#define GPIO_SKL_LP_GPP_C9 0x02020009
+#define GPIO_SKL_LP_GPP_C10 0x0202000A
+#define GPIO_SKL_LP_GPP_C11 0x0202000B
+#define GPIO_SKL_LP_GPP_C12 0x0202000C
+#define GPIO_SKL_LP_GPP_C13 0x0202000D
+#define GPIO_SKL_LP_GPP_C14 0x0202000E
+#define GPIO_SKL_LP_GPP_C15 0x0202000F
+#define GPIO_SKL_LP_GPP_C16 0x02020010
+#define GPIO_SKL_LP_GPP_C17 0x02020011
+#define GPIO_SKL_LP_GPP_C18 0x02020012
+#define GPIO_SKL_LP_GPP_C19 0x02020013
+#define GPIO_SKL_LP_GPP_C20 0x02020014
+#define GPIO_SKL_LP_GPP_C21 0x02020015
+#define GPIO_SKL_LP_GPP_C22 0x02020016
+#define GPIO_SKL_LP_GPP_C23 0x02020017
+#define GPIO_SKL_LP_GPP_D0 0x02030000
+#define GPIO_SKL_LP_GPP_D1 0x02030001
+#define GPIO_SKL_LP_GPP_D2 0x02030002
+#define GPIO_SKL_LP_GPP_D3 0x02030003
+#define GPIO_SKL_LP_GPP_D4 0x02030004
+#define GPIO_SKL_LP_GPP_D5 0x02030005
+#define GPIO_SKL_LP_GPP_D6 0x02030006
+#define GPIO_SKL_LP_GPP_D7 0x02030007
+#define GPIO_SKL_LP_GPP_D8 0x02030008
+#define GPIO_SKL_LP_GPP_D9 0x02030009
+#define GPIO_SKL_LP_GPP_D10 0x0203000A
+#define GPIO_SKL_LP_GPP_D11 0x0203000B
+#define GPIO_SKL_LP_GPP_D12 0x0203000C
+#define GPIO_SKL_LP_GPP_D13 0x0203000D
+#define GPIO_SKL_LP_GPP_D14 0x0203000E
+#define GPIO_SKL_LP_GPP_D15 0x0203000F
+#define GPIO_SKL_LP_GPP_D16 0x02030010
+#define GPIO_SKL_LP_GPP_D17 0x02030011
+#define GPIO_SKL_LP_GPP_D18 0x02030012
+#define GPIO_SKL_LP_GPP_D19 0x02030013
+#define GPIO_SKL_LP_GPP_D20 0x02030014
+#define GPIO_SKL_LP_GPP_D21 0x02030015
+#define GPIO_SKL_LP_GPP_D22 0x02030016
+#define GPIO_SKL_LP_GPP_D23 0x02030017
+#define GPIO_SKL_LP_GPP_E0 0x02040000
+#define GPIO_SKL_LP_GPP_E1 0x02040001
+#define GPIO_SKL_LP_GPP_E2 0x02040002
+#define GPIO_SKL_LP_GPP_E3 0x02040003
+#define GPIO_SKL_LP_GPP_E4 0x02040004
+#define GPIO_SKL_LP_GPP_E5 0x02040005
+#define GPIO_SKL_LP_GPP_E6 0x02040006
+#define GPIO_SKL_LP_GPP_E7 0x02040007
+#define GPIO_SKL_LP_GPP_E8 0x02040008
+#define GPIO_SKL_LP_GPP_E9 0x02040009
+#define GPIO_SKL_LP_GPP_E10 0x0204000A
+#define GPIO_SKL_LP_GPP_E11 0x0204000B
+#define GPIO_SKL_LP_GPP_E12 0x0204000C
+#define GPIO_SKL_LP_GPP_E13 0x0204000D
+#define GPIO_SKL_LP_GPP_E14 0x0204000E
+#define GPIO_SKL_LP_GPP_E15 0x0204000F
+#define GPIO_SKL_LP_GPP_E16 0x02040010
+#define GPIO_SKL_LP_GPP_E17 0x02040011
+#define GPIO_SKL_LP_GPP_E18 0x02040012
+#define GPIO_SKL_LP_GPP_E19 0x02040013
+#define GPIO_SKL_LP_GPP_E20 0x02040014
+#define GPIO_SKL_LP_GPP_E21 0x02040015
+#define GPIO_SKL_LP_GPP_E22 0x02040016
+#define GPIO_SKL_LP_GPP_E23 0x02040017
+#define GPIO_SKL_LP_GPP_F0 0x02050000
+#define GPIO_SKL_LP_GPP_F1 0x02050001
+#define GPIO_SKL_LP_GPP_F2 0x02050002
+#define GPIO_SKL_LP_GPP_F3 0x02050003
+#define GPIO_SKL_LP_GPP_F4 0x02050004
+#define GPIO_SKL_LP_GPP_F5 0x02050005
+#define GPIO_SKL_LP_GPP_F6 0x02050006
+#define GPIO_SKL_LP_GPP_F7 0x02050007
+#define GPIO_SKL_LP_GPP_F8 0x02050008
+#define GPIO_SKL_LP_GPP_F9 0x02050009
+#define GPIO_SKL_LP_GPP_F10 0x0205000A
+#define GPIO_SKL_LP_GPP_F11 0x0205000B
+#define GPIO_SKL_LP_GPP_F12 0x0205000C
+#define GPIO_SKL_LP_GPP_F13 0x0205000D
+#define GPIO_SKL_LP_GPP_F14 0x0205000E
+#define GPIO_SKL_LP_GPP_F15 0x0205000F
+#define GPIO_SKL_LP_GPP_F16 0x02050010
+#define GPIO_SKL_LP_GPP_F17 0x02050011
+#define GPIO_SKL_LP_GPP_F18 0x02050012
+#define GPIO_SKL_LP_GPP_F19 0x02050013
+#define GPIO_SKL_LP_GPP_F20 0x02050014
+#define GPIO_SKL_LP_GPP_F21 0x02050015
+#define GPIO_SKL_LP_GPP_F22 0x02050016
+#define GPIO_SKL_LP_GPP_F23 0x02050017
+#define GPIO_SKL_LP_GPP_G0 0x02060000
+#define GPIO_SKL_LP_GPP_G1 0x02060001
+#define GPIO_SKL_LP_GPP_G2 0x02060002
+#define GPIO_SKL_LP_GPP_G3 0x02060003
+#define GPIO_SKL_LP_GPP_G4 0x02060004
+#define GPIO_SKL_LP_GPP_G5 0x02060005
+#define GPIO_SKL_LP_GPP_G6 0x02060006
+#define GPIO_SKL_LP_GPP_G7 0x02060007
+#define GPIO_SKL_LP_GPD0 0x02070000
+#define GPIO_SKL_LP_GPD1 0x02070001
+#define GPIO_SKL_LP_GPD2 0x02070002
+#define GPIO_SKL_LP_GPD3 0x02070003
+#define GPIO_SKL_LP_GPD4 0x02070004
+#define GPIO_SKL_LP_GPD5 0x02070005
+#define GPIO_SKL_LP_GPD6 0x02070006
+#define GPIO_SKL_LP_GPD7 0x02070007
+#define GPIO_SKL_LP_GPD8 0x02070008
+#define GPIO_SKL_LP_GPD9 0x02070009
+#define GPIO_SKL_LP_GPD10 0x0207000A
+#define GPIO_SKL_LP_GPD11 0x0207000B
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+//Sample GPIO Table
+
+static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
+{
+//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
+//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
+ {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+ {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+ {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
+ {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+ {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+ {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
+ {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
+ {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
+ {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
+ {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
+ {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
+ {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
+ {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
+ {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
+ {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
+ {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
+ {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
+ {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
+ {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
+ {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
+ // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
+ // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+ // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+ // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+ // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+ {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
+ {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
+ {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
+ {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
+ {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
+ {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+ {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
+ {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+ {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
+ {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+ {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+ {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+ {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+ {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
+ {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
+ {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+ {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
+ {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
+ {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+ {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
+ {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
+ {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
+ {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
+ {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
+ {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+ {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+ {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+ {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+ {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
+ {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
+ {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
+ {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
+ {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
+ {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
+ {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
+ {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
+ {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
+ {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
+ {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
+ {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
+ {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
+ {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
+ {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
+ {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
+ {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
+ {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
+ {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
+ {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
+ {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
+ {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+ {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+ {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+ {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
+ {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
+ {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
+ {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
+ {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
+ {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
+ {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
+ {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+ {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
+ {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+ {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
+ {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
+ {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+ {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
+ {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
+ {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
+ {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
+ {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+ {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
+ {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
+ {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
+ {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
+ {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+ {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
+ {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
+ {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
+ {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
+ {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
+ {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
+ {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
+ {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+ {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+ {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+ {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+ {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+ {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+ {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+ {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+ {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
+ {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
+ {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
+ {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
+ {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
+ {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
+ {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
+ {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
+ {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
+ {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
+ {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
+ {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+ {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
+ {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
+ {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
+ {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
+ {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
+ {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
+ {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
+ {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
+ {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
+ {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
+ {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+ {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
+ {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
+ {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
+ {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
+ {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+ {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
+ {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
+ {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
+ {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
+ {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
+};
+
+#endif //_GPIO_CONFIG_H_
diff --git a/models/gaze16-3050/FSP/Include/MemInfoHob.h b/models/gaze16-3050/FSP/Include/MemInfoHob.h
new file mode 100644
index 0000000..7ae1793
--- /dev/null
+++ b/models/gaze16-3050/FSP/Include/MemInfoHob.h
@@ -0,0 +1,281 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ @copyright
+ Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_TRACE_CACHE_TYPE 3
+
+#define MAX_NODE 2
+#define MAX_CH 4
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
+ #ifndef INT32_MAX
+ #define INT32_MAX (0x7FFFFFFF)
+ #endif //INT32_MAX
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#ifndef MRC_DDR_TYPE_WIO2
+#define MRC_DDR_TYPE_WIO2 4
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 5
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT64 BaseAddress; ///< Trace Base Address
+ UINT64 TotalSize; ///< Total Trace Region of Same Cache type
+ UINT8 CacheType; ///< Trace Cache Type
+ UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
+ UINT8 Rsvd[2];
+} PSMI_MEM_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ Revision 1:
+ - Initial version.
+ Revision 2:
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT64 PrmrrBase;
+ UINT32 PramSize;
+ UINT64 PramBase;
+ UINT64 DismLimit;
+ UINT64 DismBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+ PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
diff --git a/models/gaze16-3050/FSP/LICENSE b/models/gaze16-3050/FSP/LICENSE
new file mode 100644
index 0000000..9fddc58
--- /dev/null
+++ b/models/gaze16-3050/FSP/LICENSE
@@ -0,0 +1,46 @@
+************************************************************************
+** **
+** **
+** IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING **
+** **
+** ANY PORTION OF THE SOFTWARE **
+** **
+************************************************************************
+
+Copyright (c) 2018 Intel Corporation.
+All rights reserved.
+
+Redistribution.
+
+Redistribution and use in binary form, without modification, are permitted
+provided that the following conditions are met:
+
+- Redistributions must reproduce the above copyright notice and the
+following disclaimer in the documentation and/or other materials provided
+with the distribution.
+
+- Neither the name of Intel Corporation nor the names of its suppliers
+may be used to endorse or promote products derived from this software
+without specific prior written permission.
+
+- No reverse engineering, decompilation, or disassembly of this software
+is permitted.
+
+"Binary form" includes any format that is commonly used for electronic
+conveyance that is a reversible, bit-exact translation of binary
+representation to ASCII or ISO text, for example "uuencode".
+
+DISCLAIMER.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/models/gaze16-3050/IntelGopDriver.efi b/models/gaze16-3050/IntelGopDriver.efi
new file mode 100644
index 0000000..5227c96
--- /dev/null
+++ b/models/gaze16-3050/IntelGopDriver.efi
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d7d82e53d79b2972f8db1019fb0b5ddd18d4e2e4db4ef7243abe064e765c4a38
+size 153984
diff --git a/models/gaze16-3050/IntelGopDriver.inf b/models/gaze16-3050/IntelGopDriver.inf
new file mode 100644
index 0000000..39b2eb9
--- /dev/null
+++ b/models/gaze16-3050/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IntelGopDriver
+ FILE_GUID = 767222f4-a9f4-41ba-9faa-edaa1405a486
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+[Binaries.X64]
+ PE32|IntelGopDriver.efi|*
diff --git a/models/gaze16-3050/README.md b/models/gaze16-3050/README.md
new file mode 100644
index 0000000..1a798b7
--- /dev/null
+++ b/models/gaze16-3050/README.md
@@ -0,0 +1,12 @@
+# System76 Gazelle (gaze16)
+
+## Contents
+
+- [EC](./ec.rom)
+ - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+ - Size: 4 KB
+ - HAP: false
+- [ME](./me.rom)
+ - Size: 5116 KB
+ - Version: 15.0.30.1776
diff --git a/models/gaze16-3050/README.md.in b/models/gaze16-3050/README.md.in
new file mode 100644
index 0000000..42ee48c
--- /dev/null
+++ b/models/gaze16-3050/README.md.in
@@ -0,0 +1 @@
+# System76 Gazelle (gaze16)
diff --git a/models/gaze16-3050/chip.txt b/models/gaze16-3050/chip.txt
new file mode 100644
index 0000000..9b1d0de
--- /dev/null
+++ b/models/gaze16-3050/chip.txt
@@ -0,0 +1 @@
+GD25Q127C/GD25Q128C
diff --git a/models/gaze16-3050/coreboot-collector.txt b/models/gaze16-3050/coreboot-collector.txt
new file mode 100644
index 0000000..c4e90c8
--- /dev/null
+++ b/models/gaze16-3050/coreboot-collector.txt
@@ -0,0 +1,310 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x9A36, Revision 0x05
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0x9A05, Revision 0x05
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x9A60, Revision 0x01
+PCI Device: 0000:00:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x9A11, Revision 0x05
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0x9A0D, Revision 0x01
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0x9A0B, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x43ED, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x43EF, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x43F0, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x43E8, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x43E0, Revision 0x11
+PCI Device: 0000:00:17.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x43BC, Revision 0x11
+PCI Device: 0000:00:1c.6: Class 0x00060400, Vendor 0x8086, Device 0x43BE, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x438B, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x43C8, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x43A3, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x43A4, Revision 0x11
+PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x25A2, Revision 0xA1
+PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x2291, Revision 0xA1
+PCI Device: 0000:02:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
+PCI Device: 0000:03:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 10000:e0:06.0: Class 0x00060400, Vendor 0x8086, Device 0x9A0F, Revision 0x05
+PCI Device: 10000:e0:17.0: Class 0x00010601, Vendor 0x8086, Device 0x43D3, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x15B7, Device 0x5009, Revision 0x01
+## GPIO ##
+500 Series PCH
+GPP_A0 (0x6E,0x10) 0x44000700 0x00003018 0x00000100 0x00000000
+GPP_A1 (0x6E,0x12) 0x44000702 0x00003019 0x00000100 0x00000000
+GPP_A2 (0x6E,0x14) 0x44000600 0x00003020 0x00000100 0x00000000
+GPP_A3 (0x6E,0x16) 0x44000700 0x00003021 0x00000100 0x00000000
+GPP_A4 (0x6E,0x18) 0x44000700 0x00003022 0x00000100 0x00000000
+GPP_A5 (0x6E,0x1A) 0x44000700 0x00001023 0x00000100 0x00000000
+GPP_A6 (0x6E,0x1C) 0x44000700 0x00000024 0x00000100 0x00000000
+GPP_A7 (0x6E,0x1E) 0x44000102 0x00003025 0x00000100 0x00000000
+GPP_A8 (0x6E,0x20) 0x44000102 0x00003026 0x00000100 0x00000000
+GPP_A9 (0x6E,0x22) 0x44000102 0x00003027 0x00000100 0x00000000
+GPP_A10 (0x6E,0x24) 0x44000102 0x00003028 0x00000100 0x00000000
+GPP_A11 (0x6E,0x26) 0x44000102 0x00003029 0x00000100 0x00000000
+GPP_A12 (0x6E,0x28) 0x44000102 0x0000302a 0x00000100 0x00000000
+GPP_A13 (0x6E,0x2A) 0x44000102 0x0000302b 0x00000100 0x00000000
+GPP_A14 (0x6E,0x2C) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000500 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000500 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000500 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000500 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000102 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000102 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000100 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000102 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000102 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000102 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x40100102 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000102 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000102 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000102 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000102 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000102 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000102 0x00000044 0x00000000 0x00000000
+GPP_B0 (0x6E,0x5A) 0x40100102 0x00003045 0x00000000 0x00000000
+GPP_B1 (0x6E,0x5C) 0x44000102 0x00000046 0x00000000 0x00000000
+GPP_B2 (0x6E,0x5E) 0x44000102 0x00000047 0x00000000 0x00000000
+GPP_B3 (0x6E,0x60) 0x44000201 0x00000048 0x00000000 0x00000000
+GPP_B4 (0x6E,0x62) 0x44000102 0x00000049 0x00000000 0x00000000
+GPP_B5 (0x6E,0x64) 0x44000702 0x0000004a 0x00000000 0x00000000
+GPP_B6 (0x6E,0x66) 0x44000102 0x0000004b 0x00000000 0x00000000
+GPP_B7 (0x6E,0x68) 0x44000102 0x0000004c 0x00000000 0x00000000
+GPP_B8 (0x6E,0x6A) 0x44000102 0x0000004d 0x00000000 0x00000000
+GPP_B9 (0x6E,0x6C) 0x44000700 0x0000004e 0x00000000 0x00000000
+GPP_B10 (0x6E,0x6E) 0x44000700 0x0000004f 0x00000000 0x00000000
+GPP_B11 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
+GPP_B12 (0x6E,0x72) 0x44000700 0x00000051 0x00000000 0x00000000
+GPP_B13 (0x6E,0x74) 0x44000700 0x00000052 0x00000000 0x00000000
+GPP_B14 (0x6E,0x76) 0x44000500 0x00000053 0x00000000 0x00000000
+GPP_B15 (0x6E,0x78) 0x44000201 0x00000054 0x00000000 0x00000000
+GPP_B16 (0x6E,0x7A) 0x44000102 0x00000055 0x00000000 0x00000000
+GPP_B17 (0x6E,0x7C) 0x44000102 0x00000056 0x00000000 0x00000000
+GPP_B18 (0x6E,0x7E) 0x44000102 0x00000057 0x00000000 0x00000000
+GPP_B19 (0x6E,0x80) 0x44000102 0x00000058 0x00000000 0x00000000
+GPP_B20 (0x6E,0x82) 0x44000102 0x00000059 0x00000000 0x00000000
+GPP_B21 (0x6E,0x84) 0x44000102 0x0000005a 0x00000000 0x00000000
+GPP_B22 (0x6E,0x86) 0x44000102 0x0000005b 0x00000000 0x00000000
+GPP_B23 (0x6E,0x88) 0x44000102 0x0000005c 0x00000000 0x00000000
+GPP_D0 (0x6D,0x00) 0x44000100 0x0000005d 0x00000000 0x00000000
+GPP_D1 (0x6D,0x02) 0x44000100 0x0000005e 0x00000000 0x00000000
+GPP_D2 (0x6D,0x04) 0x44000100 0x0000005f 0x00000000 0x00000000
+GPP_D3 (0x6D,0x06) 0x44000100 0x00000060 0x00000000 0x00000000
+GPP_D4 (0x6D,0x08) 0x44000502 0x00000061 0x00000000 0x00000000
+GPP_D5 (0x6D,0x0A) 0x44000900 0x00000062 0x00000000 0x00000000
+GPP_D6 (0x6D,0x0C) 0x44000d00 0x00000063 0x00000000 0x00000000
+GPP_D7 (0x6D,0x0E) 0x44000100 0x00000064 0x00000000 0x00000000
+GPP_D8 (0x6D,0x10) 0x44000100 0x00000065 0x00000000 0x00000000
+GPP_D9 (0x6D,0x12) 0x44000502 0x00000066 0x00000000 0x00000000
+GPP_D10 (0x6D,0x14) 0x44000502 0x00000067 0x00000000 0x00000000
+GPP_D11 (0x6D,0x16) 0x44000100 0x00003c68 0x00000000 0x00000000
+GPP_D12 (0x6D,0x18) 0x44000100 0x00000069 0x00000000 0x00000000
+GPP_D13 (0x6D,0x1A) 0x44000100 0x0000006a 0x00000000 0x00000000
+GPP_D14 (0x6D,0x1C) 0x44000100 0x0000006b 0x00000000 0x00000000
+GPP_D15 (0x6D,0x1E) 0x44000502 0x0000006c 0x00000000 0x00000000
+GPP_D16 (0x6D,0x20) 0x44000100 0x0000006d 0x00000000 0x00000000
+GPP_D17 (0x6D,0x22) 0x44000100 0x0000006e 0x00000000 0x00000000
+GPP_D18 (0x6D,0x24) 0x44000100 0x0000006f 0x00000000 0x00000000
+GPP_D19 (0x6D,0x26) 0x44000100 0x00000070 0x00000000 0x00000000
+GPP_D20 (0x6D,0x28) 0x44000100 0x00000071 0x00000000 0x00000000
+GPP_D21 (0x6D,0x2A) 0x44000100 0x00000072 0x00000000 0x00000000
+GPP_D22 (0x6D,0x2C) 0x44000100 0x00000073 0x00000000 0x00000000
+GPP_D23 (0x6D,0x2E) 0x44000100 0x00000074 0x00000000 0x00000000
+GPP_C0 (0x6D,0x34) 0x44000502 0x00000075 0x00000000 0x00000000
+GPP_C1 (0x6D,0x36) 0x44000502 0x00000076 0x00000000 0x00000000
+GPP_C2 (0x6D,0x38) 0x44000102 0x00000077 0x00000800 0x00000000
+GPP_C3 (0x6D,0x3A) 0x44000102 0x00000018 0x00000000 0x00000000
+GPP_C4 (0x6D,0x3C) 0x44000102 0x00000019 0x00000000 0x00000000
+GPP_C5 (0x6D,0x3E) 0x44000100 0x00000020 0x00000000 0x00000000
+GPP_C6 (0x6D,0x40) 0x44000102 0x00000021 0x00000000 0x00000000
+GPP_C7 (0x6D,0x42) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_C8 (0x6D,0x44) 0x44000102 0x00000023 0x00000000 0x00000000
+GPP_C9 (0x6D,0x46) 0x44000102 0x00000024 0x00000000 0x00000000
+GPP_C10 (0x6D,0x48) 0x44000102 0x00000025 0x00000000 0x00000000
+GPP_C11 (0x6D,0x4A) 0x44000100 0x00000026 0x00000000 0x00000000
+GPP_C12 (0x6D,0x4C) 0x44000102 0x00000027 0x00000000 0x00000000
+GPP_C13 (0x6D,0x4E) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_C14 (0x6D,0x50) 0x44000102 0x00000029 0x00000000 0x00000000
+GPP_C15 (0x6D,0x52) 0x44000102 0x0000002a 0x00000000 0x00000000
+GPP_C16 (0x6D,0x54) 0x44000502 0x0000002b 0x00000000 0x00000000
+GPP_C17 (0x6D,0x56) 0x44000502 0x00000030 0x00000000 0x00000000
+GPP_C18 (0x6D,0x58) 0x44000102 0x00000031 0x00000000 0x00000000
+GPP_C19 (0x6D,0x5A) 0x44000102 0x00000032 0x00000000 0x00000000
+GPP_C20 (0x6D,0x5C) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_C21 (0x6D,0x5E) 0x44000102 0x00000034 0x00000000 0x00000000
+GPP_C22 (0x6D,0x60) 0x44000201 0x00000035 0x00000000 0x00000000
+GPP_C23 (0x6D,0x62) 0x44000102 0x00000036 0x00000000 0x00000000
+GPP_S0 (0x6D,0x64) 0x44000100 0x01800037 0x00000000 0x00000000
+GPP_S1 (0x6D,0x66) 0x44000100 0x01800038 0x00000000 0x00000000
+GPP_S2 (0x6D,0x68) 0x44000100 0x01800039 0x00000000 0x00000000
+GPP_S3 (0x6D,0x6A) 0x44000100 0x0180003a 0x00000000 0x00000000
+GPP_S4 (0x6D,0x6C) 0x44000100 0x0180003b 0x00000000 0x00000000
+GPP_S5 (0x6D,0x6E) 0x44000100 0x0180003c 0x00000000 0x00000000
+GPP_S6 (0x6D,0x70) 0x44000100 0x0180003d 0x00000000 0x00000000
+GPP_S7 (0x6D,0x72) 0x44000100 0x0180003e 0x00000000 0x00000000
+GPP_G0 (0x6D,0x74) 0x44000102 0x0000003f 0x00000000 0x00000000
+GPP_G1 (0x6D,0x76) 0x44000102 0x00000040 0x00000000 0x00000000
+GPP_G2 (0x6D,0x78) 0x44000100 0x00001041 0x00000000 0x00000000
+GPP_G3 (0x6D,0x7A) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_G4 (0x6D,0x7C) 0x44000102 0x00000043 0x00000000 0x00000000
+GPP_G5 (0x6D,0x7E) 0x44000102 0x00000044 0x00000000 0x00000000
+GPP_G6 (0x6D,0x80) 0x44000102 0x00000045 0x00000000 0x00000000
+GPP_G7 (0x6D,0x82) 0x44000102 0x00000046 0x00000000 0x00000000
+GPP_G8 (0x6D,0x84) 0x44000102 0x00003c47 0x00000100 0x00000000
+GPP_G9 (0x6D,0x86) 0x44000102 0x00000048 0x00000100 0x00000000
+GPP_G10 (0x6D,0x88) 0x44000102 0x00003c49 0x00000100 0x00000000
+GPP_G11 (0x6D,0x8A) 0x44000102 0x0000004a 0x00000100 0x00000000
+GPP_G12 (0x6D,0x8C) 0x44001300 0x00003c4b 0x00000100 0x00000000
+GPP_G13 (0x6D,0x8E) 0x44001300 0x00003c4c 0x00000100 0x00000000
+GPP_G14 (0x6D,0x90) 0x44000102 0x00003c4d 0x00000100 0x00000000
+GPP_G15 (0x6D,0x92) 0x44000102 0x0000004e 0x00000100 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003050 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000702 0x00003c51 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000102 0x00003c52 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003053 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000054 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000055 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000056 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000100 0x00000057 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000058 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000200 0x00000059 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000005a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000102 0x0000005b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x04000300 0x0000005c 0x00000000 0x00000000
+GPP_E0 (0x6B,0x00) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_E1 (0x6B,0x02) 0x44000700 0x0000305e 0x00000000 0x00000000
+GPP_E2 (0x6B,0x04) 0x44000102 0x0000005f 0x00000000 0x00000000
+GPP_E3 (0x6B,0x06) 0x44000102 0x00000060 0x00000000 0x00000000
+GPP_E4 (0x6B,0x08) 0x44000102 0x00000061 0x00000000 0x00000000
+GPP_E5 (0x6B,0x0A) 0x04000500 0x00000062 0x00000000 0x00000000
+GPP_E6 (0x6B,0x0C) 0x44000102 0x00000063 0x00000000 0x00000000
+GPP_E7 (0x6B,0x0E) 0x44000102 0x00000064 0x00000000 0x00000000
+GPP_E8 (0x6B,0x10) 0x44000500 0x00000065 0x00000000 0x00000000
+GPP_E9 (0x6B,0x12) 0x44000102 0x00000066 0x00000800 0x00000000
+GPP_E10 (0x6B,0x14) 0x44000102 0x00000067 0x00000800 0x00000000
+GPP_E11 (0x6B,0x16) 0x44000102 0x00000068 0x00000800 0x00000000
+GPP_E12 (0x6B,0x18) 0x44000102 0x00000069 0x00000000 0x00000000
+GPP_F0 (0x6B,0x1A) 0x44000902 0x0000006a 0x00000000 0x00000000
+GPP_F1 (0x6B,0x1C) 0x44000102 0x0000006b 0x00000000 0x00000000
+GPP_F2 (0x6B,0x1E) 0x84000201 0x0000006c 0x00000000 0x00000000
+GPP_F3 (0x6B,0x20) 0x44000201 0x0000006d 0x00000000 0x00000000
+GPP_F4 (0x6B,0x22) 0x44000201 0x0000006e 0x00000000 0x00000000
+GPP_F5 (0x6B,0x24) 0x44000201 0x0000006f 0x00000000 0x00000000
+GPP_F6 (0x6B,0x26) 0x44000102 0x00000070 0x00000000 0x00000000
+GPP_F7 (0x6B,0x28) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_F8 (0x6B,0x2A) 0x44000201 0x00000072 0x00000000 0x00000000
+GPP_F9 (0x6B,0x2C) 0x44000201 0x00000073 0x00000000 0x00000000
+GPP_F10 (0x6B,0x2E) 0x44000102 0x00000074 0x00000000 0x00000000
+GPP_F11 (0x6B,0x30) 0x44000102 0x00000075 0x00000000 0x00000000
+GPP_F12 (0x6B,0x32) 0x44000201 0x00000076 0x00000000 0x00000000
+GPP_F13 (0x6B,0x34) 0x44000102 0x00000077 0x00000000 0x00000000
+GPP_F14 (0x6B,0x36) 0x44000100 0x00000018 0x00000000 0x00000000
+GPP_F15 (0x6B,0x38) 0x44000100 0x00000019 0x00000000 0x00000000
+GPP_F16 (0x6B,0x3A) 0x44000102 0x00000020 0x00000000 0x00000000
+GPP_F17 (0x6B,0x3C) 0x44000201 0x00000021 0x00000000 0x00000000
+GPP_F18 (0x6B,0x3E) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_F19 (0x6B,0x40) 0x44000700 0x00000023 0x00000000 0x00000000
+GPP_F20 (0x6B,0x42) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_F21 (0x6B,0x44) 0x44000700 0x00000025 0x00000000 0x00000000
+GPP_F22 (0x6B,0x46) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_F23 (0x6B,0x48) 0x44000102 0x00000027 0x00000000 0x00000000
+GPP_H0 (0x6A,0x00) 0x44000102 0x00000024 0x00000000 0x00000000
+GPP_H1 (0x6A,0x02) 0x44000702 0x00000025 0x00000000 0x00000000
+GPP_H2 (0x6A,0x04) 0x44000702 0x00000026 0x00000000 0x00000000
+GPP_H3 (0x6A,0x06) 0x44000702 0x00000027 0x00000000 0x00000000
+GPP_H4 (0x6A,0x08) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_H5 (0x6A,0x0A) 0x44000102 0x00000029 0x00000000 0x00000000
+GPP_H6 (0x6A,0x0C) 0x44000102 0x0000002a 0x00000000 0x00000000
+GPP_H7 (0x6A,0x0E) 0x44000102 0x0000002b 0x00000000 0x00000000
+GPP_H8 (0x6A,0x10) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_H9 (0x6A,0x12) 0x44000102 0x00000031 0x00000000 0x00000000
+GPP_H10 (0x6A,0x14) 0x44000102 0x00000032 0x00000000 0x00000000
+GPP_H11 (0x6A,0x16) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_H12 (0x6A,0x18) 0x44000102 0x00000034 0x00000000 0x00000000
+GPP_H13 (0x6A,0x1A) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_H14 (0x6A,0x1C) 0x44000102 0x00000036 0x00000000 0x00000000
+GPP_H15 (0x6A,0x1E) 0x84000102 0x00000037 0x00000800 0x00000000
+GPP_H16 (0x6A,0x20) 0x44000102 0x00000038 0x00000000 0x00000000
+GPP_H17 (0x6A,0x22) 0x44000201 0x00000039 0x00000000 0x00000000
+GPP_H18 (0x6A,0x24) 0x44000100 0x0000003a 0x00000000 0x00000000
+GPP_H19 (0x6A,0x26) 0x44000102 0x0000003b 0x00000000 0x00000000
+GPP_H20 (0x6A,0x28) 0x44000102 0x0000003c 0x00000000 0x00000000
+GPP_H21 (0x6A,0x2A) 0x44000102 0x0000003d 0x00000000 0x00000000
+GPP_H22 (0x6A,0x2C) 0x44000102 0x0000003e 0x00000000 0x00000000
+GPP_H23 (0x6A,0x2E) 0x44000201 0x0000003f 0x00000000 0x00000000
+GPP_J0 (0x6A,0x30) 0x44000500 0x04000040 0x00000000 0x00000000
+GPP_J1 (0x6A,0x32) 0x44000700 0x04000041 0x00000000 0x00000000
+GPP_J2 (0x6A,0x34) 0x44000500 0x04000042 0x00000000 0x00000000
+GPP_J3 (0x6A,0x36) 0x44000502 0x04003043 0x00000000 0x00000000
+GPP_J4 (0x6A,0x38) 0x44000500 0x04000044 0x00000000 0x00000000
+GPP_J5 (0x6A,0x3A) 0x44000502 0x04003045 0x00000000 0x00000000
+GPP_J6 (0x6A,0x3C) 0x44000500 0x04000046 0x00000000 0x00000000
+GPP_J7 (0x6A,0x3E) 0x44000500 0x04000047 0x00000000 0x00000000
+GPP_J8 (0x6A,0x40) 0x84000102 0x04000048 0x00000000 0x00000000
+GPP_J9 (0x6A,0x42) 0x44000100 0x04000049 0x00000000 0x00000000
+GPP_K0 (0x6A,0x44) 0x44000200 0x0000004a 0x00000000 0x00000000
+GPP_K1 (0x6A,0x46) 0x44000102 0x0000004b 0x00000000 0x00000000
+GPP_K2 (0x6A,0x48) 0x44000102 0x0000004c 0x00000000 0x00000000
+GPP_K3 (0x6A,0x4A) 0x44000102 0x0000004d 0x00000000 0x00000000
+GPP_K4 (0x6A,0x4C) 0x44000102 0x0000004e 0x00000000 0x00000000
+GPP_K5 (0x6A,0x4E) 0x44000102 0x0000004f 0x00000000 0x00000000
+GPP_K6 (0x6A,0x50) 0x44000702 0x00000050 0x00000000 0x00000000
+GPP_K7 (0x6A,0x52) 0x44000500 0x00000051 0x00000000 0x00000000
+GPP_K8 (0x6A,0x54) 0x44000700 0x00000052 0x00000000 0x00000000
+GPP_K9 (0x6A,0x56) 0x44000700 0x00000053 0x00000000 0x00000000
+GPP_K10 (0x6A,0x58) 0x46880100 0x00000054 0x00000000 0x00000000
+GPP_K11 (0x6A,0x5A) 0x44000100 0x00001055 0x00000000 0x00000000
+GPP_I0 (0x69,0x00) 0x04000702 0x00000056 0x00000000 0x00000000
+GPP_I1 (0x69,0x02) 0x44000102 0x00000057 0x00000000 0x00000000
+GPP_I2 (0x69,0x04) 0x44000102 0x00000058 0x00000000 0x00000000
+GPP_I3 (0x69,0x06) 0x44000102 0x00000059 0x00000000 0x00000000
+GPP_I4 (0x69,0x08) 0x44000102 0x0000005a 0x00000000 0x00000000
+GPP_I5 (0x69,0x0A) 0x44000500 0x0000005b 0x00000000 0x00000000
+GPP_I6 (0x69,0x0C) 0x44000502 0x0000005c 0x00000000 0x00000000
+GPP_I7 (0x69,0x0E) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_I8 (0x69,0x10) 0x44000102 0x0000005e 0x00000000 0x00000000
+GPP_I9 (0x69,0x12) 0x44000201 0x0000005f 0x00000000 0x00000000
+GPP_I10 (0x69,0x14) 0x44000100 0x00001060 0x00000000 0x00000000
+GPP_I11 (0x69,0x16) 0x84000102 0x00000061 0x00000000 0x00000000
+GPP_I12 (0x69,0x18) 0x84000102 0x00000062 0x00000000 0x00000000
+GPP_I13 (0x69,0x1A) 0x84000102 0x00000063 0x00000000 0x00000000
+GPP_I14 (0x69,0x1C) 0x84000102 0x00000064 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+ vendor_name: Realtek
+ chip_name: ALC256
+ vendor_id: 0x10ec0256
+ subsystem_id: 0x15585017
+ revision_id: 0x100002
+ 0x12: 0x90a60130
+ 0x13: 0x40000000
+ 0x14: 0x90170110
+ 0x18: 0x411111f0
+ 0x19: 0x411111f0
+ 0x1a: 0x411111f0
+ 0x1b: 0x02a11040
+ 0x1d: 0x41700001
+ 0x1e: 0x411111f0
+ 0x21: 0x02211020
+hdaudioC0D2
+ vendor_name: Intel
+ chip_name: Tigerlake HDMI
+ vendor_id: 0x80862812
+ subsystem_id: 0x80860101
+ revision_id: 0x100000
+ 0x04: 0x18560010
+ 0x06: 0x18560010
+ 0x08: 0x18560010
+ 0x0a: 0x18560010
+ 0x0b: 0x18560010
+ 0x0c: 0x18560010
+ 0x0d: 0x18560010
+ 0x0e: 0x18560010
+ 0x0f: 0x18560010
+hdaudioC1D0
+ vendor_name: Nvidia
+ chip_name: GPU a0 HDMI/DP
+ vendor_id: 0x10de00a0
+ subsystem_id: 0x10de0000
+ revision_id: 0x100100
+ 0x04: 0x185600f0
diff --git a/models/gaze16-3050/coreboot.config b/models/gaze16-3050/coreboot.config
new file mode 100644
index 0000000..5332226
--- /dev/null
+++ b/models/gaze16-3050/coreboot.config
@@ -0,0 +1,24 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_GAZE16_3050=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_FSP_M_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_M.fd"
+CONFIG_FSP_S_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_S.fd"
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_POST_IO=n
+CONFIG_RUN_FSP_GOP=y
+CONFIG_SMMSTORE=y
+CONFIG_SUBSYSTEM_DEVICE_ID=0x5015
+CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
diff --git a/models/gaze16-3050/ec.config b/models/gaze16-3050/ec.config
new file mode 100644
index 0000000..be8546f
--- /dev/null
+++ b/models/gaze16-3050/ec.config
@@ -0,0 +1 @@
+BOARD=system76/gaze16-3050
diff --git a/models/gaze16-3050/ecspy.txt b/models/gaze16-3050/ecspy.txt
new file mode 100644
index 0000000..f9956f1
--- /dev/null
+++ b/models/gaze16-3050/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 2
+A0: data 0 mirror 0 pot 0 control 00
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 0 mirror 1 pot 0 control 00
+A3: data 1 mirror 1 pot 0 control 44
+A4: data 1 mirror 1 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 0 mirror 0 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 84
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 80
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 44
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 1 mirror 1 pot 0 control 40
+D4: data 1 mirror 1 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 1 mirror 1 pot 0 control 02
+D7: data 1 mirror 1 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 0 mirror 0 pot 0 control 84
+E3: data 0 mirror 0 pot 0 control 44
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 1 mirror 1 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 40
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 0 mirror 0 pot 0 control 00
+F7: data 0 mirror 0 pot 0 control 44
+G0: data 1 mirror 1 pot 0 control 84
+G1: data 1 mirror 1 pot 0 control 44
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 1 mirror 1 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 1 mirror 1 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 1 mirror 1 pot 0 control 80
+H4: data 1 mirror 1 pot 0 control 80
+H5: data 0 mirror 0 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 80
+H7: data 1 mirror 1 pot 0 control 44
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 40
+I3: data 0 mirror 0 pot 0 control 80
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 0 mirror 0 pot 0 control 00
+I6: data 0 mirror 0 pot 0 control 00
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 0 mirror 0 pot 0 control 40
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 1 mirror 1 pot 0 control 40
+M0: data 1 mirror 1 control 06
+M1: data 1 mirror 1 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 0 control 06
+M5: data 1 mirror 1 control 00
+M6: data 1 mirror 1 control 86
+M7: data 0 mirror 0 control 00
diff --git a/models/gaze16-3050/edk2.config b/models/gaze16-3050/edk2.config
new file mode 100644
index 0000000..eb4f1b9
--- /dev/null
+++ b/models/gaze16-3050/edk2.config
@@ -0,0 +1,2 @@
+PCIE_BASE=0xC0000000
+#SYSTEM76_EC_LOGGING=TRUE
diff --git a/models/gaze16-3050/fd.rom b/models/gaze16-3050/fd.rom
new file mode 100644
index 0000000..1460a8b
--- /dev/null
+++ b/models/gaze16-3050/fd.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c866e8f0767916ad9a1e318d043828d1080caf79004352a692e95ff2e1bb5342
+size 4096
diff --git a/models/gaze16-3050/gpio.h b/models/gaze16-3050/gpio.h
new file mode 100644
index 0000000..da76219
--- /dev/null
+++ b/models/gaze16-3050/gpio.h
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include
+#include
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+ PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPD7, NONE, PWROK),
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+ PAD_CFG_GPO(GPD9, 0, PWROK),
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPD11, NONE, PWROK),
+ _PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A14, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
+ PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+ PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+ PAD_CFG_GPO(GPP_B15, 1, DEEP),
+ PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+ PAD_CFG_GPO(GPP_C22, 1, DEEP),
+ PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+ PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F2, 1, PLTRST),
+ PAD_CFG_GPO(GPP_F3, 1, DEEP),
+ PAD_CFG_GPO(GPP_F4, 1, DEEP),
+ PAD_CFG_GPO(GPP_F5, 1, DEEP),
+ PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F8, 1, DEEP),
+ PAD_CFG_GPO(GPP_F9, 1, DEEP),
+ PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
+ PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ PAD_NC(GPP_F22, NONE),
+ PAD_CFG_GPI(GPP_F23, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+ PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G11, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_G12, 0x44001300, 0x3c00),
+ _PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00),
+ PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H0, NONE, DEEP),
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_H4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+ PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+ PAD_CFG_GPO(GPP_H23, 1, DEEP),
+ PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPP_I1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I4, NONE, DEEP),
+ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I8, NONE, DEEP),
+ PAD_CFG_GPO(GPP_I9, 1, DEEP),
+ PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
+ PAD_CFG_GPI(GPP_I11, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_I12, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
+ PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_J9, NONE, DEEP),
+ PAD_CFG_GPO(GPP_K0, 0, DEEP),
+ PAD_CFG_GPI(GPP_K1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+ PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+ _PAD_CFG_STRUCT(GPP_K10, 0x46880100, 0x0000),
+ PAD_CFG_GPI(GPP_K11, DN_20K, DEEP),
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_R5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R11, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
+ PAD_CFG_GPI(GPP_R13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S7, NONE, DEEP),
+};
+
+#endif
+
+#endif
diff --git a/models/gaze16-3050/hda_verb.c b/models/gaze16-3050/hda_verb.c
new file mode 100644
index 0000000..df4cd15
--- /dev/null
+++ b/models/gaze16-3050/hda_verb.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC256 */
+ 0x10ec0256, /* Vendor ID */
+ 0x15585017, /* Subsystem ID */
+ 11, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x15585017),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+ /* Intel, TigerlakeHDMI */
+ 0x80862812, /* Vendor ID */
+ 0x80860101, /* Subsystem ID */
+ 10, /* Number of entries */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+ /* Nvidia, GPUa0HDMI/DP */
+ 0x10de00a0, /* Vendor ID */
+ 0x10de0000, /* Subsystem ID */
+ 2, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x10de0000),
+ AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/models/gaze16-3050/me.rom b/models/gaze16-3050/me.rom
new file mode 100644
index 0000000..8df695b
--- /dev/null
+++ b/models/gaze16-3050/me.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c4cb1fccd8c5f23d5671be2d5a19880eeb7b29c797e7697d52877b13503f62a1
+size 5238784
diff --git a/models/gaze16-3050/microcode.rom b/models/gaze16-3050/microcode.rom
new file mode 100644
index 0000000..46c7b75
--- /dev/null
+++ b/models/gaze16-3050/microcode.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:e2b82f224a767a8a9a0336dac3539808b1d03a2d388a858d8ce4beb94e81a1f3
+size 100352
diff --git a/models/gaze16-3050/vbt.rom b/models/gaze16-3050/vbt.rom
new file mode 100644
index 0000000..1b4aec8
--- /dev/null
+++ b/models/gaze16-3050/vbt.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:af15dc53068c9c97ae67ea6f6a5a1b7c68be004a0ce971b758f98685955a9138
+size 8704
diff --git a/models/gaze16-3060/FSP/Fsp_M.fd b/models/gaze16-3060/FSP/Fsp_M.fd
new file mode 100644
index 0000000..c149193
--- /dev/null
+++ b/models/gaze16-3060/FSP/Fsp_M.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c23a3ca630e362b25ec84024423756eb1d48be3c00d08b9f718eeb9533a809f4
+size 651264
diff --git a/models/gaze16-3060/FSP/Fsp_S.fd b/models/gaze16-3060/FSP/Fsp_S.fd
new file mode 100644
index 0000000..6233dc9
--- /dev/null
+++ b/models/gaze16-3060/FSP/Fsp_S.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:53c9c9d8dc4db35612fc60e74f5461f55aa157e0943c53a0120f0764bd8396a4
+size 368640
diff --git a/models/gaze16-3060/FSP/Fsp_T.fd b/models/gaze16-3060/FSP/Fsp_T.fd
new file mode 100644
index 0000000..c8c54aa
--- /dev/null
+++ b/models/gaze16-3060/FSP/Fsp_T.fd
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2c17e3dfb42354917778fb079c1d72aaca09086ebc94fcbe2904449195ceaa5b
+size 28672
diff --git a/models/gaze16-3060/FSP/Include/FirmwareVersionInfoHob.h b/models/gaze16-3060/FSP/Include/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..2b54a85
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FirmwareVersionInfoHob.h
@@ -0,0 +1,62 @@
+/** @file
+ Header file for Firmware Version Information
+
+ @copyright
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include
+#include
+#include
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/models/gaze16-3060/FSP/Include/FspInfoHob.h b/models/gaze16-3060/FSP/Include/FspInfoHob.h
new file mode 100644
index 0000000..2db8e6f
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FspInfoHob.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP Information HOB.
+
+@copyright
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _FSP_INFO_HOB_H_
+#define _FSP_INFO_HOB_H_
+
+extern EFI_GUID gFspInfoGuid;
+
+#pragma pack (push, 1)
+
+typedef struct {
+UINT8 SiliconInitVersionMajor;
+UINT8 SiliconInitVersionMinor;
+UINT8 SiliconInitVersionRevision;
+UINT8 SiliconInitVersionBuild;
+UINT8 FspVersionRevision;
+UINT8 FspVersionBuild;
+UINT8 TimeStamp [12];
+UINT8 FspVersionMinor;
+} FSP_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _FSP_INFO_HOB_H_
diff --git a/models/gaze16-3060/FSP/Include/FspUpd.h b/models/gaze16-3060/FSP/Include/FspUpd.h
new file mode 100644
index 0000000..6e329ba
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FspUpd.h
@@ -0,0 +1,27 @@
+/** @file FspUpd.h
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4754 /* 'TGLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4754 /* 'TGLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4754 /* 'TGLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3060/FSP/Include/FspmUpd.h b/models/gaze16-3060/FSP/Include/FspmUpd.h
new file mode 100644
index 0000000..7951f99
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FspmUpd.h
@@ -0,0 +1,3615 @@
+/** @file FspmUpd.h
+
+ @copyright
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+#include
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0048 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x004A - Enable above 4GB MMIO resource support
+ Enable/disable above 4GB MMIO resource support
+ $EN_DIS
+**/
+ UINT8 EnableAbove4GBMmio;
+
+/** Offset 0x004B - Enable/Disable CrashLog Device 10
+ Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogDevice;
+
+/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr00]
+**/
+ UINT32 MemorySpdPtr000;
+
+/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr01]
+**/
+ UINT32 MemorySpdPtr001;
+
+/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr02]
+**/
+ UINT32 MemorySpdPtr010;
+
+/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr03]
+**/
+ UINT32 MemorySpdPtr011;
+
+/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr04]
+**/
+ UINT32 MemorySpdPtr020;
+
+/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr05]
+**/
+ UINT32 MemorySpdPtr021;
+
+/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr06]
+**/
+ UINT32 MemorySpdPtr030;
+
+/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr07]
+**/
+ UINT32 MemorySpdPtr031;
+
+/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr08]
+**/
+ UINT32 MemorySpdPtr100;
+
+/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr09]
+**/
+ UINT32 MemorySpdPtr101;
+
+/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr10]
+**/
+ UINT32 MemorySpdPtr110;
+
+/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr11]
+**/
+ UINT32 MemorySpdPtr111;
+
+/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr12]
+**/
+ UINT32 MemorySpdPtr120;
+
+/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr13]
+**/
+ UINT32 MemorySpdPtr121;
+
+/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr14]
+**/
+ UINT32 MemorySpdPtr130;
+
+/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked
+ as 00 [ALIAS_NAME MemorySpdPtr15]
+**/
+ UINT32 MemorySpdPtr131;
+
+/** Offset 0x008C - RcompResistor settings
+ Indicates RcompResistor settings: Board-dependent
+**/
+ UINT16 RcompResistor;
+
+/** Offset 0x008E - RcompTarget settings
+ RcompTarget settings: board-dependent
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh0]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch0[2];
+
+/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh1]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch1[2];
+
+/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh2]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch2[2];
+
+/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh3]
+**/
+ UINT8 DqsMapCpu2DramMc0Ch3[2];
+
+/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh4]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch0[2];
+
+/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh5]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch1[2];
+
+/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh6]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch2[2];
+
+/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqsMapCpu2DramCh7]
+**/
+ UINT8 DqsMapCpu2DramMc1Ch3[2];
+
+/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh0]
+**/
+ UINT8 DqMapCpu2DramMc0Ch0[16];
+
+/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh1]
+**/
+ UINT8 DqMapCpu2DramMc0Ch1[16];
+
+/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh2]
+**/
+ UINT8 DqMapCpu2DramMc0Ch2[16];
+
+/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh3]
+**/
+ UINT8 DqMapCpu2DramMc0Ch3[16];
+
+/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh4]
+**/
+ UINT8 DqMapCpu2DramMc1Ch0[16];
+
+/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh5]
+**/
+ UINT8 DqMapCpu2DramMc1Ch1[16];
+
+/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh6]
+**/
+ UINT8 DqMapCpu2DramMc1Ch2[16];
+
+/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent [ALIAS_NAME
+ DqMapCpu2DramCh7]
+**/
+ UINT8 DqMapCpu2DramMc1Ch3[16];
+
+/** Offset 0x0128 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x0129 - Smram Mask
+ The SMM Regions AB-SEG and/or H-SEG reserved
+ 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+ UINT8 SmramMask;
+
+/** Offset 0x012A - MRC Fast Boot
+ Enables/Disable the MRC fast path thru the MRC
+ $EN_DIS
+**/
+ UINT8 MrcFastBoot;
+
+/** Offset 0x012B - Rank Margin Tool per Task
+ This option enables the user to execute Rank Margin Tool per major training step
+ in the MRC.
+ $EN_DIS
+**/
+ UINT8 RmtPerTask;
+
+/** Offset 0x012C - Training Trace
+ This option enables the trained state tracing feature in MRC. This feature will
+ print out the key training parameters state across major training steps.
+ $EN_DIS
+**/
+ UINT8 TrainTrace;
+
+/** Offset 0x012D
+**/
+ UINT8 UnusedUpdSpace0[3];
+
+/** Offset 0x0130 - Intel Enhanced Debug
+ @deprecated - Not used and has no effect
+ 0 : Disable, 0x400000 : Enable
+**/
+ UINT32 IedSize;
+
+/** Offset 0x0134 - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x0138 - MMIO Size
+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+ UINT16 MmioSize;
+
+/** Offset 0x013A - Probeless Trace
+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+ This also requires IED to be enabled.
+ $EN_DIS
+**/
+ UINT8 ProbelessTrace;
+
+/** Offset 0x013B - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x013C - Spd Address Tabl
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[16];
+
+/** Offset 0x014C - Platform Debug Consent
+ To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
+ Enabling this BIOS option may alter the default value of other debug-related BIOS
+ options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
+ policies, but the user must set each debug option manually, aimed at advanced users.\n
+ Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
+**/
+ UINT8 PlatformDebugConsent;
+
+/** Offset 0x014D - DCI Enable
+ Determine if to enable DCI debug from host
+ $EN_DIS
+**/
+ UINT8 DciEn;
+
+/** Offset 0x014E - DCI DbC Mode
+ Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
+ Set both USB2/3DBCEN; No Change: Comply with HW value
+ 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
+**/
+ UINT8 DciDbcMode;
+
+/** Offset 0x014F - Enable DCI ModPHY Power Gate
+ Enable ModPHY Power Gate when DCI is enabled
+ $EN_DIS
+**/
+ UINT8 DciModphyPg;
+
+/** Offset 0x0150 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
+ This BIOS option enables kernel and platform debug for USB3 interface over a UFP
+ Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DciUsb3TypecUfpDbg;
+
+/** Offset 0x0151 - PCH Trace Hub Mode
+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+ 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+**/
+ UINT8 PchTraceHubMode;
+
+/** Offset 0x0152 - PCH Trace Hub Memory Region 0 buffer Size
+ Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg0Size;
+
+/** Offset 0x0153 - PCH Trace Hub Memory Region 1 buffer Size
+ Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg1Size;
+
+/** Offset 0x0154 - HD Audio DMIC Link Clock Select
+ Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB
+ 0: Both, 1: ClkA, 2: ClkB
+**/
+ UINT8 PchHdaAudioLinkDmicClockSelect[2];
+
+/** Offset 0x0156 - PchPreMemRsvd
+ Reserved for PCH Pre-Mem Reserved
+ $EN_DIS
+**/
+ UINT8 PchPreMemRsvd[5];
+
+/** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 X2ApicOptOut;
+
+/** Offset 0x015C - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 DmaControlGuarantee;
+
+/** Offset 0x015D
+**/
+ UINT8 UnusedUpdSpace1[3];
+
+/** Offset 0x0160 - Base addresses for VT-d function MMIO access
+ Base addresses for VT-d MMIO access per VT-d engine
+**/
+ UINT32 VtdBaseAddress[9];
+
+/** Offset 0x0184 - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x0185 - Vtd Programming for Igd
+ 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIgdEnable;
+
+/** Offset 0x0186 - Vtd Programming for Ipu
+ 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIpuEnable;
+
+/** Offset 0x0187 - Vtd Programming for Iop
+ 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdIopEnable;
+
+/** Offset 0x0188 - Vtd Programming for ITbt
+ 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar
+ programming disabled)
+ $EN_DIS
+**/
+ UINT8 VtdItbtEnable;
+
+/** Offset 0x0189 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
+ 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
+ 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x018A - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGfx;
+
+/** Offset 0x018B - Aperture Size
+ Select the Aperture Size.
+ 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB
+**/
+ UINT8 ApertureSize;
+
+/** Offset 0x018C - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x018D
+**/
+ UINT8 UnusedUpdSpace2;
+
+/** Offset 0x018E - DDR Frequency Limit
+ Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+ 2133, 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 DdrFreqLimit;
+
+/** Offset 0x0190 - SA GV
+ System Agent dynamic frequency support and when enabled memory will be training
+ at three different frequencies.
+ 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x0191 - Memory Test on Warm Boot
+ Run Base Memory Test on Warm Boot
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemTestOnWarmBoot;
+
+/** Offset 0x0192 - DDR Speed Control
+ DDR Frequency and Gear control for all SAGV points.
+ 0:Auto, 1:Manual
+**/
+ UINT8 DdrSpeedControl;
+
+/** Offset 0x0193 - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x0194 - Controller 0 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh0]
+**/
+ UINT8 DisableDimmMc0Ch0;
+
+/** Offset 0x0195 - Controller 0 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh1]
+**/
+ UINT8 DisableDimmMc0Ch1;
+
+/** Offset 0x0196 - Controller 0 Channel 2 DIMM Control
+ Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh2]
+**/
+ UINT8 DisableDimmMc0Ch2;
+
+/** Offset 0x0197 - Controller 0 Channel 3 DIMM Control
+ Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh3]
+**/
+ UINT8 DisableDimmMc0Ch3;
+
+/** Offset 0x0198 - Controller 1 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh4]
+**/
+ UINT8 DisableDimmMc1Ch0;
+
+/** Offset 0x0199 - Controller 1 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh5]
+**/
+ UINT8 DisableDimmMc1Ch1;
+
+/** Offset 0x019A - Controller 1 Channel 2 DIMM Control
+ Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh6]
+**/
+ UINT8 DisableDimmMc1Ch2;
+
+/** Offset 0x019B - Controller 1 Channel 3 DIMM Control
+ Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs [ALIAS_NAME
+ DisableDimmCh7]
+**/
+ UINT8 DisableDimmMc1Ch3;
+
+/** Offset 0x019C - Scrambler Support
+ This option enables data scrambling in memory.
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x019D - SPD Profile Selected
+ Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+ Profile 1, 3=XMP Profile 2
+ 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
+**/
+ UINT8 SpdProfileSelected;
+
+/** Offset 0x019E - Memory Reference Clock
+ 100MHz, 133MHz.
+ 0:133MHz, 1:100MHz
+**/
+ UINT8 RefClk;
+
+/** Offset 0x019F
+**/
+ UINT8 UnusedUpdSpace3;
+
+/** Offset 0x01A0 - Memory Voltage
+ DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
+ chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
+ 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+ Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+ UINT16 VddVoltage;
+
+/** Offset 0x01A2 - Memory Ratio
+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+ recalculate memory timings listed below.
+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 Ratio;
+
+/** Offset 0x01A3 - tCL
+ CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCL;
+
+/** Offset 0x01A4 - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCWL;
+
+/** Offset 0x01A5
+**/
+ UINT8 UnusedUpdSpace4;
+
+/** Offset 0x01A6 - tFAW
+ Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tFAW;
+
+/** Offset 0x01A8 - tRAS
+ RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRAS;
+
+/** Offset 0x01AA - tRCD/tRP
+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used
+ if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+ UINT8 tRCDtRP;
+
+/** Offset 0x01AB
+**/
+ UINT8 UnusedUpdSpace5;
+
+/** Offset 0x01AC - tREFI
+ Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tREFI;
+
+/** Offset 0x01AE - tRFC
+ Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRFC;
+
+/** Offset 0x01B0 - tRRD
+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRRD;
+
+/** Offset 0x01B1 - tRTP
+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
+ values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRTP;
+
+/** Offset 0x01B2 - tWR
+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+ 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+ 34:34, 40:40
+**/
+ UINT8 tWR;
+
+/** Offset 0x01B3 - tWTR
+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tWTR;
+
+/** Offset 0x01B4 - NMode
+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+ UINT8 NModeSupport;
+
+/** Offset 0x01B5 - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x01B6 - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x01B7 - CPU Trace Hub Mode
+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+ 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
+**/
+ UINT8 CpuTraceHubMode;
+
+/** Offset 0x01B8 - CPU Trace Hub Memory Region 0
+ CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg0Size;
+
+/** Offset 0x01B9 - CPU Trace Hub Memory Region 1
+ CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg1Size;
+
+/** Offset 0x01BA - SAGV Gear Ratio
+ Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 SaGvGear[4];
+
+/** Offset 0x01BE - SAGV Frequency
+ SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
+**/
+ UINT16 SaGvFreq[4];
+
+/** Offset 0x01C6 - SAGV Disabled Gear Ratio
+ Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 GearRatio;
+
+/** Offset 0x01C7 - HECI Timeouts
+ 0: Disable, 1: Enable (Default) timeout check for HECI
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
+/** Offset 0x01C8 - HECI1 BAR address
+ BAR address of HECI1
+**/
+ UINT32 Heci1BarAddress;
+
+/** Offset 0x01CC - HECI2 BAR address
+ BAR address of HECI2
+**/
+ UINT32 Heci2BarAddress;
+
+/** Offset 0x01D0 - HECI3 BAR address
+ BAR address of HECI3
+**/
+ UINT32 Heci3BarAddress;
+
+/** Offset 0x01D4 - HG dGPU Power Delay
+ HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
+ 300=300 microseconds
+**/
+ UINT16 HgDelayAfterPwrEn;
+
+/** Offset 0x01D6 - HG dGPU Reset Delay
+ HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
+ microseconds
+**/
+ UINT16 HgDelayAfterHoldReset;
+
+/** Offset 0x01D8 - MMIO size adjustment for AUTO mode
+ Positive number means increasing MMIO size, Negative value means decreasing MMIO
+ size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+ UINT16 MmioSizeAdjustment;
+
+/** Offset 0x01DA - PCIe ASPM programming will happen in relation to the Oprom
+ Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
+ Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
+ Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
+ 0:Before, 1:After
+**/
+ UINT8 InitPcieAspmAfterOprom;
+
+/** Offset 0x01DB - Selection of the primary display device
+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics
+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics
+**/
+ UINT8 PrimaryDisplay;
+
+/** Offset 0x01DC - Selection of PSMI Region size
+ 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
+ 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
+**/
+ UINT8 PsmiRegionSize;
+
+/** Offset 0x01DD
+**/
+ UINT8 UnusedUpdSpace6[3];
+
+/** Offset 0x01E0 - Temporary MMIO address for GMADR
+ Obsolete field now and it has been extended to 64 bit address, used GmAdr64
+**/
+ UINT32 GmAdr;
+
+/** Offset 0x01E4 - Temporary MMIO address for GTTMMADR
+ The reference code will use this as Temporary MMIO address space to access GTTMMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+ UINT32 GttMmAdr;
+
+/** Offset 0x01E8 - Selection of iGFX GTT Memory size
+ 1=2MB, 2=4MB, 3=8MB, Default is 3
+ 1:2MB, 2:4MB, 3:8MB
+**/
+ UINT16 GttSize;
+
+/** Offset 0x01EA
+**/
+ UINT8 UnusedUpdSpace7[2];
+
+/** Offset 0x01EC - Hybrid Graphics GPIO information for PEG 0
+ Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie0Rtd3Gpio[24];
+
+/** Offset 0x024C - Enable/Disable MRC TXT dependency
+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+ $EN_DIS
+**/
+ UINT8 TxtImplemented;
+
+/** Offset 0x024D - Enable/Disable SA OcSupport
+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+ $EN_DIS
+**/
+ UINT8 SaOcSupport;
+
+/** Offset 0x024E - GT slice Voltage Mode
+ 0(Default): Adaptive, 1: Override
+ 0: Adaptive, 1: Override
+**/
+ UINT8 GtVoltageMode;
+
+/** Offset 0x024F - Maximum GTs turbo ratio override
+ 0(Default)=Minimal/Auto, 60=Maximum
+**/
+ UINT8 GtMaxOcRatio;
+
+/** Offset 0x0250 - The voltage offset applied to GT slice
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 GtVoltageOffset;
+
+/** Offset 0x0252 - The GT slice voltage override which is applied to the entire range of GT frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtVoltageOverride;
+
+/** Offset 0x0254 - adaptive voltage applied during turbo frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtExtraTurboVoltage;
+
+/** Offset 0x0256 - voltage offset applied to the SA
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 SaVoltageOffset;
+
+/** Offset 0x0258 - PCIe root port Function number for Hybrid Graphics dGPU
+ Root port Index number to indicate which PCIe root port has dGPU
+**/
+ UINT8 RootPortIndex;
+
+/** Offset 0x0259 - Realtime Memory Timing
+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+ realtime memory timing changes after MRC_DONE.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 RealtimeMemoryTiming;
+
+/** Offset 0x025A - iTBT PCIe Multiple Segment setting
+ When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
+ TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieMultipleSegmentEnabled;
+
+/** Offset 0x025B - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
+**/
+ UINT8 SaIpuEnable;
+
+/** Offset 0x025C - IPU IMR Configuration
+ 0:IPU Camera, 1:IPU Gen Default is 0
+ 0:IPU Camera, 1:IPU Gen
+**/
+ UINT8 SaIpuImrConfiguration;
+
+/** Offset 0x025D - IMGU CLKOUT Configuration
+ The configuration of IMGU CLKOUT, 0: Disable;1: Enable.
+ $EN_DIS
+**/
+ UINT8 ImguClkOutEn[6];
+
+/** Offset 0x0263
+**/
+ UINT8 UnusedUpdSpace8;
+
+/** Offset 0x0264 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 CpuPcieRpEnableMask;
+
+/** Offset 0x0268 - Assertion on Link Down GPIOs
+ GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
+ GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
+ 0:Disable, 1:Enable
+**/
+ UINT8 CpuPcieRpLinkDownGpios;
+
+/** Offset 0x0269 - Enable ClockReq Messaging
+ ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default):
+ Enable ClockReq Messaging [ALIAS_NAME RpClockReqMsgEnable]
+ 0:Disable, 1:Enable
+**/
+ UINT8 CpuPcieRpClockReqMsgEnable;
+
+/** Offset 0x026A - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
+ 4: Gen4 (see: CPU_PCIE_SPEED). [ALIAS_NAME RpPcieThresholdBytes]
+**/
+ UINT8 CpuPcieRpPcieSpeed[4];
+
+/** Offset 0x026E - Selection of PSMI Support On/Off
+ 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
+ $EN_DIS
+**/
+ UINT8 GtPsmiSupport;
+
+/** Offset 0x026F - Selection of DiSM Region Size
+ DiSM Size to be allocated for 2LM Sku Default is 0
+ 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB
+**/
+ UINT8 DismSize;
+
+/** Offset 0x0270 - Enable Display memory map programming for DFD Restore
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DfdRestoreEnable;
+
+/** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device
+ 0=Disabled,1(Default)=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortAConfig;
+
+/** Offset 0x0272 - Program GPIOs for LFP on DDI port-B device
+ 0(Default)=Disabled,1=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortBConfig;
+
+/** Offset 0x0273 - Enable or disable HPD of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortAHpd;
+
+/** Offset 0x0274 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x0275 - Enable or disable HPD of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x0276 - Enable or disable HPD of DDI port 1
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Hpd;
+
+/** Offset 0x0277 - Enable or disable HPD of DDI port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Hpd;
+
+/** Offset 0x0278 - Enable or disable HPD of DDI port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Hpd;
+
+/** Offset 0x0279 - Enable or disable HPD of DDI port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Hpd;
+
+/** Offset 0x027A - Enable or disable DDC of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortADdc;
+
+/** Offset 0x027B - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x027C - Enable or disable DDC of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x027D - Enable DDC setting of DDI Port 1
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Ddc;
+
+/** Offset 0x027E - Enable DDC setting of DDI Port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Ddc;
+
+/** Offset 0x027F - Enable DDC setting of DDI Port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Ddc;
+
+/** Offset 0x0280 - Enable DDC setting of DDI Port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Ddc;
+
+/** Offset 0x0281 - Enable Gt CLOS
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 GtClosEnable;
+
+/** Offset 0x0282
+**/
+ UINT8 UnusedUpdSpace9[6];
+
+/** Offset 0x0288 - Temporary MMIO address for GMADR
+ The reference code will use this as Temporary MMIO address space to access GMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+ (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
+ - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB)
+**/
+ UINT64 GmAdr64;
+
+/** Offset 0x0290 - Hybrid Graphics Slot Selection
+ PEG or PCH Slot Selection for Hybrid Graphics
+**/
+ UINT8 HgSlot;
+
+/** Offset 0x0291 - DMI ASPM Configuration:{Combo
+ Set ASPM Configuration
+ 0:Disabled, 1:L0s, 2:L1, 3:L1L0s
+**/
+ UINT8 DmiAspm;
+
+/** Offset 0x0292 - DMI ASPM Control Configuration:{Combo
+ Set ASPM Control configuration
+ 0:Disabled, 1:L0s, 2:L1, 3:L1L0s
+**/
+ UINT8 DmiAspmCtrl;
+
+/** Offset 0x0293 - DMI ASPM L1 exit Latency
+ Range: 0-7, 4 is default L1 exit Latency
+**/
+ UINT8 DmiAspmL1ExitLatency;
+
+/** Offset 0x0294 - Per-core HT Disable
+ Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
+ 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value
+ of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have
+ HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1.
+**/
+ UINT16 PerCoreHtDisable;
+
+/** Offset 0x0296 - DEKEL CDR Relock
+ Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieRpCdrRelock[4];
+
+/** Offset 0x029A - Realtime Memory OverClock
+ Disable/Enables Realtime Memory OverClock
+ $EN_DIS
+**/
+ UINT8 RealtimeMemoryOC;
+
+/** Offset 0x029B - Xl1el
+ Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieNewFom[4];
+
+/** Offset 0x029F - Xl1el
+ Enable/Disable NewFomDisable. 0: Disable(Default); 1: Enable
+**/
+ UINT8 CpuPcieIotgMode[4];
+
+/** Offset 0x02A3 - SaPreMemProductionRsvd
+ Reserved for SA Pre-Mem Production
+ $EN_DIS
+**/
+ UINT8 SaPreMemProductionRsvd[87];
+
+/** Offset 0x02FA - DMI Max Link Speed
+ Auto (0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2):
+ Limit Link to Gen2 Speed, (Default) Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 DmiMaxLinkSpeed;
+
+/** Offset 0x02FB - DMI Equalization Phase 2
+ DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
+ AUTO - Use the current default method
+ 0:Disable phase2, 1:Enable phase2, 2:Auto
+**/
+ UINT8 DmiGen3EqPh2Enable;
+
+/** Offset 0x02FC - DMI Gen3 Equalization Phase3
+ DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 DmiGen3EqPh3Method;
+
+/** Offset 0x02FD - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+ Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiGen3ProgramStaticEq;
+
+/** Offset 0x02FE - DeEmphasis control for DMI
+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+ 0: -6dB, 1: -3.5dB
+**/
+ UINT8 DmiDeEmphasis;
+
+/** Offset 0x02FF - DMI Gen3 Root port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 DmiGen3RootPortPreset[8];
+
+/** Offset 0x0307 - DMI Gen3 End port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+ UINT8 DmiGen3EndPointPreset[8];
+
+/** Offset 0x030F - DMI Gen3 End port Hint values per lane
+ Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 DmiGen3EndPointHint[8];
+
+/** Offset 0x0317 - DMI Gen3 RxCTLEp per-Bundle control
+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
+**/
+ UINT8 DmiGen3RxCtlePeaking[4];
+
+/** Offset 0x031B - BIST on Reset
+ Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 BistOnReset;
+
+/** Offset 0x031C - Skip Stop PBET Timer Enable/Disable
+ Skip Stop PBET Timer; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 SkipStopPbet;
+
+/** Offset 0x031D - C6DRAM power gating feature
+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature.
+ $EN_DIS
+**/
+ UINT8 EnableC6Dram;
+
+/** Offset 0x031E - Over clocking support
+ Over clocking support; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcSupport;
+
+/** Offset 0x031F - Over clocking Lock
+ Over clocking Lock Enable/Disable; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcLock;
+
+/** Offset 0x0320 - Maximum Core Turbo Ratio Override
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the
+ fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85
+**/
+ UINT8 CoreMaxOcRatio;
+
+/** Offset 0x0321 - Core voltage mode
+ Core voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 CoreVoltageMode;
+
+/** Offset 0x0322 - Maximum clr turbo ratio override
+ Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+ fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85
+**/
+ UINT8 RingMaxOcRatio;
+
+/** Offset 0x0323 - Hyper Threading Enable/Disable
+ Enable or Disable Hyper Threading; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 HyperThreading;
+
+/** Offset 0x0324 - Enable or Disable CPU Ratio Override
+ Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CpuRatioOverride;
+
+/** Offset 0x0325 - CPU ratio value
+ CPU ratio value. Valid Range 0 to 63
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x0326 - Boot frequency
+ Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.
+ 1: Maximum non-turbo performance. 2: Turbo performance
+ 0:0, 1:1, 2:2
+**/
+ UINT8 BootFrequency;
+
+/** Offset 0x0327 - Number of active cores
+ Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2:
+ 2 ;3: 3
+ 0:All, 1:1, 2:2, 3:3
+**/
+ UINT8 ActiveCoreCount;
+
+/** Offset 0x0328 - Processor Early Power On Configuration FCLK setting
+ 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.-
+ 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x0329 - Set JTAG power in C10 and deeper power states
+ False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
+ and deeper power states for debug purpose. 0: False; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 JtagC10PowerGateDisable;
+
+/** Offset 0x032A - Enable or Disable VMX
+ Enable or Disable VMX; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x032B - AVX2 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx2RatioOffset;
+
+/** Offset 0x032C - AVX3 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx3RatioOffset;
+
+/** Offset 0x032D - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0:
+ Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
+/** Offset 0x032E - core voltage override
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageOverride;
+
+/** Offset 0x0330 - Core Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageAdaptive;
+
+/** Offset 0x0332 - Core Turbo voltage Offset
+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+ UINT16 CoreVoltageOffset;
+
+/** Offset 0x0334 - Core PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 CorePllVoltageOffset;
+
+/** Offset 0x0335 - Ring Downbin
+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+ lower than the core ratio.0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 RingDownBin;
+
+/** Offset 0x0336 - Ring voltage mode
+ Ring voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 RingVoltageMode;
+
+/** Offset 0x0337 - TjMax Offset
+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+ UINT8 TjMaxOffset;
+
+/** Offset 0x0338 - Ring voltage override
+ The ring voltage override which is applied to the entire range of cpu ring frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageOverride;
+
+/** Offset 0x033A - Ring Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageAdaptive;
+
+/** Offset 0x033C - Ring Turbo voltage Offset
+ The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
+**/
+ UINT16 RingVoltageOffset;
+
+/** Offset 0x033E - Enable or Disable TME
+ Enable or Disable TME; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TmeEnable;
+
+/** Offset 0x033F - Enable CPU CrashLog
+ Enable or Disable CPU CrashLog; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
+
+/** Offset 0x0340 - ElixirSpringsPatchAddr
+ DEPRECATED
+**/
+ UINT32 ElixirSpringsPatchAddr;
+
+/** Offset 0x0344 - ElixirSpringsPatchSize
+ DEPRECATED
+**/
+ UINT32 ElixirSpringsPatchSize;
+
+/** Offset 0x0348 - CPU Run Control
+ Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2:
+ No Change
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DebugInterfaceEnable;
+
+/** Offset 0x0349 - CPU Run Control Lock
+ Lock or Unlock CPU Run Control; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceLockEnable;
+
+/** Offset 0x034A - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x034B
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x034C - EnableSgx
+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
+ 0: Disable, 1: Enable, 2: Software Control
+**/
+ UINT8 EnableSgx;
+
+/** Offset 0x034D - Txt
+ Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 Txt;
+
+/** Offset 0x034E
+**/
+ UINT8 UnusedUpdSpace10[2];
+
+/** Offset 0x0350 - PrmrrSize
+ Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x0354 - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x0358 - TxtDprMemoryBase
+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+ UINT64 TxtDprMemoryBase;
+
+/** Offset 0x0360 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x0364 - TxtDprMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x0368 - BiosAcmBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 BiosAcmBase;
+
+/** Offset 0x036C - BiosAcmSize
+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+ UINT32 BiosAcmSize;
+
+/** Offset 0x0370 - ApStartupBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 ApStartupBase;
+
+/** Offset 0x0374 - TgaSize
+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+ UINT32 TgaSize;
+
+/** Offset 0x0378 - TxtLcpPdBase
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+ UINT64 TxtLcpPdBase;
+
+/** Offset 0x0380 - TxtLcpPdSize
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+ UINT64 TxtLcpPdSize;
+
+/** Offset 0x0388 - IsTPMPresence
+ IsTPMPresence default values
+**/
+ UINT8 IsTPMPresence;
+
+/** Offset 0x0389 - Configuration for boot TDP selection
+ Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP
+ Up;0xFF : Deactivate
+**/
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x038A - ReservedSecurityPreMem
+ Reserved for Security Pre-Mem
+ $EN_DIS
+**/
+ UINT8 ReservedSecurityPreMem[5];
+
+/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
+ Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtleEnable[24];
+
+/** Offset 0x03A7 - PCH HSIO PCIE Rx Set Ctle Value
+ PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtle[24];
+
+/** Offset 0x03BF - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
+
+/** Offset 0x03D7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
+
+/** Offset 0x03EF - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
+
+/** Offset 0x0407 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
+
+/** Offset 0x041F - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
+
+/** Offset 0x0437 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
+
+/** Offset 0x044F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
+
+/** Offset 0x0467 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+ PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmph[24];
+
+/** Offset 0x047F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
+
+/** Offset 0x0497 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
+
+/** Offset 0x04AF - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
+
+/** Offset 0x04C7 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
+
+/** Offset 0x04DF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
+
+/** Offset 0x04E7 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMag[8];
+
+/** Offset 0x04EF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
+
+/** Offset 0x04F7 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMag[8];
+
+/** Offset 0x04FF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
+
+/** Offset 0x0507 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMag[8];
+
+/** Offset 0x050F - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
+
+/** Offset 0x0517 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmp[8];
+
+/** Offset 0x051F - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
+
+/** Offset 0x0527 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmp[8];
+
+/** Offset 0x052F - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
+
+/** Offset 0x0537 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmp[8];
+
+/** Offset 0x053F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DeEmphEnable[8];
+
+/** Offset 0x0547 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen1DeEmph[8];
+
+/** Offset 0x054F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DeEmphEnable[8];
+
+/** Offset 0x0557 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen2DeEmph[8];
+
+/** Offset 0x055F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DeEmphEnable[8];
+
+/** Offset 0x0567 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen3DeEmph[8];
+
+/** Offset 0x056F - PCH LPC Enhanced Port 80 Decoding
+ Original LPC only decodes one byte of port 80h.
+ $EN_DIS
+**/
+ UINT8 PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x0570 - PCH Port80 Route
+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+ 0:LPC, 1:PCI
+**/
+ UINT8 PchPort80Route;
+
+/** Offset 0x0571 - Enable SMBus ARP support
+ Enable SMBus ARP support.
+ $EN_DIS
+**/
+ UINT8 SmbusArpEnable;
+
+/** Offset 0x0572 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0573
+**/
+ UINT8 UnusedUpdSpace11;
+
+/** Offset 0x0574 - SMBUS Base Address
+ SMBUS Base Address (IO space).
+**/
+ UINT16 PchSmbusIoBase;
+
+/** Offset 0x0576 - Enable SMBus Alert Pin
+ Enable SMBus Alert Pin.
+ $EN_DIS
+**/
+ UINT8 PchSmbAlertEnable;
+
+/** Offset 0x0577 - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+ (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[16];
+
+/** Offset 0x0587 - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[16];
+
+/** Offset 0x0597
+**/
+ UINT8 UnusedUpdSpace12;
+
+/** Offset 0x0598 - Point of RsvdSmbusAddressTable
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+ UINT32 RsvdSmbusAddressTablePtr;
+
+/** Offset 0x059C - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x05A0 - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x05A1 - Serial Io Uart Debug Controller Number
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 SerialIoUartDebugControllerNumber;
+
+/** Offset 0x05A2 - Serial Io Uart Debug Auto Flow
+ Enables UART hardware flow control, CTS and RTS lines.
+ $EN_DIS
+**/
+ UINT8 SerialIoUartDebugAutoFlow;
+
+/** Offset 0x05A3
+**/
+ UINT8 UnusedUpdSpace13;
+
+/** Offset 0x05A4 - Serial Io Uart Debug BaudRate
+ Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+ 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+ UINT32 SerialIoUartDebugBaudRate;
+
+/** Offset 0x05A8 - Serial Io Uart Debug Parity
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartDebugParity;
+
+/** Offset 0x05A9 - Serial Io Uart Debug Stop Bits
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 SerialIoUartDebugStopBits;
+
+/** Offset 0x05AA - Serial Io Uart Debug Data Bits
+ Set default word length. 0: Default, 5,6,7,8
+ 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+ UINT8 SerialIoUartDebugDataBits;
+
+/** Offset 0x05AB
+**/
+ UINT8 UnusedUpdSpace14;
+
+/** Offset 0x05AC - Serial Io Uart Debug Mmio Base
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 SerialIoUartDebugMmioBase;
+
+/** Offset 0x05B0 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x05B1 - GT PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 GtPllVoltageOffset;
+
+/** Offset 0x05B2 - Ring PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 RingPllVoltageOffset;
+
+/** Offset 0x05B3 - System Agent PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 SaPllVoltageOffset;
+
+/** Offset 0x05B4 - Memory Controller PLL voltage offset
+ Core PLL voltage offset. 0: No offset. Range 0-63
+**/
+ UINT8 McPllVoltageOffset;
+
+/** Offset 0x05B5 - MRC Safe Config
+ Enables/Disable MRC Safe Config
+ $EN_DIS
+**/
+ UINT8 MrcSafeConfig;
+
+/** Offset 0x05B6 - TCSS Thunderbolt PCIE Root Port 0 Enable
+ Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie0En;
+
+/** Offset 0x05B7 - TCSS Thunderbolt PCIE Root Port 1 Enable
+ Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie1En;
+
+/** Offset 0x05B8 - TCSS Thunderbolt PCIE Root Port 2 Enable
+ Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie2En;
+
+/** Offset 0x05B9 - TCSS Thunderbolt PCIE Root Port 3 Enable
+ Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie3En;
+
+/** Offset 0x05BA - TCSS USB HOST (xHCI) Enable
+ Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
+ $EN_DIS
+**/
+ UINT8 TcssXhciEn;
+
+/** Offset 0x05BB - TCSS USB DEVICE (xDCI) Enable
+ Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
+ $EN_DIS
+**/
+ UINT8 TcssXdciEn;
+
+/** Offset 0x05BC - TCSS DMA0 Enable
+ Set TCSS DMA0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma0En;
+
+/** Offset 0x05BD - TCSS DMA1 Enable
+ Set TCSS DMA1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma1En;
+
+/** Offset 0x05BE - PcdSerialDebugBaudRate
+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+ 3:9600, 4:19200, 6:56700, 7:115200
+**/
+ UINT8 PcdSerialDebugBaudRate;
+
+/** Offset 0x05BF - HobBufferSize
+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+ total HOB size).
+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+ UINT8 HobBufferSize;
+
+/** Offset 0x05C0 - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x05C1 - SenseAmp Offset Training
+ Enables/Disable SenseAmp Offset Training
+ $EN_DIS
+**/
+ UINT8 SOT;
+
+/** Offset 0x05C2 - Early ReadMPR Timing Centering 2D
+ Enables/Disable Early ReadMPR Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDMPRTC2D;
+
+/** Offset 0x05C3 - Read MPR Training
+ Enables/Disable Read MPR Training
+ $EN_DIS
+**/
+ UINT8 RDMPRT;
+
+/** Offset 0x05C4 - Receive Enable Training
+ Enables/Disable Receive Enable Training
+ $EN_DIS
+**/
+ UINT8 RCVET;
+
+/** Offset 0x05C5 - Jedec Write Leveling
+ Enables/Disable Jedec Write Leveling
+ $EN_DIS
+**/
+ UINT8 JWRL;
+
+/** Offset 0x05C6 - Early Write Time Centering 2D
+ Enables/Disable Early Write Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 EWRTC2D;
+
+/** Offset 0x05C7 - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDTC2D;
+
+/** Offset 0x05C8 - Write Timing Centering 1D
+ Enables/Disable Write Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRTC1D;
+
+/** Offset 0x05C9 - Write Voltage Centering 1D
+ Enables/Disable Write Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRVC1D;
+
+/** Offset 0x05CA - Read Timing Centering 1D
+ Enables/Disable Read Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDTC1D;
+
+/** Offset 0x05CB - Dimm ODT Training
+ Enables/Disable Dimm ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTT;
+
+/** Offset 0x05CC - DIMM RON Training
+ Enables/Disable DIMM RON Training
+ $EN_DIS
+**/
+ UINT8 DIMMRONT;
+
+/** Offset 0x05CD - Write Drive Strength/Equalization 2D
+ Enables/Disable Write Drive Strength/Equalization 2D
+ $EN_DIS
+**/
+ UINT8 WRDSEQT;
+
+/** Offset 0x05CE - Write Slew Rate Training
+ Enables/Disable Write Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 WRSRT;
+
+/** Offset 0x05CF - Read ODT Training
+ Enables/Disable Read ODT Training
+ $EN_DIS
+**/
+ UINT8 RDODTT;
+
+/** Offset 0x05D0 - Read Equalization Training
+ Enables/Disable Read Equalization Training
+ $EN_DIS
+**/
+ UINT8 RDEQT;
+
+/** Offset 0x05D1 - Read Amplifier Training
+ Enables/Disable Read Amplifier Training
+ $EN_DIS
+**/
+ UINT8 RDAPT;
+
+/** Offset 0x05D2 - Write Timing Centering 2D
+ Enables/Disable Write Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRTC2D;
+
+/** Offset 0x05D3 - Read Timing Centering 2D
+ Enables/Disable Read Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDTC2D;
+
+/** Offset 0x05D4 - Write Voltage Centering 2D
+ Enables/Disable Write Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRVC2D;
+
+/** Offset 0x05D5 - Read Voltage Centering 2D
+ Enables/Disable Read Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDVC2D;
+
+/** Offset 0x05D6 - Command Voltage Centering
+ Enables/Disable Command Voltage Centering
+ $EN_DIS
+**/
+ UINT8 CMDVC;
+
+/** Offset 0x05D7 - Late Command Training
+ Enables/Disable Late Command Training
+ $EN_DIS
+**/
+ UINT8 LCT;
+
+/** Offset 0x05D8 - Round Trip Latency Training
+ Enables/Disable Round Trip Latency Training
+ $EN_DIS
+**/
+ UINT8 RTL;
+
+/** Offset 0x05D9 - Turn Around Timing Training
+ Enables/Disable Turn Around Timing Training
+ $EN_DIS
+**/
+ UINT8 TAT;
+
+/** Offset 0x05DA - Memory Test
+ Enables/Disable Memory Test
+ $EN_DIS
+**/
+ UINT8 MEMTST;
+
+/** Offset 0x05DB - DIMM SPD Alias Test
+ Enables/Disable DIMM SPD Alias Test
+ $EN_DIS
+**/
+ UINT8 ALIASCHK;
+
+/** Offset 0x05DC - Receive Enable Centering 1D
+ Enables/Disable Receive Enable Centering 1D
+ $EN_DIS
+**/
+ UINT8 RCVENC1D;
+
+/** Offset 0x05DD - Retrain Margin Check
+ Enables/Disable Retrain Margin Check
+ $EN_DIS
+**/
+ UINT8 RMC;
+
+/** Offset 0x05DE - Write Drive Strength Up/Dn independently
+ Enables/Disable Write Drive Strength Up/Dn independently
+ $EN_DIS
+**/
+ UINT8 WRDSUDT;
+
+/** Offset 0x05DF - ECC Support
+ Enables/Disable ECC Support
+ $EN_DIS
+**/
+ UINT8 EccSupport;
+
+/** Offset 0x05E0 - Ibecc
+ In-Band ECC Support
+ $EN_DIS
+**/
+ UINT8 Ibecc;
+
+/** Offset 0x05E1 - IbeccParity
+ In-Band ECC Parity Control
+ $EN_DIS
+**/
+ UINT8 IbeccParity;
+
+/** Offset 0x05E2 - IbeccOperationMode
+ In-Band ECC Operation Mode
+ 0:Protect base on address range, 1: Non-protected, 2: All protected
+**/
+ UINT8 IbeccOperationMode;
+
+/** Offset 0x05E3 - IbeccProtectedRegionEnable
+ In-Band ECC Protected Region Enable
+ $EN_DIS
+**/
+ UINT8 IbeccProtectedRegionEnable[8];
+
+/** Offset 0x05EB
+**/
+ UINT8 UnusedUpdSpace15[1];
+
+/** Offset 0x05EC - IbeccProtectedRegionBases
+ IBECC Protected Region Bases
+**/
+ UINT16 IbeccProtectedRegionBase[8];
+
+/** Offset 0x05FC - IbeccProtectedRegionMasks
+ IBECC Protected Region Masks
+**/
+ UINT16 IbeccProtectedRegionMask[8];
+
+/** Offset 0x060C - Memory Remap
+ Enables/Disable Memory Remap
+ $EN_DIS
+**/
+ UINT8 RemapEnable;
+
+/** Offset 0x060D - Rank Interleave support
+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+ the same time.
+ $EN_DIS
+**/
+ UINT8 RankInterleave;
+
+/** Offset 0x060E - Enhanced Interleave support
+ Enables/Disable Enhanced Interleave support
+ $EN_DIS
+**/
+ UINT8 EnhancedInterleave;
+
+/** Offset 0x060F - Ch Hash Support
+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT8 ChHashEnable;
+
+/** Offset 0x0610 - Extern Therm Status
+ Enables/Disable Extern Therm Status
+ $EN_DIS
+**/
+ UINT8 EnableExtts;
+
+/** Offset 0x0611 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDn;
+
+/** Offset 0x0612 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDnLpddr;
+
+/** Offset 0x0613 - SelfRefresh Enable
+ Enables/Disable SelfRefresh Enable
+ $EN_DIS
+**/
+ UINT8 SrefCfgEna;
+
+/** Offset 0x0614 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x0615 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeat;
+
+/** Offset 0x0616 - Enable RH Prevention
+ Enables/Disable RH Prevention
+ $EN_DIS
+**/
+ UINT8 RhPrevention;
+
+/** Offset 0x0617 - Exit On Failure (MRC)
+ Enables/Disable Exit On Failure (MRC)
+ $EN_DIS
+**/
+ UINT8 ExitOnFailure;
+
+/** Offset 0x0618 - New Features 1 - MRC
+ New Feature Enabling 1, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 NewFeatureEnable1;
+
+/** Offset 0x0619 - New Features 2 - MRC
+ New Feature Enabling 2, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 NewFeatureEnable2;
+
+/** Offset 0x061A - Duty Cycle Correction Training
+ Enable/Disable Duty Cycle Correction Training
+ $EN_DIS
+**/
+ UINT8 DCC;
+
+/** Offset 0x061B - Read Voltage Centering 1D
+ Enable/Disable Read Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDVC1D;
+
+/** Offset 0x061C - TxDqTCO Comp Training
+ Enable/Disable TxDqTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCO;
+
+/** Offset 0x061D - ClkTCO Comp Training
+ Enable/Disable ClkTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 CLKTCO;
+
+/** Offset 0x061E - CMD Slew Rate Training
+ Enable/Disable CMD Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 CMDSR;
+
+/** Offset 0x061F - CMD Drive Strength and Tx Equalization
+ Enable/Disable CMD Drive Strength and Tx Equalization
+ $EN_DIS
+**/
+ UINT8 CMDDSEQ;
+
+/** Offset 0x0620 - DIMM CA ODT Training
+ Enable/Disable DIMM CA ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTCA;
+
+/** Offset 0x0621 - TxDqsTCO Comp Training
+ Enable/Disable TxDqsTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCODQS;
+
+/** Offset 0x0622 - CMD/CTL Drive Strength Up/Dn 2D
+ Enable/Disable CMD/CTL Drive Strength Up/Dn 2D
+ $EN_DIS
+**/
+ UINT8 CMDDRUD;
+
+/** Offset 0x0623 - VccDLL Bypass Training
+ Enable/Disable VccDLL Bypass Training
+ $EN_DIS
+**/
+ UINT8 VCCDLLBP;
+
+/** Offset 0x0624 - PanicVttDnLp Training
+ Enable/Disable PanicVttDnLp Training
+ $EN_DIS
+**/
+ UINT8 PVTTDNLP;
+
+/** Offset 0x0625 - Read Vref Decap Training*
+ Enable/Disable Read Vref Decap Training*
+ $EN_DIS
+**/
+ UINT8 RDVREFDC;
+
+/** Offset 0x0626 - Vddq Training
+ Enable/Disable Vddq Training
+ $EN_DIS
+**/
+ UINT8 VDDQT;
+
+/** Offset 0x0627 - Rank Margin Tool Per Bit
+ Enable/Disable Rank Margin Tool Per Bit
+ $EN_DIS
+**/
+ UINT8 RMTBIT;
+
+/** Offset 0x0628 - Override Performance Downgrade for Mixed Memory
+ Disable/Enables Override Performance Downgrade for Mixed Memory
+ $EN_DIS
+**/
+ UINT8 OverrideDowngradeForMixedMemory;
+
+/** Offset 0x0629
+**/
+ UINT8 Reserved2[1];
+
+/** Offset 0x062A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedClock;
+
+/** Offset 0x062B - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedZq;
+
+/** Offset 0x062C - Ch Hash Interleaved Bit
+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+ UINT8 ChHashInterleaveBit;
+
+/** Offset 0x062D
+**/
+ UINT8 UnusedUpdSpace16;
+
+/** Offset 0x062E - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6] Default is 0x0830
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x0630 - Base reference clock value
+ Base reference clock value, in Hertz(Default is 100Hz)
+ 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
+**/
+ UINT32 BClkFrequency;
+
+/** Offset 0x0634 - EPG DIMM Idd3N
+ Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
+ a per DIMM basis. Default is 26
+**/
+ UINT16 Idd3n;
+
+/** Offset 0x0636 - EPG DIMM Idd3P
+ Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
+ on a per DIMM basis. Default is 11
+**/
+ UINT16 Idd3p;
+
+/** Offset 0x0638 - RH Activation Probability
+ RH Activation Probability, Probability value is 1/2^(inputvalue)
+**/
+ UINT8 RhActProbability;
+
+/** Offset 0x0639 - Idle Energy Mc0Ch0Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch0Dimm0;
+
+/** Offset 0x063A - Idle Energy Mc0Ch0Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch0Dimm1;
+
+/** Offset 0x063B - Idle Energy Mc0Ch1Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch1Dimm0;
+
+/** Offset 0x063C - Idle Energy Mc0Ch1Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc0Ch1Dimm1;
+
+/** Offset 0x063D - Idle Energy Mc1Ch0Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch0Dimm0;
+
+/** Offset 0x063E - Idle Energy Mc1Ch0Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch0Dimm1;
+
+/** Offset 0x063F - Idle Energy Mc1Ch1Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0640 - Idle Energy Mc1Ch1Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0641 - PowerDown Energy Mc0Ch0Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch0Dimm0;
+
+/** Offset 0x0642 - PowerDown Energy Mc0Ch0Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch0Dimm1;
+
+/** Offset 0x0643 - PowerDown Energy Mc0Ch1Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch1Dimm0;
+
+/** Offset 0x0644 - PowerDown Energy Mc0Ch1Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc0Ch1Dimm1;
+
+/** Offset 0x0645 - PowerDown Energy Mc1Ch0Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch0Dimm0;
+
+/** Offset 0x0646 - PowerDown Energy Mc1Ch0Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch0Dimm1;
+
+/** Offset 0x0647 - PowerDown Energy Mc1Ch1Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0648 - PowerDown Energy Mc1Ch1Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
+**/
+ UINT8 PdEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0649 - Activate Energy Mc0Ch0Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch0Dimm0;
+
+/** Offset 0x064A - Activate Energy Mc0Ch0Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch0Dimm1;
+
+/** Offset 0x064B - Activate Energy Mc0Ch1Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch1Dimm0;
+
+/** Offset 0x064C - Activate Energy Mc0Ch1Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc0Ch1Dimm1;
+
+/** Offset 0x064D - Activate Energy Mc1Ch0Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch0Dimm0;
+
+/** Offset 0x064E - Activate Energy Mc1Ch0Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch0Dimm1;
+
+/** Offset 0x064F - Activate Energy Mc1Ch1Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0650 - Activate Energy Mc1Ch1Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0651 - Read Energy Mc0Ch0Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch0Dimm0;
+
+/** Offset 0x0652 - Read Energy Mc0Ch0Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch0Dimm1;
+
+/** Offset 0x0653 - Read Energy Mc0Ch1Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch1Dimm0;
+
+/** Offset 0x0654 - Read Energy Mc0Ch1Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc0Ch1Dimm1;
+
+/** Offset 0x0655 - Read Energy Mc1Ch0Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch0Dimm0;
+
+/** Offset 0x0656 - Read Energy Mc1Ch0Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch0Dimm1;
+
+/** Offset 0x0657 - Read Energy Mc1Ch1Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0658 - Read Energy Mc1Ch1Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0659 - Write Energy Mc0Ch0Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch0Dimm0;
+
+/** Offset 0x065A - Write Energy Mc0Ch0Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch0Dimm1;
+
+/** Offset 0x065B - Write Energy Mc0Ch1Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch1Dimm0;
+
+/** Offset 0x065C - Write Energy Mc0Ch1Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc0Ch1Dimm1;
+
+/** Offset 0x065D - Write Energy Mc1Ch0Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch0Dimm0;
+
+/** Offset 0x065E - Write Energy Mc1Ch0Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch0Dimm1;
+
+/** Offset 0x065F - Write Energy Mc1Ch1Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch1Dimm0;
+
+/** Offset 0x0660 - Write Energy Mc1Ch1Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyMc1Ch1Dimm1;
+
+/** Offset 0x0661 - Throttler CKEMin Timer
+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+ Dfault is 0x00
+**/
+ UINT8 ThrtCkeMinTmr;
+
+/** Offset 0x0662 - Rapl Power Floor Ch0
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh0;
+
+/** Offset 0x0663 - Rapl Power Floor Ch1
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh1;
+
+/** Offset 0x0664 - Command Rate Support
+ CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
+ 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
+**/
+ UINT8 EnCmdRate;
+
+/** Offset 0x0665 - REFRESH_2X_MODE
+ 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
+ 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
+**/
+ UINT8 Refresh2X;
+
+/** Offset 0x0666 - Energy Performance Gain
+ Enable/disable(default) Energy Performance Gain.
+ $EN_DIS
+**/
+ UINT8 EpgEnable;
+
+/** Offset 0x0667 - Row Hammer Solution
+ Type of method used to prevent Row Hammer. Default is Hardware RHP
+ 0:Hardware RHP, 1:2x Refresh
+**/
+ UINT8 RhSolution;
+
+/** Offset 0x0668 - User Manual Threshold
+ Disabled: Predefined threshold will be used.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserThresholdEnable;
+
+/** Offset 0x0669 - User Manual Budget
+ Disabled: Configuration of memories will defined the Budget value.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserBudgetEnable;
+
+/** Offset 0x066A - Power Down Mode
+ This option controls command bus tristating during idle periods
+ 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
+**/
+ UINT8 PowerDownMode;
+
+/** Offset 0x066B - Pwr Down Idle Timer
+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+ AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+ UINT8 PwdwnIdleCounter;
+
+/** Offset 0x066C - Page Close Idle Timeout
+ This option controls Page Close Idle Timeout
+ 0:Enabled, 1:Disabled
+**/
+ UINT8 DisPgCloseIdleTimeout;
+
+/** Offset 0x066D - Bitmask of ranks that have CA bus terminated
+ Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default,
+ Rank0 is terminating and Rank1 is non-terminating
+**/
+ UINT8 CmdRanksTerminated;
+
+/** Offset 0x066E - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x066F - Fivr Faults
+ Fivr Faults; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 FivrFaults;
+
+/** Offset 0x0670 - Fivr Efficiency
+ Fivr Efficiency Management; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 FivrEfficiency;
+
+/** Offset 0x0671 - Safe Mode Support
+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+ $EN_DIS
+**/
+ UINT8 SafeMode;
+
+/** Offset 0x0672 - Ask MRC to clear memory content
+ Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x0673 - LpDdrDqDqsReTraining
+ Enables/Disable LpDdrDqDqsReTraining
+ $EN_DIS
+**/
+ UINT8 LpDdrDqDqsReTraining;
+
+/** Offset 0x0674 - TCSS USB Port Enable
+ Bitmap for per port enabling
+**/
+ UINT8 UsbTcPortEnPreMem;
+
+/** Offset 0x0675
+**/
+ UINT8 UnusedUpdSpace17;
+
+/** Offset 0x0676 - Post Code Output Port
+ This option configures Post Code Output Port
+**/
+ UINT16 PostCodeOutputPort;
+
+/** Offset 0x0678 - RMTLoopCount
+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+ UINT8 RMTLoopCount;
+
+/** Offset 0x0679 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
+/** Offset 0x067A - WRC Feature
+ Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports
+ IO devices allocating onto the ring and into LLC. WRC is fused on by default.
+ $EN_DIS
+**/
+ UINT8 WrcFeatureEnable;
+
+/** Offset 0x067B
+**/
+ UINT8 UnusedUpdSpace18[1];
+
+/** Offset 0x067C - BCLK RFI Frequency
+ Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No
+ RFI Tuning. Range is 98Mhz-100Mhz.
+**/
+ UINT32 BclkRfiFreq[4];
+
+/** Offset 0x068C - Size of PCIe IMR.
+ Size of PCIe IMR in megabytes
+**/
+ UINT16 PcieImrSize;
+
+/** Offset 0x068E - Enable PCIe IMR
+ 0: Disable(AUTO), 1: Enable
+ $EN_DIS
+**/
+ UINT8 PcieImrEnabled;
+
+/** Offset 0x068F - Enable PCIe IMR
+ 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
+ the Root port location from PCH PCIe or SA PCIe
+ $EN_DIS
+**/
+ UINT8 PcieImrRpLocation;
+
+/** Offset 0x0690 - Root port number for IMR.
+ Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
+ from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
+**/
+ UINT8 PcieImrRpSelection;
+
+/** Offset 0x0691 - SerialDebugMrcLevel
+ MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 SerialDebugMrcLevel;
+
+/** Offset 0x0692 - Mem Boot Mode
+ 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
+ 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
+**/
+ UINT8 MemBootMode;
+
+/** Offset 0x0693 - PCIe ASPM programming will happen in relation to the Oprom
+ This option is specifically needed for ASPM configuration in 2LM feature
+ 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto
+**/
+ UINT8 Peg3Aspm;
+
+/** Offset 0x0694 - MFVC WRR VC Arbitration
+ 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES
+ 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES
+**/
+ UINT8 MfvcWrrArb;
+
+/** Offset 0x0695 - BZM Support
+ 1: enable, 0: disable(Default), Enable/disable setting for Boot-time Zero Memory support
+ $EN_DIS
+**/
+ UINT8 BzmSupport;
+
+/** Offset 0x0696 - VcId_7_0 values
+ Select VC ID for arbitration
+**/
+ UINT8 VcId_7_0[16];
+
+/** Offset 0x06A6 - Set Hw Parameters enable/disable
+ 1: enable, 0: disable, Enable/disable setting of HW parameters
+ $EN_DIS
+**/
+ UINT8 SetHwParameters;
+
+/** Offset 0x06A7
+**/
+ UINT8 UnusedUpdSpace19;
+
+/** Offset 0x06A8 - LTR L1.2 Threshold Value
+ LTR L1.2 Threshold Value
+**/
+ UINT16 Ltr_L1D2_ThVal;
+
+/** Offset 0x06AA - LTR L1.2 Threshold Scale
+ LTR L1.2 Threshold Scale
+**/
+ UINT8 Ltr_L1D2_ThScale;
+
+/** Offset 0x06AB - system power state
+ system power state indicates the platform power state
+**/
+ UINT8 SysPwrState;
+
+/** Offset 0x06AC - Media Death Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Media Death Notification
+ $EN_DIS
+**/
+ UINT8 MediaDeathNotification;
+
+/** Offset 0x06AD - Health Log Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Health Log Notification
+ $EN_DIS
+**/
+ UINT8 HealthLogNotification;
+
+/** Offset 0x06AE - Temp crosses below TempThrottle Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification
+ $EN_DIS
+**/
+ UINT8 TempBelowThrottleNotification;
+
+/** Offset 0x06AF - Temp crosses above TempThrottle Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification
+ $EN_DIS
+**/
+ UINT8 TempAboveThrottleNotification;
+
+/** Offset 0x06B0 - Missing Commit Bit Notification Enable/Disable
+ 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification
+ $EN_DIS
+**/
+ UINT8 MissingCommitBitNotification;
+
+/** Offset 0x06B1 - NVMeHoldDisableBit
+ 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit
+ $EN_DIS
+**/
+ UINT8 NVMeHoldDisableBit;
+
+/** Offset 0x06B2 - Ddr4OneDpc
+ DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+ or on both (default)
+ 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
+**/
+ UINT8 Ddr4OneDpc;
+
+/** Offset 0x06B3 - Ch Hash Override POR settings
+ Enable/Disable Override Channel Hash Support POR values
+ $EN_DIS
+**/
+ UINT8 ChHashOverride;
+
+/** Offset 0x06B4 - PDA Enumeration
+ Enables/Disable PDA Enumeration
+ $EN_DIS
+**/
+ UINT8 PDA;
+
+/** Offset 0x06B5 - DPin Policy
+ Set DPin Policy. Internal Only:All display ports are for internal only. External
+ First:All display ports are for external only, if there is no External DP-In presence
+ presents then IOM will use all ports internal only
+ 0: Internal Only, 1: External First
+**/
+ UINT8 DpInExternalEn;
+
+/** Offset 0x06B6 - DPin External Ports Number
+ Total number of External Gfx DpIn Port present on Board. Currently hardware wise
+ max 0x04 DpIn port supported, however DpIn module can handle upto 0x08 DpIn ports
+**/
+ UINT8 NumberOfDpInPort;
+
+/** Offset 0x06B7 - DPin External Port Connect Map
+ Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port.
+**/
+ UINT8 DpInPortConnectMap;
+
+/** Offset 0x06B8 - Command Pins Mapping
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
+**/
+ UINT8 Lp5CccConfig[4];
+
+/** Offset 0x06BC - Command Pins Mirrored
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+**/
+ UINT32 CmdMirror[1];
+
+/** Offset 0x06C0 - CPU BCLK SSC Enable
+ Enable/Disable CPU BCLK Spread Spectrum. Default is Enabled.
+ $EN_DIS
+**/
+ UINT8 CpuBclkSpread;
+
+/** Offset 0x06C1 - McParity
+ CMI/MC Parity Control
+ $EN_DIS
+**/
+ UINT8 McParity;
+
+/** Offset 0x06C2 - Vddq Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 VddqVoltageOverride;
+
+/** Offset 0x06C4 - Extended Bank Hashing
+ Eanble/Disable ExtendedBankHashing
+ $EN_DIS
+**/
+ UINT8 ExtendedBankHashing;
+
+/** Offset 0x06C5 - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x06C6 - Generate BIOS Data ACPI Table
+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+ $EN_DIS
+**/
+ UINT8 BdatEnable;
+
+/** Offset 0x06C7 - Detect External Graphics device for LegacyOpROM
+ Detect and report if external graphics device only support LegacyOpROM or not (to
+ support CSM auto-enable). Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 ScanExtGfxForLegacyOpRom;
+
+/** Offset 0x06C8 - Lock PCU Thermal Management registers
+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 LockPTMregs;
+
+/** Offset 0x06C9 - Rsvd
+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+ peak values unmodified
+ $EN_DIS
+**/
+ UINT8 PegGen3Rsvd;
+
+/** Offset 0x06CA - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x06CB - BdatTestType
+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+ 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+ UINT8 BdatTestType;
+
+/** Offset 0x06CC - PMR Size
+ Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
+**/
+ UINT32 DmaBufferSize;
+
+/** Offset 0x06D0 - VT-d/IOMMU Boot Policy
+ BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
+**/
+ UINT8 PreBootDmaMask;
+
+/** Offset 0x06D1 - Enable/Disable DMI GEN3 Hardware Eq
+ Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default):
+ Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiHweq;
+
+/** Offset 0x06D2 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass
+ CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
+ Enable Phase 23 Bypass
+ $EN_DIS
+**/
+ UINT8 Gen3EqPhase23Bypass;
+
+/** Offset 0x06D3 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass
+ CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
+ Enable Phase 3 Bypass
+ $EN_DIS
+**/
+ UINT8 Gen3EqPhase3Bypass;
+
+/** Offset 0x06D4 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+ Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
+ Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter
+ Coefficient Override
+ $EN_DIS
+**/
+ UINT8 Gen3LtcoEnable;
+
+/** Offset 0x06D5 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+ Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+ Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote
+ Transmitter Coefficient/Preset Override
+ $EN_DIS
+**/
+ UINT8 Gen3RtcoRtpoEnable;
+
+/** Offset 0x06D6 - DMI Gen3 Transmitter Pre-Cursor Coefficient
+ Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+ 2 is default for each lane
+**/
+ UINT8 DmiGen3Ltcpre[8];
+
+/** Offset 0x06DE - DMI Gen3 Transmitter Post-Cursor Coefficient
+ Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
+ for each lane
+**/
+ UINT8 DmiGen3Ltcpo[8];
+
+/** Offset 0x06E6 - PCIE Hw Eq Gen3 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuDmiHwEqGen3CoeffListCm[8];
+
+/** Offset 0x06EE - PCIE Hw Eq Gen3 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuDmiHwEqGen3CoeffListCp[8];
+
+/** Offset 0x06F6 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
+ Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
+ Manual(0x1): Enable DmiGen3DsPresetEnable
+ $EN_DIS
+**/
+ UINT8 DmiGen3DsPresetEnable;
+
+/** Offset 0x06F7 - DMI Gen3 Root port preset Rx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
+ for each lane
+**/
+ UINT8 DmiGen3DsPortRxPreset[8];
+
+/** Offset 0x06FF - DMI Gen3 Root port preset Tx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
+ for each lane
+**/
+ UINT8 DmiGen3DsPortTxPreset[8];
+
+/** Offset 0x0707 - Program DMI GEN3 Extended number of VC
+ (DEPRECATED)
+**/
+ UINT8 DmiGen3MultiVC;
+
+/** Offset 0x0708 - Enable/Disable DMI GEN3 DmiGen3Vc1Control
+ (DEPRECATED)
+ $EN_DIS
+**/
+ UINT8 DmiGen3Vc1Control;
+
+/** Offset 0x0709 - Enable/Disable DMI GEN3 DmiGen3VcMControl
+ (DEPRECATED)
+ $EN_DIS
+**/
+ UINT8 DmiGen3VcMControl;
+
+/** Offset 0x070A - DMI Secure Register Lock:{Combo
+ (DEPRECATED)
+ 0:Disable, 1:Enable
+**/
+ UINT8 DmiSrl;
+
+/** Offset 0x070B - DMI Scramble Enable:{Combo
+ (DEPRECATED)
+ 0:Disable, 1:Enable
+**/
+ UINT8 DmiScramble;
+
+/** Offset 0x070C - DMI Max Payload Size:{Combo
+ (DEPRECATED)
+ 0:Auto, 1:128 TLP, 2:256 TLP
+**/
+ UINT8 DmiMaxPayload;
+
+/** Offset 0x070D - DPin Dynamic Switch Policy
+ Dynamic one-time switch from iGFx to dGFx after boot to OS
+ 0: Disble, 1: Enable
+**/
+ UINT8 DPinDynamicSwitch;
+
+/** Offset 0x070E - Delay before sending commn
+ Delay before sending dynamic one-time switch cmd to IOM, ACPI BIOS consumes this
+ value and proceed delay when _DSM is invoked: 0=Minimal, 5000=Maximum, default
+ is 0 second
+**/
+ UINT16 DPinDynamicSwitchDelay0;
+
+/** Offset 0x0710 - Delay before IOM de-assert HPD
+ Delay before IOM de-assert HPD, ACPI BIOS passes this value to IOM when sending
+ dynamic one-time switch command: 1000=Minimal, 5000=Maximum, default is 1000 = 1 second
+**/
+ UINT16 DPinDynamicSwitchDelay1;
+
+/** Offset 0x0712 - SaPreMemTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPreMemTestRsvd[28];
+
+/** Offset 0x072E - TotalFlashSize
+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+ UINT16 TotalFlashSize;
+
+/** Offset 0x0730 - BiosSize
+ The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
+ 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
+ Range) so that a BIOS Update Script can be stored in the DPR.
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x0732 - SecurityTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SecurityTestRsvd[12];
+
+/** Offset 0x073E - Smbus dynamic power gating
+ Disable or Enable Smbus dynamic power gating.
+ $EN_DIS
+**/
+ UINT8 SmbusDynamicPowerGating;
+
+/** Offset 0x073F - Disable and Lock Watch Dog Register
+ Set 1 to clear WDT status, then disable and lock WDT registers.
+ $EN_DIS
+**/
+ UINT8 WdtDisableAndLock;
+
+/** Offset 0x0740 - SMBUS SPD Write Disable
+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+ Disable bit. For security recommendations, SPD write disable bit must be set.
+ $EN_DIS
+**/
+ UINT8 SmbusSpdWriteDisable;
+
+/** Offset 0x0741 - VC Type
+ Virtual Channel Type Select: 0: VC0, 1: VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 PchHdaVcType;
+
+/** Offset 0x0742 - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
+
+/** Offset 0x0743 - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x0744 - Enable HDA SDI lanes
+ Enable/disable HDA SDI lanes.
+**/
+ UINT8 PchHdaSdiEnable[2];
+
+/** Offset 0x0746 - HDA Power/Clock Gating (PGD/CGD)
+ Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
+ FORCE_ENABLE, 2: FORCE_DISABLE.
+ 0: POR, 1: Force Enable, 2: Force Disable
+**/
+ UINT8 PchHdaTestPowerClockGating;
+
+/** Offset 0x0747 - Enable HD Audio DMIC_N Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+ UINT8 PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x0749
+**/
+ UINT8 UnusedUpdSpace20[3];
+
+/** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number)
+ Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x0754 - DMIC ClkB Pin Muxing
+ Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
+
+/** Offset 0x075C - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x075D
+**/
+ UINT8 UnusedUpdSpace21[3];
+
+/** Offset 0x0760 - DMIC Data Pin Muxing
+ Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*
+**/
+ UINT32 PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x0768 - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+ UINT8 PchHdaAudioLinkSspEnable[6];
+
+/** Offset 0x076E - Enable HD Audio SoundWire#N Link
+ Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+ UINT8 PchHdaAudioLinkSndwEnable[4];
+
+/** Offset 0x0772 - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x0773 - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T(Default), 4: 16T
+ 0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x0774 - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x0775 - Force ME DID Init Status
+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+ ME DID init stat value
+ $EN_DIS
+**/
+ UINT8 DidInitStat;
+
+/** Offset 0x0776 - CPU Replaced Polling Disable
+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+ $EN_DIS
+**/
+ UINT8 DisableCpuReplacedPolling;
+
+/** Offset 0x0777 - ME DID Message
+ (DEPRECATED)Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable
+ will prevent the DID message from being sent)
+ $EN_DIS
+**/
+ UINT8 SendDidMsg;
+
+/** Offset 0x0778 - Check HECI message before send
+ Test, 0: disable, 1: enable, Enable/Disable message check.
+ $EN_DIS
+**/
+ UINT8 DisableMessageCheck;
+
+/** Offset 0x0779 - Skip MBP HOB
+ Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
+ $EN_DIS
+**/
+ UINT8 SkipMbpHob;
+
+/** Offset 0x077A - HECI2 Interface Communication
+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+ $EN_DIS
+**/
+ UINT8 HeciCommunication2;
+
+/** Offset 0x077B - Enable KT device
+ Test, 0: disable, 1: enable, Enable or Disable KT device.
+ $EN_DIS
+**/
+ UINT8 KtDeviceEnable;
+
+/** Offset 0x077C - Hybrid Graphics GPIO information for PEG 1
+ Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie1Rtd3Gpio[24];
+
+/** Offset 0x07DC - Hybrid Graphics GPIO information for PEG 2
+ Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie2Rtd3Gpio[24];
+
+/** Offset 0x083C - Hybrid Graphics GPIO information for PEG 3
+ Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
+**/
+ UINT32 CpuPcie3Rtd3Gpio[24];
+
+/** Offset 0x089C - Skip CPU replacement check
+ Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+ $EN_DIS
+**/
+ UINT8 SkipCpuReplacementCheck;
+
+/** Offset 0x089D - PCI Express Dekel Workaround
+ Select the 1 to 9 for Dekel registers endpoint programming: 1=Minimal, 9=Maximum,
+ default is 2
+**/
+ UINT8 CpuPcieRpDekelSquelchWa;
+
+/** Offset 0x089E - Serial Io Uart Debug Mode
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartDebugMode;
+
+/** Offset 0x089F
+**/
+ UINT8 UnusedUpdSpace22;
+
+/** Offset 0x08A0 - SerialIoUartDebugRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugRxPinMux;
+
+/** Offset 0x08A4 - SerialIoUartDebugTxPinMux - FSPM
+ Select TX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugTxPinMux;
+
+/** Offset 0x08A8 - SerialIoUartDebugRtsPinMux - FSPM
+ Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugRtsPinMux;
+
+/** Offset 0x08AC - SerialIoUartDebugCtsPinMux - FSPM
+ Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugCtsPinMux;
+
+/** Offset 0x08B0 - Avx2 Voltage Guardband Scaling Factor
+ AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
+ 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+ UINT8 Avx2VoltageScaleFactor;
+
+/** Offset 0x08B1 - Avx512 Voltage Guardband Scaling Factor
+ AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
+ in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+ UINT8 Avx512VoltageScaleFactor;
+
+/** Offset 0x08B2 - Lane Used of CSI port
+ Lane Used of each CSI port
+ 1:x1, 2:x2, 3:x3, 4:x4, 8:x8
+**/
+ UINT8 IpuLaneUsed[8];
+
+/** Offset 0x08BA - Lane Used of CSI port
+ Speed of each CSI port
+ 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps
+**/
+ UINT8 CsiSpeed[8];
+
+/** Offset 0x08C2 - DPmem Support
+ 1: enable, 0: disable(Default), Enable/disable setting for Dynamic Persistent Memory support
+ $EN_DIS
+**/
+ UINT8 DpmemSupport;
+
+/** Offset 0x08C3 - Core VF Point Offset Mode
+ Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes;
+ 0: Legacy; 1: Selection.
+ 0:Legacy, 1:Selection
+**/
+ UINT8 CoreVfPointOffsetMode;
+
+/** Offset 0x08C4 - Core VF Point Offset
+ Array used to specifies the Offset Voltage applied to the each selected Core VF
+ Point. This voltage is specified in millivolts.
+**/
+ UINT16 CoreVfPointOffset[15];
+
+/** Offset 0x08E2 - Core VF Point Offset Prefix
+ Sets the CoreVfPointOffset value as positive or negative for corresponding core
+ VF Point; 0: Positive ; 1: Negative.
+ 0:Positive, 1:Negative
+**/
+ UINT8 CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x08F1 - Core VF Point Ratio
+ Array for the each selected Core VF Point to display the ration.
+**/
+ UINT8 CoreVfPointRatio[15];
+
+/** Offset 0x0900 - Core VF Point Count
+ Number of supported Core Voltage & Frequency Point Offset
+**/
+ UINT8 CoreVfPointCount;
+
+/** Offset 0x0901 - Enable CPU CrashLog GPRs dump
+ Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only
+ disable Smm GPRs dump
+ 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
+**/
+ UINT8 CrashLogGprs;
+
+/** Offset 0x0902
+**/
+ UINT8 UnusedUpdSpace23[2];
+
+/** Offset 0x0904 - Bitmask of disable cores
+ Core mask is a bitwise indication of which core should be disabled. 0x00=Default;
+ Bit 0 - core 0, bit 7 - core 7.
+**/
+ UINT32 DisableCoreMask;
+
+/** Offset 0x0908 - REFRESH_PANIC_WM
+ @deprecated - Not used and has no effect, Please use RefreshWm
+**/
+ UINT8 RefreshPanicWm;
+
+/** Offset 0x0909 - REFRESH_HP_WM
+ @deprecated - Not used and has no effect, Please use RefreshWm
+**/
+ UINT8 RefreshHpWm;
+
+/** Offset 0x090A - Support Unlimited ICCMAX
+ Support Unlimited ICCMAX more than maximum value 255.75A; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 UnlimitedIccMax;
+
+/** Offset 0x090B - Per Core Max Ratio override
+ Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
+ favored core ratio to each Core. 0: Disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PerCoreRatioOverride;
+
+/** Offset 0x090C - Per Core Current Max Ratio
+ Array for the Per Core Max Ratio
+**/
+ UINT8 PerCoreRatio[10];
+
+/** Offset 0x0916 - Margin Limit Check
+ Margin Limit Check. Choose level of margin check
+ 0:Disable, 1:L1, 2:L2, 3:Both
+**/
+ UINT8 MarginLimitCheck;
+
+/** Offset 0x0917
+**/
+ UINT8 UnusedUpdSpace24;
+
+/** Offset 0x0918 - Margin Limit L2
+ % of L1 check for margin limit check
+**/
+ UINT16 MarginLimitL2;
+
+/** Offset 0x091A - Iotg Pll SscEn
+ Enable or disable CPU SSC. 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 IotgPllSscEn;
+
+/** Offset 0x091B - GPIO Override
+ Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+ before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level
+ 2 - skips GpioSetNativePadByFunction and GpioSetPadMode
+**/
+ UINT8 GpioOverride;
+
+/** Offset 0x091C - Write0 enabling
+ Enable/Disable Write0
+ $EN_DIS
+**/
+ UINT8 WRITE0;
+
+/** Offset 0x091D
+**/
+ UINT8 UnusedUpdSpace25[3];
+
+/** Offset 0x0920
+**/
+ UINT32 VccInVoltageOverride;
+
+/** Offset 0x0924 - Dynamic Memory Timings Changes
+ Dynamic Memory Timings Changes; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 DynamicMemoryChange;
+
+/** Offset 0x0925 - IbeccErrorInj
+ In-Band ECC Error Injection NOTE: For Debug or Development purposes only! Disable
+ this option for production systems.
+ $EN_DIS
+**/
+ UINT8 IbeccErrorInj;
+
+/** Offset 0x0926 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
+ Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable,
+ Manual(0x1): Enable DmiGen3UsPresetEnable
+ $EN_DIS
+**/
+ UINT8 DmiGen3UsPresetEnable;
+
+/** Offset 0x0927 - DMI Gen3 Root port preset Rx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
+ for each lane
+**/
+ UINT8 DmiGen3UsPortRxPreset[8];
+
+/** Offset 0x092F - DMI Gen3 Root port preset Tx values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
+ for each lane
+**/
+ UINT8 DmiGen3UsPortTxPreset[8];
+
+/** Offset 0x0937 - BCLK Frequency Source
+ Clock source of BCLK OC frequency, 0:CPU BCLK, 1:PCH BCLK, 2:External CLK
+ 0:CPU BCLK, 1:PCH BCLK, 2:External CLK
+**/
+ UINT8 BclkSource;
+
+/** Offset 0x0938 - CPU BCLK OC Frequency
+ CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0
+ - Auto. Range is 8000-50000 (10KHz).
+**/
+ UINT32 CpuBclkOcFrequency;
+
+/** Offset 0x093C - Ring CCF Auto Gv Disable Down
+ Ring CCF Auto Gv Disable Down, 0: Disabled, 1:Fused default
+ 0:Disabled, 1:Fused default
+**/
+ UINT8 RingCcfAutoGvDisable;
+
+/** Offset 0x093D - SA/Uncore voltage mode
+ SA/Uncore voltage mode; 0: Adaptive; 1: Override.
+ $EN_DIS
+**/
+ UINT8 SaVoltageMode;
+
+/** Offset 0x093E - SA/Uncore Voltage Override
+ The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
+ mode. Valid Range 0 to 2000
+**/
+ UINT16 SaVoltageOverride;
+
+/** Offset 0x0940 - SA/Uncore Extra Turbo voltage
+ Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 SaExtraTurboVoltage;
+
+/** Offset 0x0942 - DdrMemoryDown
+ DDR Memory Down Support.
+ $EN_DIS
+**/
+ UINT8 DdrMemoryDown;
+
+/** Offset 0x0943
+**/
+ UINT8 UnusedUpdSpace26;
+
+/** Offset 0x0944 - The VccIn Max Voltage Limit
+ This will override maximum VCCIN voltage limit to the voltage value specified. 0
+ - no override Valid Range 0 to 3000mV
+**/
+ UINT16 VccInMaxLimit;
+
+/** Offset 0x0946 - VccIO Voltage Override
+ This will override VccIO output voltage level to the voltage value specified. Valid
+ Range 0 to 2000
+**/
+ UINT16 VccIoVoltageOverride;
+
+/** Offset 0x0948 - Boost VRef Voltage
+ Default: 0: 0.7V 1: 1.0V to support the high frequencies needed for BCLK OC.
+ 0: 0.7V , 1:1.0V
+**/
+ UINT8 BoostRefVoltage;
+
+/** Offset 0x0949 - Pcie Ref Pll SSC
+ Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%,
+ 0x5: 0.5%, 0xFE: Disable, 0xFF: Auto
+**/
+ UINT8 PcieRefPllSsc;
+
+/** Offset 0x094A - Refresh Watermarks
+ Refresh Watermark, High, Low
+ 1:Enable Refresh Watermark High (Default), 0:Enable Refresh Watermark Low
+**/
+ UINT8 RefreshWm;
+
+/** Offset 0x094B
+**/
+ UINT8 UnusedUpdSpace27[4];
+
+/** Offset 0x094F
+**/
+ UINT8 ReservedFspmUpd2[1];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0950
+**/
+ UINT8 UnusedUpdSpace28[6];
+
+/** Offset 0x0956
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3060/FSP/Include/FspsUpd.h b/models/gaze16-3060/FSP/Include/FspsUpd.h
new file mode 100644
index 0000000..3843c11
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FspsUpd.h
@@ -0,0 +1,4203 @@
+/** @file FspsUpd.h
+
+ @copyright
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - Logo Pointer
+ Points to PEI Display Logo Image
+**/
+ UINT32 LogoPtr;
+
+/** Offset 0x0024 - Logo Size
+ Size of PEI Display Logo Image
+**/
+ UINT32 LogoSize;
+
+/** Offset 0x0028 - Blt Buffer Address
+ Address of Blt buffer
+**/
+ UINT32 BltBufferAddress;
+
+/** Offset 0x002C - Blt Buffer Size
+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+**/
+ UINT32 BltBufferSize;
+
+/** Offset 0x0030 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x0034 - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x0035 - Show SPI controller
+ Enable/disable to show SPI controller.
+ $EN_DIS
+**/
+ UINT8 ShowSpiController;
+
+/** Offset 0x0036
+**/
+ UINT8 UnusedUpdSpace0[2];
+
+/** Offset 0x0038 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x003C - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0040 - Turbo Mode
+ Enable/Disable Turbo mode. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 TurboMode;
+
+/** Offset 0x0041 - Enable SATA SALP Support
+ Enable/disable SATA Aggressive Link Power Management.
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0042 - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+ and so on.
+**/
+ UINT8 SataPortsEnable[8];
+
+/** Offset 0x004A - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+ port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlp[8];
+
+/** Offset 0x0052 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x0062 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x006C - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x006D
+**/
+ UINT8 UnusedUpdSpace1[3];
+
+/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+ UINT32 DevIntConfigPtr;
+
+/** Offset 0x0074 - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
+**/
+ UINT8 NumOfDevIntConfig;
+
+/** Offset 0x0075 - PIRQx to IRQx Map Config
+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
+ 8259 PCI mode.
+**/
+ UINT8 PxRcConfig[8];
+
+/** Offset 0x007D - Select GPIO IRQ Route
+ GPIO IRQ Select. The valid value is 14 or 15.
+**/
+ UINT8 GpioIrqRoute;
+
+/** Offset 0x007E - Select SciIrqSelect
+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+ UINT8 SciIrqSelect;
+
+/** Offset 0x007F - Select TcoIrqSelect
+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+ UINT8 TcoIrqSelect;
+
+/** Offset 0x0080 - Enable/Disable Tco IRQ
+ Enable/disable TCO IRQ
+ $EN_DIS
+**/
+ UINT8 TcoIrqEnable;
+
+/** Offset 0x0081 - PCH HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ UINT8 PchHdaVerbTableEntryNum;
+
+/** Offset 0x0082
+**/
+ UINT8 UnusedUpdSpace2[2];
+
+/** Offset 0x0084 - PCH HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ UINT32 PchHdaVerbTablePtr;
+
+/** Offset 0x0088 - PCH HDA Codec Sx Wake Capability
+ Capability to detect wake initiated by a codec in Sx
+**/
+ UINT8 PchHdaCodecSxWakeCapability;
+
+/** Offset 0x0089 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ UINT8 SataEnable;
+
+/** Offset 0x008A - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x008B - SPIn Device Mode
+ Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+ modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
+**/
+ UINT8 SerialIoSpiMode[7];
+
+/** Offset 0x0092 - SPI Chip Select Polarity
+ Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
+ 1:SerialIoSpiCsActiveHigh
+**/
+ UINT8 SerialIoSpiCsPolarity[14];
+
+/** Offset 0x00A0 - SPI Chip Select Enable
+ 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+ UINT8 SerialIoSpiCsEnable[14];
+
+/** Offset 0x00AE - SPIn Default Chip Select Output
+ Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
+ options: 0:CS0, 1:CS1
+**/
+ UINT8 SerialIoSpiDefaultCsOutput[7];
+
+/** Offset 0x00B5 - SPIn Default Chip Select Mode HW/SW
+ Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+ SPI1, ... Available options: 0:HW, 1:SW
+**/
+ UINT8 SerialIoSpiCsMode[7];
+
+/** Offset 0x00BC - SPIn Default Chip Select State Low/High
+ Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+ Available options: 0:Low, 1:High
+**/
+ UINT8 SerialIoSpiCsState[7];
+
+/** Offset 0x00C3 - UARTn Device Mode
+ Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+ modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartMode[7];
+
+/** Offset 0x00CA
+**/
+ UINT8 UnusedUpdSpace3[2];
+
+/** Offset 0x00CC - Default BaudRate for each Serial IO UART
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 SerialIoUartBaudRate[7];
+
+/** Offset 0x00E8 - Default ParityType for each Serial IO UART
+ Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartParity[7];
+
+/** Offset 0x00EF - Default DataBits for each Serial IO UART
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 SerialIoUartDataBits[7];
+
+/** Offset 0x00F6 - Default StopBits for each Serial IO UART
+ Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+ TwoStopBits
+**/
+ UINT8 SerialIoUartStopBits[7];
+
+/** Offset 0x00FD - Power Gating mode for each Serial IO UART that works in COM mode
+ Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+ UINT8 SerialIoUartPowerGating[7];
+
+/** Offset 0x0104 - Enable Dma for each Serial IO UART that supports it
+ Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+ UINT8 SerialIoUartDmaEnable[7];
+
+/** Offset 0x010B - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS lines.
+**/
+ UINT8 SerialIoUartAutoFlow[7];
+
+/** Offset 0x0112
+**/
+ UINT8 UnusedUpdSpace4[2];
+
+/** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0130 - SerialIoUartCtsPinMuxPolicy
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartCtsPinMuxPolicy[7];
+
+/** Offset 0x014C - SerialIoUartRxPinMuxPolicy
+ Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+ possible values.
+**/
+ UINT32 SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x0168 - SerialIoUartTxPinMuxPolicy
+ Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+ possible values.
+**/
+ UINT32 SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x0184 - UART Number For Debug Purpose
+ UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
+ 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
+ for debug purpose.
+ 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
+**/
+ UINT8 SerialIoDebugUartNumber;
+
+/** Offset 0x0185 - Serial IO UART DBG2 table
+ Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable;
+ 1: Enable.
+**/
+ UINT8 SerialIoUartDbg2[7];
+
+/** Offset 0x018C - I2Cn Device Mode
+ Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+ modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+ UINT8 SerialIoI2cMode[8];
+
+/** Offset 0x0194 - Serial IO I2C SDA Pin Muxing
+ Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x01B4 - Serial IO I2C SCL Pin Muxing
+ Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x01D4 - PCH SerialIo I2C Pads Termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+**/
+ UINT8 PchSerialIoI2cPadsTermination[8];
+
+/** Offset 0x01DC - ISH GP GPIO Pin Muxing
+ Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
+**/
+ UINT32 IshGpGpioPinMuxing[8];
+
+/** Offset 0x01FC - ISH UART Rx Pin Muxing
+ Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
+**/
+ UINT32 IshUartRxPinMuxing[3];
+
+/** Offset 0x0208 - ISH UART Tx Pin Muxing
+ Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
+**/
+ UINT32 IshUartTxPinMuxing[3];
+
+/** Offset 0x0214 - ISH UART Rts Pin Muxing
+ Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
+**/
+ UINT32 IshUartRtsPinMuxing[3];
+
+/** Offset 0x0220 - ISH UART Rts Pin Muxing
+ Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
+**/
+ UINT32 IshUartCtsPinMuxing[3];
+
+/** Offset 0x022C - ISH I2C SDA Pin Muxing
+ Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
+**/
+ UINT32 IshI2cSdaPinMuxing[3];
+
+/** Offset 0x0238 - ISH I2C SCL Pin Muxing
+ Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
+**/
+ UINT32 IshI2cSclPinMuxing[3];
+
+/** Offset 0x0244 - ISH SPI MOSI Pin Muxing
+ Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
+**/
+ UINT32 IshSpiMosiPinMuxing[2];
+
+/** Offset 0x024C - ISH SPI MISO Pin Muxing
+ Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
+**/
+ UINT32 IshSpiMisoPinMuxing[2];
+
+/** Offset 0x0254 - ISH SPI CLK Pin Muxing
+ Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
+**/
+ UINT32 IshSpiClkPinMuxing[2];
+
+/** Offset 0x025C - ISH SPI CS#N Pin Muxing
+ Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible
+ values. N-SPI number, 0-1.
+**/
+ UINT32 IshSpiCsPinMuxing[4];
+
+/** Offset 0x026C - ISH GP GPIO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
+ respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
+ 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31
+**/
+ UINT8 IshGpGpioPadTermination[8];
+
+/** Offset 0x0274 - ISH UART Rx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
+ Rx, and so on.
+**/
+ UINT8 IshUartRxPadTermination[3];
+
+/** Offset 0x0277 - ISH UART Tx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
+ Tx, and so on.
+**/
+ UINT8 IshUartTxPadTermination[3];
+
+/** Offset 0x027A - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
+ Rts, and so on.
+**/
+ UINT8 IshUartRtsPadTermination[3];
+
+/** Offset 0x027D - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
+ Cts, and so on.
+**/
+ UINT8 IshUartCtsPadTermination[3];
+
+/** Offset 0x0280 - ISH I2C SDA Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+ and so on.
+**/
+ UINT8 IshI2cSdaPadTermination[3];
+
+/** Offset 0x0283 - ISH I2C SCL Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+ and so on.
+**/
+ UINT8 IshI2cSclPadTermination[3];
+
+/** Offset 0x0286 - ISH SPI MOSI Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
+ Mosi, and so on.
+**/
+ UINT8 IshSpiMosiPadTermination[2];
+
+/** Offset 0x0288 - ISH SPI MISO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
+ Miso, and so on.
+**/
+ UINT8 IshSpiMisoPadTermination[2];
+
+/** Offset 0x028A - ISH SPI CLK Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
+ and so on.
+**/
+ UINT8 IshSpiClkPadTermination[2];
+
+/** Offset 0x028C - ISH SPI CS#N Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
+ respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
+ Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3
+**/
+ UINT8 IshSpiCsPadTermination[4];
+
+/** Offset 0x0290 - Enable PCH ISH SPI Cs#N pins assigned
+ Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
+ number: 0-1
+**/
+ UINT8 PchIshSpiCsEnable[4];
+
+/** Offset 0x0294 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2PhyPetxiset[16];
+
+/** Offset 0x02A4 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2PhyTxiset[16];
+
+/** Offset 0x02B4 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2PhyPredeemp[16];
+
+/** Offset 0x02C4 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2PhyPehalfbit[16];
+
+/** Offset 0x02D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x02DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x02E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x02F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default
+ = 00h. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x02FC
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
+
+/** Offset 0x0306
+**/
+ UINT8 PchUsb3HsioFilterSelNEnable[10];
+
+/** Offset 0x0310
+**/
+ UINT8 PchUsb3HsioFilterSelPEnable[10];
+
+/** Offset 0x031A
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
+
+/** Offset 0x0324
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
+
+/** Offset 0x032E
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
+
+/** Offset 0x0338
+**/
+ UINT8 PchUsb3HsioFilterSelN[10];
+
+/** Offset 0x0342
+**/
+ UINT8 PchUsb3HsioFilterSelP[10];
+
+/** Offset 0x034C - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x034D - Enable PCH TSN
+ Enable/disable TSN on the PCH.
+ $EN_DIS
+**/
+ UINT8 PchTsnEnable;
+
+/** Offset 0x034E - TSN Link Speed
+ Set TSN Link Speed.
+ 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
+**/
+ UINT8 PchTsnLinkSpeed;
+
+/** Offset 0x034F
+**/
+ UINT8 UnusedUpdSpace5;
+
+/** Offset 0x0350 - PCH TSN0 MAC Address High Bits
+ Set TSN0 MAC Address High.
+**/
+ UINT32 PchTsn0MacAddressHigh;
+
+/** Offset 0x0354 - PCH TSN0 MAC Address Low Bits
+ Set TSN0 MAC Address Low.
+**/
+ UINT32 PchTsn0MacAddressLow;
+
+/** Offset 0x0358 - PCIe PTM enable/disable
+ Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+ UINT8 PciePtm[24];
+
+/** Offset 0x0370 - PCIe DPC enable/disable
+ Enable/disable Downstream Port Containment for PCIE Root Ports.
+**/
+ UINT8 PcieDpc[24];
+
+/** Offset 0x0388 - PCIe DPC extensions enable/disable
+ Enable/disable Downstream Port Containment Extensions for PCIE Root Ports.
+**/
+ UINT8 PcieEdpc[24];
+
+/** Offset 0x03A0 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x03A1
+**/
+ UINT8 UnusedUpdSpace6[3];
+
+/** Offset 0x03A4 - Power button debounce configuration
+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+ UINT32 PmcPowerButtonDebounce;
+
+/** Offset 0x03A8 - PCH eSPI Master and Slave BME enabled
+ PCH eSPI Master and Slave BME enabled
+ $EN_DIS
+**/
+ UINT8 PchEspiBmeMasterSlaveEnabled;
+
+/** Offset 0x03A9 - PCH SATA use RST Legacy OROM
+ Use PCH SATA RST Legacy OROM when CSM is Enabled
+ $EN_DIS
+**/
+ UINT8 SataRstLegacyOrom;
+
+/** Offset 0x03AA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+ Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtV1p05RailEnabledStates;
+
+/** Offset 0x03AB - Mask to enable the platform configuration of external V1p05 VR rail
+ External V1P05 Rail Supported Configuration
+**/
+ UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
+
+/** Offset 0x03AC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtV1p05RailVoltage;
+
+/** Offset 0x03AE - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtV1p05RailIccMax;
+
+/** Offset 0x03AF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+ Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailEnabledStates;
+
+/** Offset 0x03B0 - Mask to enable the platform configuration of external Vnn VR rail
+ External Vnn Rail Supported Configuration
+**/
+ UINT8 PchFivrExtVnnRailSupportedVoltageStates;
+
+/** Offset 0x03B1
+**/
+ UINT8 UnusedUpdSpace7;
+
+/** Offset 0x03B2 - External Vnn Voltage Value that will be used in S0ix/Sx states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
+**/
+ UINT16 PchFivrExtVnnRailVoltage;
+
+/** Offset 0x03B4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailIccMax;
+
+/** Offset 0x03B5 - Mask to enable the usage of external Vnn VR rail in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
+ Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailSxEnabledStates;
+
+/** Offset 0x03B6 - External Vnn Voltage Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
+ (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtVnnRailSxVoltage;
+
+/** Offset 0x03B8 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailSxIccMax;
+
+/** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to low current mode voltage.
+**/
+ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x03BA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x03BB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
+
+/** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x03BE
+**/
+ UINT8 UnusedUpdSpace8[2];
+
+/** Offset 0x03C0 - Trace Hub Memory Base
+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
+ memory is configured properly.
+**/
+ UINT32 TraceHubMemBase;
+
+/** Offset 0x03C4 - PMC Debug Message Enable
+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
+ $EN_DIS
+**/
+ UINT8 PmcDbgMsgEn;
+
+/** Offset 0x03C5
+**/
+ UINT8 UnusedUpdSpace9[3];
+
+/** Offset 0x03C8 - Pointer of ChipsetInit Binary
+ ChipsetInit Binary Pointer.
+**/
+ UINT32 ChipsetInitBinPtr;
+
+/** Offset 0x03CC - Length of ChipsetInit Binary
+ ChipsetInit Binary Length.
+**/
+ UINT32 ChipsetInitBinLen;
+
+/** Offset 0x03D0 - FIVR Dynamic Power Management
+ Enable/Disable FIVR Dynamic Power Management.
+ $EN_DIS
+**/
+ UINT8 PchFivrDynPm;
+
+/** Offset 0x03D1
+**/
+ UINT8 UnusedUpdSpace10;
+
+/** Offset 0x03D2 - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtV1p05RailIccMaximum;
+
+/** Offset 0x03D4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailIccMaximum;
+
+/** Offset 0x03D6 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailSxIccMaximum;
+
+/** Offset 0x03D8 - PCH eSPI Link Configuration Lock (SBLCL)
+ Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves
+ addresseses from range 0x0 - 0x7FF
+ $EN_DIS
+**/
+ UINT8 PchEspiLockLinkConfiguration;
+
+/** Offset 0x03D9 - Extented BIOS Direct Read Decode enable
+ Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
+ 0: disabled (default), 1: enabled
+ $EN_DIS
+**/
+ UINT8 PchSpiExtendedBiosDecodeRangeEnable;
+
+/** Offset 0x03DA - Enforce Enhanced Debug Mode
+ Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 EnforceEDebugMode;
+
+/** Offset 0x03DB - PchPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 PchPostMemRsvd[1];
+
+/** Offset 0x03DC - Extended BIOS Direct Read Decode Range base
+ Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
+**/
+ UINT32 PchSpiExtendedBiosDecodeRangeBase;
+
+/** Offset 0x03E0 - Extended BIOS Direct Read Decode Range limit
+ Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
+**/
+ UINT32 PchSpiExtendedBiosDecodeRangeLimit;
+
+/** Offset 0x03E4 - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x03E5 - CNVi BT Core
+ Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtCore;
+
+/** Offset 0x03E6 - CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtAudioOffload;
+
+/** Offset 0x03E7
+**/
+ UINT8 UnusedUpdSpace11;
+
+/** Offset 0x03E8 - CNVi RF_RESET pin muxing
+ Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default)
+ or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+ UINT32 CnviRfResetPinMux;
+
+/** Offset 0x03EC - CNVi CLKREQ pin muxing
+ Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default)
+ or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in
+ GpioPins*.h.
+**/
+ UINT32 CnviClkreqPinMux;
+
+/** Offset 0x03F0 - Enable Host C10 reporting through eSPI
+ Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire.
+ $EN_DIS
+**/
+ UINT8 PchEspiHostC10ReportEnable;
+
+/** Offset 0x03F1 - PCH USB2 PHY Power Gating enable
+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+ Sus Well PG
+ $EN_DIS
+**/
+ UINT8 PmcUsb2PhySusPgEnable;
+
+/** Offset 0x03F2 - PCH USB OverCurrent mapping enable
+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+ mapping allow for NOA usage of OC pins
+ $EN_DIS
+**/
+ UINT8 PchUsbOverCurrentEnable;
+
+/** Offset 0x03F3 - Espi Lgmr Memory Range decode
+ This option enables or disables espi lgmr
+ $EN_DIS
+**/
+ UINT8 PchEspiLgmrEnable;
+
+/** Offset 0x03F4 - External V1P05 Control Ramp Timer value
+ Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtV1p05RailCtrlRampTmr;
+
+/** Offset 0x03F5 - External VNN Control Ramp Timer value
+ Hold off time to be used when changing the vnn_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtVnnRailCtrlRampTmr;
+
+/** Offset 0x03F6 - Set SATA DEVSLP GPIO Reset Config
+ Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
+ 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
+ for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlpResetConfig[8];
+
+/** Offset 0x03FE - HECI3 state
+ The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
+ DEPRECATED 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 Heci3Enabled;
+
+/** Offset 0x03FF - PCHHOT# pin
+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchHotEnable;
+
+/** Offset 0x0400 - SATA LED
+ SATA LED indicating SATA controller activity. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 SataLedEnable;
+
+/** Offset 0x0401 - VRAlert# Pin
+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmVrAlert;
+
+/** Offset 0x0402 - AMT Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+ $EN_DIS
+**/
+ UINT8 AmtEnabled;
+
+/** Offset 0x0403 - WatchDog Timer Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 WatchDogEnabled;
+
+/** Offset 0x0404 - Manageability Mode set by Mebx
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
+ $EN_DIS
+**/
+ UINT8 ManageabilityMode;
+
+/** Offset 0x0405 - PET Progress
+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
+ PET Events. Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 FwProgress;
+
+/** Offset 0x0406 - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+ Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtSolEnabled;
+
+/** Offset 0x0407
+**/
+ UINT8 UnusedUpdSpace12;
+
+/** Offset 0x0408 - OS Timer
+ 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerOs;
+
+/** Offset 0x040A - BIOS Timer
+ 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerBios;
+
+/** Offset 0x040C - Remote Assistance Trigger Availablilty
+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
+ $EN_DIS
+**/
+ UINT8 RemoteAssistance;
+
+/** Offset 0x040D - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtKvmEnabled;
+
+/** Offset 0x040E - Force MEBX execution
+ Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
+ $EN_DIS
+**/
+ UINT8 ForcMebxSyncUp;
+
+/** Offset 0x040F - PCH PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 PcieRpSlotImplemented[24];
+
+/** Offset 0x0427 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 PcieRpAcsEnabled[24];
+
+/** Offset 0x043F - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 PcieRpEnableCpm[24];
+
+/** Offset 0x0457
+**/
+ UINT8 UnusedUpdSpace13[1];
+
+/** Offset 0x0458 - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x0488 - ModPHY SUS Power Domain Dynamic Gating
+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+ PCH-H. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcModPhySusPgEnable;
+
+/** Offset 0x0489 - V1p05-PHY supply external FET control
+ Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05PhyExtFetControlEn;
+
+/** Offset 0x048A - V1p05-IS supply external FET control
+ Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05IsExtFetControlEn;
+
+/** Offset 0x048B - Enable/Disable PavpEnable
+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+ $EN_DIS
+**/
+ UINT8 PavpEnable;
+
+/** Offset 0x048C - CdClock Frequency selection
+ 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
+ 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+ 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
+ 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x048D - Enable/Disable PeiGraphicsPeimInit
+ Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+ Disable: FSP will NOT initialize the framebuffer.
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x048E - Enable D3 Hot in TCSS
+ This policy will enable/disable D3 hot support in IOM
+ $EN_DIS
+**/
+ UINT8 D3HotEnable;
+
+/** Offset 0x048F - Enable or disable GNA device
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 GnaEnable;
+
+/** Offset 0x0490 - TypeC port GPIO setting
+ GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Tgl
+ = TigerLake)
+**/
+ UINT32 IomTypeCPortPadCfg[8];
+
+/** Offset 0x04B0 - CPU USB3 Port Over Current Pin
+ Describe the specific over current pin number of USBC Port N.
+**/
+ UINT8 CpuUsb3OverCurrentPin[8];
+
+/** Offset 0x04B8 - Enable D3 Cold in TCSS
+ This policy will enable/disable D3 cold support in IOM
+ $EN_DIS
+**/
+ UINT8 D3ColdEnable;
+
+/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4
+ Enable/Disable PCIe tunneling for USB4, default is enable
+ $EN_DIS
+**/
+ UINT8 ITbtPcieTunnelingForUsb4;
+
+/** Offset 0x04BA - Enable/Disable SkipFspGop
+ Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
+ $EN_DIS
+**/
+ UINT8 SkipFspGop;
+
+/** Offset 0x04BB - TC State in TCSS
+ This TC C-State Limit in IOM
+**/
+ UINT8 TcCstateLimit;
+
+/** Offset 0x04BC - Disable TC code On USB Connect
+ Enable: Unsupported TC cold capability on Usb Connected, Disable(default): Supported
+ TC cold On Usb Connected
+ $EN_DIS
+**/
+ UINT8 DisableTccoldOnUsbConnected;
+
+/** Offset 0x04BD - Set Iom stay in TC cold seconds in TCSS
+ Set Iom stay in TC cold seconds in IOM
+**/
+ UINT8 IomStayInTCColdeSeconds;
+
+/** Offset 0x04BE - Set Iom before entering TC cold seconds in TCSS
+ Set Iom before entering TC cold seconds in IOM
+**/
+ UINT8 IomBeforeEnteringTCCodeSeconds;
+
+/** Offset 0x04BF - SaPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 SaPostMemRsvd[2];
+
+/** Offset 0x04C1 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 VmdEnable;
+
+/** Offset 0x04C2 - Enable VMD portA Support
+ Enable/disable to VMD portA Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortA;
+
+/** Offset 0x04C3 - Enable VMD portB Support
+ Enable/disable to VMD portB Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortB;
+
+/** Offset 0x04C4 - Enable VMD portC Support
+ Enable/disable to VMD portC Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortC;
+
+/** Offset 0x04C5 - Enable VMD portD Support
+ Enable/disable to VMD portD Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortD;
+
+/** Offset 0x04C6 - VMD Config Bar size
+ Set The VMD Config Bar Size.
+**/
+ UINT8 VmdCfgBarSize;
+
+/** Offset 0x04C7 - VMD Config Bar Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default)
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdCfgBarAttr;
+
+/** Offset 0x04C8 - VMD Mem Bar1 size
+ Set The VMD Mem Bar1 Size.
+**/
+ UINT8 VmdMemBarSize1;
+
+/** Offset 0x04C9 - VMD Mem Bar1 Attributes
+ 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar1Attr;
+
+/** Offset 0x04CA - VMD Mem Bar2 size
+ Set The VMD Mem Bar2 Size.
+**/
+ UINT8 VmdMemBarSize2;
+
+/** Offset 0x04CB - VMD Mem Bar2 Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar2Attr;
+
+/** Offset 0x04CC - Enable/Disable PMC-PD Solution
+ This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
+ $EN_DIS
+**/
+ UINT8 PmcPdEnable;
+
+/** Offset 0x04CD
+**/
+ UINT8 UnusedUpdSpace14;
+
+/** Offset 0x04CE - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x04D0 - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x04D2 - USB override in IOM
+ This policy will enable/disable USB Connect override in IOM
+ $EN_DIS
+**/
+ UINT8 UsbOverride;
+
+/** Offset 0x04D3 - TCSS USB Port Enable
+ Bits 0, 1, ... max Type C port control enables
+**/
+ UINT8 UsbTcPortEn;
+
+/** Offset 0x04D4 - ITBT Root Port Enable
+ ITBT Root Port Enable, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 ITbtPcieRootPortEn[4];
+
+/** Offset 0x04D8 - ITBTForcePowerOn Timeout value
+ ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
+ 100 = 100 ms.
+**/
+ UINT16 ITbtForcePowerOnTimeoutInMs;
+
+/** Offset 0x04DA - ITbtConnectTopology Timeout value
+ ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+ is 0-10000. 100 = 100 ms.
+**/
+ UINT16 ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x04DC - VCCST request for IOM
+ This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
+ $EN_DIS
+**/
+ UINT8 VccSt;
+
+/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable
+ Used by IOM FW to skip powering down the PHY at the end of disconnect flow
+ $EN_DIS
+**/
+ UINT8 Usb3ComplModeEnable;
+
+/** Offset 0x04DE - ITBT DMA LTR
+ TCSS DMA1, DMA2 LTR value
+**/
+ UINT16 ITbtDmaLtr[2];
+
+/** Offset 0x04E2 - Enable/Disable CrashLog
+ Deprecated. Move to PreMem
+ $EN_DIS
+**/
+ UINT8 DeprecatedCpuCrashLogEnable;
+
+/** Offset 0x04E3 - Enable/Disable PTM
+ This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+ $EN_DIS
+**/
+ UINT8 PtmEnabled[4];
+
+/** Offset 0x04E7 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 SaPcieItbtRpLtrEnable[4];
+
+/** Offset 0x04EB - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x04EF - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x04F3
+**/
+ UINT8 UnusedUpdSpace15[1];
+
+/** Offset 0x04F4 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x04FC - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0500 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0504 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x050C - Force LTR Override
+ Force LTR Override.
+**/
+ UINT8 SaPcieItbtRpForceLtrOverride[4];
+
+/** Offset 0x0510 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 SaPcieItbtRpLtrConfigLock[4];
+
+/** Offset 0x0514 - Advanced Encryption Standard (AES) feature
+ Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 AesEnable;
+
+/** Offset 0x0515 - Power State 3 enable/disable
+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.
+ For all VR Indexes
+**/
+ UINT8 Psi3Enable[5];
+
+/** Offset 0x051A - Power State 4 enable/disable
+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 Psi4Enable[5];
+
+/** Offset 0x051F
+**/
+ UINT8 UnusedUpdSpace16[1];
+
+/** Offset 0x0520 - Imon slope correction
+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+ Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes
+**/
+ UINT16 ImonSlope[5];
+
+/** Offset 0x052A - Imon offset correction
+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
+**/
+ UINT16 ImonOffset[5];
+
+/** Offset 0x0534 - Enable/Disable BIOS configuration of VR
+ Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes
+**/
+ UINT8 VrConfigEnable[5];
+
+/** Offset 0x0539 - Thermal Design Current enable/disable
+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1:
+ Enable.For all VR Indexes
+**/
+ UINT8 TdcEnable[5];
+
+/** Offset 0x053E - Thermal Design Current time window
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ DEPRECATED. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 -
+ 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Index
+**/
+ UINT8 TdcTimeWindow[5];
+
+/** Offset 0x0543 - Thermal Design Current Lock
+ PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 TdcLock[5];
+
+/** Offset 0x0548 - Platform Psys slope correction
+ PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in
+ 1/100 increment values. Range is 0-200. 125 = 1.25
+**/
+ UINT8 PsysSlope;
+
+/** Offset 0x0549
+**/
+ UINT8 PsysOffset;
+
+/** Offset 0x054A - Acoustic Noise Mitigation feature
+ Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 AcousticNoiseMitigation;
+
+/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. 0: False; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisable[5];
+
+/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains
+ Slew Rate configuration for Deep Package C States for VR domains based on Acoustic
+ Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRate[5];
+
+/** Offset 0x0555 - Enable multi phases silicon initialization
+ A switch to determine MultiPhaseSiInit will be executed or not
+ $EN_DIS
+**/
+ UINT8 EnableMultiPhaseSiliconInit;
+
+/** Offset 0x0556 - Thermal Design Current current limit
+ PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
+ Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes
+**/
+ UINT16 TdcCurrentLimit[5];
+
+/** Offset 0x0560 - AcLoadline
+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249. Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 AcLoadline[5];
+
+/** Offset 0x056A - DcLoadline
+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249.Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 DcLoadline[5];
+
+/** Offset 0x0574 - Power State 1 Threshold current
+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi1Threshold[5];
+
+/** Offset 0x057E - Power State 2 Threshold current
+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi2Threshold[5];
+
+/** Offset 0x0588 - Power State 3 Threshold current
+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi3Threshold[5];
+
+/** Offset 0x0592 - Icc Max limit
+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
+**/
+ UINT16 IccMax[5];
+
+/** Offset 0x059C - VR Voltage Limit
+ PCODE MMIO Mailbox: VR Voltage Limit. DEPRECATED, Range is 0-7999mV.
+**/
+ UINT16 VrVoltageLimit[5];
+
+/** Offset 0x05A6 - Enable VR specific mailbox command
+ VR specific mailbox commands. 00b - no VR specific command sent. 01b - A
+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
+ command sent for PS4 exit issue. 11b - Reserved.
+ $EN_DIS
+**/
+ UINT8 SendVrMbxCmd;
+
+/** Offset 0x05A7 - Reserved
+ Reserved
+**/
+ UINT8 Reserved2;
+
+/** Offset 0x05A8 - Enable or Disable TXT
+ Enable or Disable TXT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TxtEnable;
+
+/** Offset 0x05A9 - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. 0: Initialize; 1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x05AA - FIVR RFI Frequency
+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0:
+ Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
+ 0-1535 (Up to 153.5MHz) for 19MHz clock.
+**/
+ UINT16 FivrRfiFrequency;
+
+/** Offset 0x05AC - FIVR RFI Spread Spectrum
+ Set the Spread Spectrum Range. 1.5%; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%,
+ 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1%
+ = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+**/
+ UINT8 FivrSpreadSpectrum;
+
+/** Offset 0x05AD
+**/
+ UINT8 UnusedUpdSpace17[3];
+
+/** Offset 0x05B0 - CpuBistData
+ Pointer CPU BIST Data
+**/
+ UINT32 CpuBistData;
+
+/** Offset 0x05B4 - CpuMpPpi
+ Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+ If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+ See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+ UINT32 CpuMpPpi;
+
+/** Offset 0x05B8 - CpuMpHob
+ @deprecated This is not needed in current version of FSP.
+**/
+ UINT32 CpuMpHob;
+
+/** Offset 0x05BC - RFI Mitigation
+ Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1:
+ Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
+ $EN_DIS
+**/
+ UINT8 RfiMitigation;
+
+/** Offset 0x05BD - FIVR RFI Spread Spectrum Enable or disable
+ Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable
+**/
+ UINT8 FivrSpectrumEnable;
+
+/** Offset 0x05BE - Pre Wake Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled. Range 0-255 0.
+**/
+ UINT8 PreWake;
+
+/** Offset 0x05BF - Ramp Up Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 0.
+**/
+ UINT8 RampUp;
+
+/** Offset 0x05C0 - Ramp Down Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 0.
+**/
+ UINT8 RampDown;
+
+/** Offset 0x05C1
+**/
+ UINT8 CpuPostMemRsvd[11];
+
+/** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number
+ Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
+ flag is set) for PPIN Support
+ 0: Disable, 1: Enable, 2: Auto
+**/
+ UINT8 PpinSupport;
+
+/** Offset 0x05CD - Enable or Disable Minimum Voltage Override
+ Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 EnableMinVoltageOverride;
+
+/** Offset 0x05CE - Min Voltage for Runtime
+ PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride
+ = 1. Range 0 to 1999mV. 0: 0mV
+**/
+ UINT16 MinVoltageRuntime;
+
+/** Offset 0x05D0 - Base of memory region allocated for Processor Trace
+ Base address of memory region allocated for Processor Trace. Processor Trace requires
+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable
+**/
+ UINT64 ProcessorTraceMemBase;
+
+/** Offset 0x05D8 - Memory region allocation for Processor Trace
+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable
+**/
+ UINT32 ProcessorTraceMemLength;
+
+/** Offset 0x05DC - Min Voltage for C8
+ PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
+ 1. Range 0 to 1999mV. 0: 0mV
+**/
+ UINT16 MinVoltageC8;
+
+/** Offset 0x05DE - Platform Psys offset correction
+ PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000,
+ Range 0-63999. For an offset of 25.348, enter 25348.
+**/
+ UINT16 PsysOffset1;
+
+/** Offset 0x05E0 - Smbios Type4 Max Speed Override
+ Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
+ If this value is not zero, it dominates the field.
+**/
+ UINT16 SmbiosType4MaxSpeedOverride;
+
+/** Offset 0x05E2 - AvxDisable
+ Enable or Disable AVX Support.
+ 0: Enable, 1: Disable
+**/
+ UINT8 AvxDisable;
+
+/** Offset 0x05E3 - Avx3Disable
+ Enable or Disable AVX3 Support
+ 0: Enable, 1: Disable
+**/
+ UINT8 Avx3Disable;
+
+/** Offset 0x05E4 - ReservedCpuPostMemProduction
+ Reserved for CPU Post-Mem Production
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemProduction[4];
+
+/** Offset 0x05E8 - Enable Power Optimizer
+ Enable DMI Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 PchPwrOptEnable;
+
+/** Offset 0x05E9 - PCH Flash Protection Ranges Write Enble
+ Write or erase is blocked by hardware.
+**/
+ UINT8 PchWriteProtectionEnable[5];
+
+/** Offset 0x05EE - PCH Flash Protection Ranges Read Enble
+ Read is blocked by hardware.
+**/
+ UINT8 PchReadProtectionEnable[5];
+
+/** Offset 0x05F3
+**/
+ UINT8 UnusedUpdSpace18[1];
+
+/** Offset 0x05F4 - PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** Offset 0x05FE - PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** Offset 0x0608 - Enable Pme
+ Enable Azalia wake-on-ring.
+ $EN_DIS
+**/
+ UINT8 PchHdaPme;
+
+/** Offset 0x0609 - HD Audio Link Frequency
+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+ UINT8 PchHdaLinkFrequency;
+
+/** Offset 0x060A - PchPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 PchPostMemRsvd4[3];
+
+/** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned
+ Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiCs0Enable[1];
+
+/** Offset 0x060E - Enable PCH Io Apic Entry 24-119
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIoApicEntry24_119;
+
+/** Offset 0x060F - PCH Io Apic ID
+ This member determines IOAPIC ID. Default is 0x02.
+**/
+ UINT8 PchIoApicId;
+
+/** Offset 0x0610 - Enable PCH ISH SPI pins assigned
+ Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiEnable[1];
+
+/** Offset 0x0611 - Enable PCH ISH UART pins assigned
+ Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshUartEnable[2];
+
+/** Offset 0x0613 - Enable PCH ISH I2C pins assigned
+ Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshI2cEnable[3];
+
+/** Offset 0x0616 - Enable PCH ISH GP pins assigned
+ Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshGpEnable[8];
+
+/** Offset 0x061E - PCH ISH PDT Unlock Msg
+ 0: False; 1: True.
+ $EN_DIS
+**/
+ UINT8 PchIshPdtUnlock;
+
+/** Offset 0x061F - Enable PCH Lan LTR capabilty of PCH internal LAN
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchLanLtrEnable;
+
+/** Offset 0x0620 - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x0621 - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x0622 - RTC BIOS Interface Lock
+ Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
+ $EN_DIS
+**/
+ UINT8 RtcBiosInterfaceLock;
+
+/** Offset 0x0623 - RTC Cmos Memory Lock
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 RtcMemoryLock;
+
+/** Offset 0x0624 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[24];
+
+/** Offset 0x063C - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 PcieRpPmSci[24];
+
+/** Offset 0x0654 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 PcieRpTransmitterHalfSwing[24];
+
+/** Offset 0x066C - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[24];
+
+/** Offset 0x0684 - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[24];
+
+/** Offset 0x069C - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 PcieRpUnsupportedRequestReport[24];
+
+/** Offset 0x06B4 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpFatalErrorReport[24];
+
+/** Offset 0x06CC - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpNoFatalErrorReport[24];
+
+/** Offset 0x06E4 - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 PcieRpCorrectableErrorReport[24];
+
+/** Offset 0x06FC - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnFatalError[24];
+
+/** Offset 0x0714 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnNonFatalError[24];
+
+/** Offset 0x072C - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnCorrectableError[24];
+
+/** Offset 0x0744 - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[24];
+
+/** Offset 0x075C - Touch Host Controller Port 0 Assignment
+ Assign THC Port 0
+ 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
+**/
+ UINT8 ThcPort0Assignment;
+
+/** Offset 0x075D
+**/
+ UINT8 UnusedUpdSpace19[3];
+
+/** Offset 0x0760 - THC Port 0 Interrupt Pin Mux
+ Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer
+ to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
+**/
+ UINT32 ThcPort0InterruptPinMuxing;
+
+/** Offset 0x0764 - Touch Host Controller Port 1 Assignment
+ Assign THC Port 1
+ 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcPort1Assignment;
+
+/** Offset 0x0765 - Touch Host Controller Port 1 ReadFrequency
+ Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+ 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+**/
+ UINT8 ThcPort1ReadFrequency;
+
+/** Offset 0x0766 - Touch Host Controller Port 1 WriteFrequency
+ Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+ 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
+**/
+ UINT8 ThcPort1WriteFrequency;
+
+/** Offset 0x0767
+**/
+ UINT8 UnusedUpdSpace20;
+
+/** Offset 0x0768 - THC Port 1 Interrupt Pin Mux
+ Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
+ to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
+**/
+ UINT32 ThcPort1InterruptPinMuxing;
+
+/** Offset 0x076C - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+ PCIE_SPEED).
+**/
+ UINT8 PcieRpPcieSpeed[24];
+
+/** Offset 0x0784 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 PcieRpPhysicalSlotNumber[24];
+
+/** Offset 0x079C - PCIE RP Completion Timeout
+ The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PcieCompletionTO_Default.
+**/
+ UINT8 PcieRpCompletionTimeout[24];
+
+/** Offset 0x07B4 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[24];
+
+/** Offset 0x07CC - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[24];
+
+/** Offset 0x07E4 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[24];
+
+/** Offset 0x07FC - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PcieRpLtrConfigLock[24];
+
+/** Offset 0x0814 - PCIe override default settings for EQ
+ Choose PCIe EQ method
+ $EN_DIS
+**/
+ UINT8 PcieEqOverrideDefault;
+
+/** Offset 0x0815 - PCIe choose EQ method
+ Choose PCIe EQ method
+ 0: HardwareEq, 1: FixedEq
+**/
+ UINT8 PcieEqMethod;
+
+/** Offset 0x0816 - PCIe choose EQ mode
+ Choose PCIe EQ mode
+ 0: PresetEq, 1: CoefficientEq
+**/
+ UINT8 PcieEqMode;
+
+/** Offset 0x0817 - PCIe EQ local transmitter override
+ Enable/Disable local transmitter override
+ $EN_DIS
+**/
+ UINT8 PcieEqLocalTransmitterOverrideEnable;
+
+/** Offset 0x0818 - PCIe number of valid list entries
+ Select number of presets or coefficients depending on the mode
+**/
+ UINT8 PcieEqPh3NumberOfPresetsOrCoefficients;
+
+/** Offset 0x0819 - PCIe pre-cursor coefficient list
+ Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PreCursorList[10];
+
+/** Offset 0x0823 - PCIe post-cursor coefficient list
+ Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PostCursorList[10];
+
+/** Offset 0x082D - PCIe preset list
+ Provide a list of presets to be used during phase 3 EQ
+**/
+ UINT8 PcieEqPh3PresetList[11];
+
+/** Offset 0x0838 - PCIe EQ phase 1 downstream transmitter port preset
+ Allows to select the downstream port preset value that will be used during phase
+ 1 of equalization
+**/
+ UINT32 PcieEqPh1DownstreamPortTransmitterPreset;
+
+/** Offset 0x083C - PCIe EQ phase 1 upstream tranmitter port preset
+ Allows to select the upstream port preset value that will be used during phase 1
+ of equalization
+**/
+ UINT32 PcieEqPh1UpstreamPortTransmitterPreset;
+
+/** Offset 0x0840 - PCIe EQ phase 2 local transmitter override preset
+ Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+ UINT8 PcieEqPh2LocalTransmitterOverridePreset;
+
+/** Offset 0x0841 - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePeerMemoryWrite;
+
+/** Offset 0x0842 - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 PcieComplianceTestMode;
+
+/** Offset 0x0843 - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 PcieRpFunctionSwap;
+
+/** Offset 0x0844 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+ Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
+ Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 CpuPcieGen3ProgramStaticEq;
+
+/** Offset 0x0845 - Enable/Disable GEN4 Static EQ Phase1 programming
+ Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
+ Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 CpuPcieGen4ProgramStaticEq;
+
+/** Offset 0x0846 - PCH Pm PME_B0_S5_DIS
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+ $EN_DIS
+**/
+ UINT8 PchPmPmeB0S5Dis;
+
+/** Offset 0x0847 - PCIE IMR
+ Enables Isolated Memory Region for PCIe.
+ $EN_DIS
+**/
+ UINT8 PcieRpImrEnabled;
+
+/** Offset 0x0848 - PCIE IMR port number
+ Selects PCIE root port number for IMR feature.
+**/
+ UINT8 PcieRpImrSelection;
+
+/** Offset 0x0849 - PCH Pm Wol Enable Override
+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolEnableOverride;
+
+/** Offset 0x084A - PCH Pm Pcie Wake From DeepSx
+ Determine if enable PCIe to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmPcieWakeFromDeepSx;
+
+/** Offset 0x084B - PCH Pm WoW lan Enable
+ Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanEnable;
+
+/** Offset 0x084C - PCH Pm WoW lan DeepSx Enable
+ Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
+ PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanDeepSxEnable;
+
+/** Offset 0x084D - PCH Pm Lan Wake From DeepSx
+ Determine if enable LAN to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmLanWakeFromDeepSx;
+
+/** Offset 0x084E - PCH Pm Deep Sx Pol
+ Deep Sx Policy.
+ $EN_DIS
+**/
+ UINT8 PchPmDeepSxPol;
+
+/** Offset 0x084F - PCH Pm Slp S3 Min Assert
+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+ UINT8 PchPmSlpS3MinAssert;
+
+/** Offset 0x0850 - PCH Pm Slp S4 Min Assert
+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+ UINT8 PchPmSlpS4MinAssert;
+
+/** Offset 0x0851 - PCH Pm Slp Sus Min Assert
+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+ UINT8 PchPmSlpSusMinAssert;
+
+/** Offset 0x0852 - PCH Pm Slp A Min Assert
+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+ UINT8 PchPmSlpAMinAssert;
+
+/** Offset 0x0853 - USB Overcurrent Override for DbC
+ This option overrides USB Over Current enablement state that USB OC will be disabled
+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.
+ $EN_DIS
+**/
+ UINT8 PchEnableDbcObs;
+
+/** Offset 0x0854 - PCH Pm Slp Strch Sus Up
+ Enable SLP_X Stretching After SUS Well Power Up.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpStrchSusUp;
+
+/** Offset 0x0855 - PCH Pm Slp Lan Low Dc
+ Enable/Disable SLP_LAN# Low on DC Power.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpLanLowDc;
+
+/** Offset 0x0856 - PCH Pm Pwr Btn Override Period
+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+ UINT8 PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x0857 - PCH Pm Disable Dsx Ac Present Pulldown
+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableDsxAcPresentPulldown;
+
+/** Offset 0x0858 - PCH Pm Disable Native Power Button
+ Power button native mode disable.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableNativePowerButton;
+
+/** Offset 0x0859 - PCH Pm ME_WAKE_STS
+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmMeWakeSts;
+
+/** Offset 0x085A - PCH Pm WOL_OVR_WK_STS
+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolOvrWkSts;
+
+/** Offset 0x085B - PCH Pm Reset Power Cycle Duration
+ Could be customized in the unit of second. Please refer to EDS for all support settings.
+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+ UINT8 PchPmPwrCycDur;
+
+/** Offset 0x085C - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x085D - PCH Legacy IO Low Latency Enable
+ Set to enable low latency of legacy IO. 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchLegacyIoLowLatency;
+
+/** Offset 0x085E - PCH Sata Pwr Opt Enable
+ SATA Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x085F - PCH Sata eSATA Speed Limit
+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+ $EN_DIS
+**/
+ UINT8 EsataSpeedLimit;
+
+/** Offset 0x0860 - PCH Sata Speed Limit
+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
+**/
+ UINT8 SataSpeedLimit;
+
+/** Offset 0x0861 - Enable SATA Port HotPlug
+ Enable SATA Port HotPlug.
+**/
+ UINT8 SataPortsHotPlug[8];
+
+/** Offset 0x0869 - Enable SATA Port Interlock Sw
+ Enable SATA Port Interlock Sw.
+**/
+ UINT8 SataPortsInterlockSw[8];
+
+/** Offset 0x0871 - Enable SATA Port External
+ Enable SATA Port External.
+**/
+ UINT8 SataPortsExternal[8];
+
+/** Offset 0x0879 - Enable SATA Port SpinUp
+ Enable the COMRESET initialization Sequence to the device.
+**/
+ UINT8 SataPortsSpinUp[8];
+
+/** Offset 0x0881 - Enable SATA Port Solid State Drive
+ 0: HDD; 1: SSD.
+**/
+ UINT8 SataPortsSolidStateDrive[8];
+
+/** Offset 0x0889 - Enable SATA Port Enable Dito Config
+ Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+**/
+ UINT8 SataPortsEnableDitoConfig[8];
+
+/** Offset 0x0891 - Enable SATA Port DmVal
+ DITO multiplier. Default is 15.
+**/
+ UINT8 SataPortsDmVal[8];
+
+/** Offset 0x0899
+**/
+ UINT8 UnusedUpdSpace21[1];
+
+/** Offset 0x089A - Enable SATA Port DmVal
+ DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+ UINT16 SataPortsDitoVal[8];
+
+/** Offset 0x08AA - Enable SATA Port ZpOdd
+ Support zero power ODD.
+**/
+ UINT8 SataPortsZpOdd[8];
+
+/** Offset 0x08B2 - PCH Sata Rst Raid Alternate Id
+ Enable RAID Alternate ID.
+ $EN_DIS
+**/
+ UINT8 SataRstRaidDeviceId;
+
+/** Offset 0x08B3 - PCH Sata Rst Raid0
+ RAID0.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid0;
+
+/** Offset 0x08B4 - PCH Sata Rst Raid1
+ RAID1.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid1;
+
+/** Offset 0x08B5 - PCH Sata Rst Raid10
+ RAID10.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid10;
+
+/** Offset 0x08B6 - PCH Sata Rst Raid5
+ RAID5.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid5;
+
+/** Offset 0x08B7 - PCH Sata Rst Irrt
+ Intel Rapid Recovery Technology.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrt;
+
+/** Offset 0x08B8 - PCH Sata Rst Orom Ui Banner
+ OROM UI and BANNER.
+ $EN_DIS
+**/
+ UINT8 SataRstOromUiBanner;
+
+/** Offset 0x08B9 - PCH Sata Rst Orom Ui Delay
+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
+**/
+ UINT8 SataRstOromUiDelay;
+
+/** Offset 0x08BA - PCH Sata Rst Hdd Unlock
+ Indicates that the HDD password unlock in the OS is enabled.
+ $EN_DIS
+**/
+ UINT8 SataRstHddUnlock;
+
+/** Offset 0x08BB - PCH Sata Rst Led Locate
+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
+ enabled on the OS.
+ $EN_DIS
+**/
+ UINT8 SataRstLedLocate;
+
+/** Offset 0x08BC - PCH Sata Rst Irrt Only
+ Allow only IRRT drives to span internal and external ports.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrtOnly;
+
+/** Offset 0x08BD - PCH Sata Rst Smart Storage
+ RST Smart Storage caching Bit.
+ $EN_DIS
+**/
+ UINT8 SataRstSmartStorage;
+
+/** Offset 0x08BE - PCH Sata Rst Pcie Storage Remap enable
+ Enable Intel RST for PCIe Storage remapping.
+**/
+ UINT8 SataRstPcieEnable[3];
+
+/** Offset 0x08C1 - PCH Sata Rst Pcie Storage Port
+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
+**/
+ UINT8 SataRstPcieStoragePort[3];
+
+/** Offset 0x08C4 - PCH Sata Rst Pcie Device Reset Delay
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+**/
+ UINT8 SataRstPcieDeviceResetDelay[3];
+
+/** Offset 0x08C7 - UFS enable/disable
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+ $EN_DIS
+**/
+ UINT8 UfsEnable[2];
+
+/** Offset 0x08C9 - IEH Mode
+ Integrated Error Handler Mode, 0: Bypass, 1: Enable
+ 0: Bypass, 1:Enable
+**/
+ UINT8 IehMode;
+
+/** Offset 0x08CA - Thermal Throttling Custimized T0Level Value
+ Custimized T0Level value.
+**/
+ UINT16 PchT0Level;
+
+/** Offset 0x08CC - Thermal Throttling Custimized T1Level Value
+ Custimized T1Level value.
+**/
+ UINT16 PchT1Level;
+
+/** Offset 0x08CE - Thermal Throttling Custimized T2Level Value
+ Custimized T2Level value.
+**/
+ UINT16 PchT2Level;
+
+/** Offset 0x08D0 - Enable The Thermal Throttle
+ Enable the thermal throttle function.
+ $EN_DIS
+**/
+ UINT8 PchTTEnable;
+
+/** Offset 0x08D1 - PMSync State 13
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+ at least T2 state.
+ $EN_DIS
+**/
+ UINT8 PchTTState13Enable;
+
+/** Offset 0x08D2 - Thermal Throttle Lock
+ Thermal Throttle Lock.
+ $EN_DIS
+**/
+ UINT8 PchTTLock;
+
+/** Offset 0x08D3 - Thermal Throttling Suggested Setting
+ Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 TTSuggestedSetting;
+
+/** Offset 0x08D4 - Enable PCH Cross Throttling
+ Enable/Disable PCH Cross Throttling
+ $EN_DIS
+**/
+ UINT8 TTCrossThrottling;
+
+/** Offset 0x08D5 - DMI Thermal Sensor Autonomous Width Enable
+ DMI Thermal Sensor Autonomous Width Enable.
+ $EN_DIS
+**/
+ UINT8 PchDmiTsawEn;
+
+/** Offset 0x08D6 - DMI Thermal Sensor Suggested Setting
+ DMT thermal sensor suggested representative values.
+ $EN_DIS
+**/
+ UINT8 DmiSuggestedSetting;
+
+/** Offset 0x08D7 - Thermal Sensor 0 Target Width
+ Thermal Sensor 0 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS0TW;
+
+/** Offset 0x08D8 - Thermal Sensor 1 Target Width
+ Thermal Sensor 1 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS1TW;
+
+/** Offset 0x08D9 - Thermal Sensor 2 Target Width
+ Thermal Sensor 2 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS2TW;
+
+/** Offset 0x08DA - Thermal Sensor 3 Target Width
+ Thermal Sensor 3 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS3TW;
+
+/** Offset 0x08DB - Port 0 T1 Multipler
+ Port 0 T1 Multipler.
+**/
+ UINT8 SataP0T1M;
+
+/** Offset 0x08DC - Port 0 T2 Multipler
+ Port 0 T2 Multipler.
+**/
+ UINT8 SataP0T2M;
+
+/** Offset 0x08DD - Port 0 T3 Multipler
+ Port 0 T3 Multipler.
+**/
+ UINT8 SataP0T3M;
+
+/** Offset 0x08DE - Port 0 Tdispatch
+ Port 0 Tdispatch.
+**/
+ UINT8 SataP0TDisp;
+
+/** Offset 0x08DF - Port 1 T1 Multipler
+ Port 1 T1 Multipler.
+**/
+ UINT8 SataP1T1M;
+
+/** Offset 0x08E0 - Port 1 T2 Multipler
+ Port 1 T2 Multipler.
+**/
+ UINT8 SataP1T2M;
+
+/** Offset 0x08E1 - Port 1 T3 Multipler
+ Port 1 T3 Multipler.
+**/
+ UINT8 SataP1T3M;
+
+/** Offset 0x08E2 - Port 1 Tdispatch
+ Port 1 Tdispatch.
+**/
+ UINT8 SataP1TDisp;
+
+/** Offset 0x08E3 - Port 0 Tinactive
+ Port 0 Tinactive.
+**/
+ UINT8 SataP0Tinact;
+
+/** Offset 0x08E4 - Port 0 Alternate Fast Init Tdispatch
+ Port 0 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP0TDispFinit;
+
+/** Offset 0x08E5 - Port 1 Tinactive
+ Port 1 Tinactive.
+**/
+ UINT8 SataP1Tinact;
+
+/** Offset 0x08E6 - Port 1 Alternate Fast Init Tdispatch
+ Port 1 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP1TDispFinit;
+
+/** Offset 0x08E7 - Sata Thermal Throttling Suggested Setting
+ Sata Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 SataThermalSuggestedSetting;
+
+/** Offset 0x08E8 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+ $EN_DIS
+**/
+ UINT8 PchMemoryThrottlingEnable;
+
+/** Offset 0x08E9 - Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPmsyncEnable[2];
+
+/** Offset 0x08EB - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryC0TransmitEnable[2];
+
+/** Offset 0x08ED - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPinSelection[2];
+
+/** Offset 0x08EF
+**/
+ UINT8 UnusedUpdSpace22;
+
+/** Offset 0x08F0 - Thermal Device Temperature
+ Decides the temperature.
+**/
+ UINT16 PchTemperatureHotLevel;
+
+/** Offset 0x08F2 - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x0902 - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x090C - Enable xHCI LTR override
+ Enables override of recommended LTR values for xHCI
+ $EN_DIS
+**/
+ UINT8 PchUsbLtrOverrideEnable;
+
+/** Offset 0x090D
+**/
+ UINT8 UnusedUpdSpace23[3];
+
+/** Offset 0x0910 - xHCI High Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x0914 - xHCI Medium Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x0918 - xHCI Low Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrLowIdleTimeOverride;
+
+/** Offset 0x091C - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x091D - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x091E - PCH Sata Rst Optane Memory
+ Optane Memory
+ $EN_DIS
+**/
+ UINT8 SataRstOptaneMemory;
+
+/** Offset 0x091F - PCH Sata Rst CPU Attached Storage
+ CPU Attached Storage
+ $EN_DIS
+**/
+ UINT8 SataRstCpuAttachedStorage;
+
+/** Offset 0x0920 - Enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+ emulation must be enabled, and WDAT table must not be exposed to the OS.
+ $EN_DIS
+**/
+ UINT8 EnableTcoTimer;
+
+/** Offset 0x0921 - Hybrid Storage Detection and Configuration Mode
+ Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
+ Default is 0: Disabled
+ 0: Disabled, 1: Dynamic Configuration
+**/
+ UINT8 HybridStorageMode;
+
+/** Offset 0x0922
+**/
+ UINT8 UnusedUpdSpace24[6];
+
+/** Offset 0x0928 - BgpdtHash[4]
+ BgpdtHash values
+**/
+ UINT64 BgpdtHash[4];
+
+/** Offset 0x0948 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
+
+/** Offset 0x094C
+**/
+ UINT8 UnusedUpdSpace25[4];
+
+/** Offset 0x0950 - BiosGuardModulePtr
+ BiosGuardModulePtr default values
+**/
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0958 - SendEcCmd
+ SendEcCmd function pointer. \n
+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
+**/
+ UINT64 SendEcCmd;
+
+/** Offset 0x0960 - EcCmdProvisionEav
+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+**/
+ UINT8 EcCmdProvisionEav;
+
+/** Offset 0x0961 - EcCmdLock
+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+**/
+ UINT8 EcCmdLock;
+
+/** Offset 0x0962
+**/
+ UINT8 UnusedUpdSpace26[6];
+
+/** Offset 0x0968 - SgxEpoch0
+ SgxEpoch0 default values
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0970 - SgxEpoch1
+ SgxEpoch1 default values
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x0978 - SgxSinitNvsData
+ SgxSinitNvsData default values
+**/
+ UINT8 SgxSinitNvsData;
+
+/** Offset 0x0979 - Si Config CSM Flag.
+ @deprecated Platform specific common policies that used by several silicon
+ components. CSM status flag.
+ $EN_DIS
+**/
+ UINT8 SiCsmFlag;
+
+/** Offset 0x097A - Skip Ssid Programming.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ $EN_DIS
+**/
+ UINT8 SiSkipSsidProgramming;
+
+/** Offset 0x097B
+**/
+ UINT8 UnusedUpdSpace27;
+
+/** Offset 0x097C - Change Default SVID
+ Change the default SVID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSvid;
+
+/** Offset 0x097E - Change Default SSID
+ Change the default SSID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSsid;
+
+/** Offset 0x0980 - SVID SDID table Poniter.
+ The address of the table of SVID SDID to customize each SVID SDID entry. This is
+ only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT32 SiSsidTablePtr;
+
+/** Offset 0x0984 - Number of ssid table.
+ SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+ This is only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiNumberOfSsidTableEntry;
+
+/** Offset 0x0986 - USB2 Port Reset Message Enable
+ 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
+**/
+ UINT8 PortResetMessageEnable[16];
+
+/** Offset 0x0996 - SATA RST Interrupt Mode
+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
+ 0:Msix, 1:Msi, 2:Legacy
+**/
+ UINT8 SataRstInterrupt;
+
+/** Offset 0x0997 - ME Unconfig on RTC clear
+ 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear.
+ 2: Cmos is clear, status unkonwn. 3: Reserved
+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+ is clear, 3: Reserved
+**/
+ UINT8 MeUnconfigOnRtcClear;
+
+/** Offset 0x0998 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x0999 - Pmc Cpu C10 Gate Pin Enable
+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+ and VccSTG rails instead of SLP_S0# pin.
+ $EN_DIS
+**/
+ UINT8 PmcCpuC10GatePinEnable;
+
+/** Offset 0x099A - Pch Dmi Aspm Ctrl
+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
+**/
+ UINT8 PchDmiAspmCtrl;
+
+/** Offset 0x099B - PchDmiCwbEnable
+ Central Write Buffer feature configurable and enabled by default
+ $EN_DIS
+**/
+ UINT8 PchDmiCwbEnable;
+
+/** Offset 0x099C - OS IDLE Mode Enable
+ Enable/Disable OS Idle Mode
+ $EN_DIS
+**/
+ UINT8 PmcOsIdleEnable;
+
+/** Offset 0x099D - S0ix Auto-Demotion
+ Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
+ $EN_DIS
+**/
+ UINT8 PchS0ixAutoDemotion;
+
+/** Offset 0x099E - Latch Events C10 Exit
+ When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
+ captured on C10 exit (instead of C10 entry which is default)
+ $EN_DIS
+**/
+ UINT8 PchPmLatchEventsC10Exit;
+
+/** Offset 0x099F - PCIE Eq Ph3 Lane Param Cm
+ CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieEqPh3LaneParamCm[32];
+
+/** Offset 0x09BF - PCIE Eq Ph3 Lane Param Cp
+ CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieEqPh3LaneParamCp[32];
+
+/** Offset 0x09DF - PCIE Hw Eq Gen3 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieHwEqGen3CoeffListCm[5];
+
+/** Offset 0x09E4 - PCIE Hw Eq Gen3 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieHwEqGen3CoeffListCp[5];
+
+/** Offset 0x09E9 - PCIE Hw Eq Gen4 CoeffList Cm
+ CPU_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 CpuPcieHwEqGen4CoeffListCm[5];
+
+/** Offset 0x09EE - PCIE Hw Eq Gen4 CoeffList Cp
+ CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 CpuPcieHwEqGen4CoeffListCp[5];
+
+/** Offset 0x09F3 - Gen3 Root port preset values per lane
+ Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen3RootPortPreset[20];
+
+/** Offset 0x0A07 - Pcie Gen4 Root port preset values per lane
+ Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen4RootPortPreset[20];
+
+/** Offset 0x0A1B - Pcie Gen3 End port preset values per lane
+ Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen3EndPointPreset[20];
+
+/** Offset 0x0A2F - Pcie Gen4 End port preset values per lane
+ Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default
+ for each lane
+**/
+ UINT8 CpuPcieGen4EndPointPreset[20];
+
+/** Offset 0x0A43 - Pcie Gen3 End port Hint values per lane
+ Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 CpuPcieGen3EndPointHint[20];
+
+/** Offset 0x0A57 - Pcie Gen4 End port Hint values per lane
+ Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 CpuPcieGen4EndPointHint[20];
+
+/** Offset 0x0A6B - CPU PCIe Fia Programming
+ Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieFiaProgramming;
+
+/** Offset 0x0A6C - CPU PCIe RootPort Clock Gating
+ Describes whether the PCI Express Clock Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieClockGating;
+
+/** Offset 0x0A6D - CPU PCIe RootPort Power Gating
+ Describes whether the PCI Express Power Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPciePowerGating;
+
+/** Offset 0x0A6E - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 CpuPcieComplianceTestMode;
+
+/** Offset 0x0A6F - PCIE Secure Register Lock
+ Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
+ load CpuPcieRpSetSecuredRegisterLock recipe. DEPRECATED 0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 CpuPcieSetSecuredRegisterLock;
+
+/** Offset 0x0A70 - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 CpuPcieEnablePeerMemoryWrite;
+
+/** Offset 0x0A71 - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 CpuPcieRpFunctionSwap;
+
+/** Offset 0x0A72 - PCI Express Slot Selection
+ Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default).
+ $EN_DIS
+**/
+ UINT8 CpuPcieSlotSelection;
+
+/** Offset 0x0A73
+**/
+ UINT8 UnusedUpdSpace28;
+
+/** Offset 0x0A74 - CPU PCIE device override table pointer
+ The PCIe device table is being used to override PCIe device ASPM settings. This
+ is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
+ refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
+ must be 0.
+**/
+ UINT32 CpuPcieDeviceOverrideTablePtr;
+
+/** Offset 0x0A78 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 CpuPcieRpHotPlug[4];
+
+/** Offset 0x0A7C - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 CpuPcieRpPmSci[4];
+
+/** Offset 0x0A80 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 CpuPcieRpTransmitterHalfSwing[4];
+
+/** Offset 0x0A84 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 CpuPcieRpAcsEnabled[4];
+
+/** Offset 0x0A88 - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 CpuPcieRpEnableCpm[4];
+
+/** Offset 0x0A8C - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 CpuPcieRpAdvancedErrorReporting[4];
+
+/** Offset 0x0A90 - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 CpuPcieRpUnsupportedRequestReport[4];
+
+/** Offset 0x0A94 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 CpuPcieRpFatalErrorReport[4];
+
+/** Offset 0x0A98 - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 CpuPcieRpNoFatalErrorReport[4];
+
+/** Offset 0x0A9C - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 CpuPcieRpCorrectableErrorReport[4];
+
+/** Offset 0x0AA0 - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnFatalError[4];
+
+/** Offset 0x0AA4 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnNonFatalError[4];
+
+/** Offset 0x0AA8 - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 CpuPcieRpSystemErrorOnCorrectableError[4];
+
+/** Offset 0x0AAC - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 CpuPcieRpMaxPayload[4];
+
+/** Offset 0x0AB0 - DPC for PCIE RP Mask
+ Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpDpcEnabled[4];
+
+/** Offset 0x0AB4 - DPC Extensions PCIE RP Mask
+ Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
+ for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpDpcExtensionsEnabled[4];
+
+/** Offset 0x0AB8 - CPU PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 CpuPcieRpSlotImplemented[4];
+
+/** Offset 0x0ABC - PCIE RP Gen3 Equalization Phase Method
+ PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+ 1: hardware equalization; 4: Fixed Coeficients.
+**/
+ UINT8 CpuPcieRpGen3EqPh3Method[4];
+
+/** Offset 0x0AC0 - PCIE RP Gen4 Equalization Phase Method
+ PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+ 1: hardware equalization; 4: Fixed Coeficients.
+**/
+ UINT8 CpuPcieRpGen4EqPh3Method[4];
+
+/** Offset 0x0AC4 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 CpuPcieRpPhysicalSlotNumber[4];
+
+/** Offset 0x0AC8 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable;
+ 2: CpuPcieAspmL1(Default)
+**/
+ UINT8 CpuPcieRpAspm[4];
+
+/** Offset 0x0ACC - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL).
+ Default is CpuPcieL1SubstatesL1_1_2.
+**/
+ UINT8 CpuPcieRpL1Substates[4];
+
+/** Offset 0x0AD0 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 CpuPcieRpLtrEnable[4];
+
+/** Offset 0x0AD4 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 CpuPcieRpLtrConfigLock[4];
+
+/** Offset 0x0AD8 - PTM for PCIE RP Mask
+ Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on. [ALIAS_NAME RpPtmBytes]
+**/
+ UINT8 CpuPcieRpPtmEnabled[4];
+
+/** Offset 0x0ADC - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 CpuPcieRpDetectTimeoutMs[4];
+
+/** Offset 0x0AE4 - VC for PCIE RP Mask
+ Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit
+ for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpVcEnabled[4];
+
+/** Offset 0x0AE8 - Multi-VC for PCIE RP Mask
+ Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT8 CpuPcieRpMultiVcEnabled[4];
+
+/** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x0AF6 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default
+ = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTran[10];
+
+/** Offset 0x0B00 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x0B0A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x0B14 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x0B1E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x0B28 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x0B32 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+ Default = 4Ch. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x0B3C - Skip PAM regsiter lock
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ $EN_DIS
+**/
+ UINT8 SkipPamLock;
+
+/** Offset 0x0B3D - EDRAM Test Mode
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
+**/
+ UINT8 EdramTestMode;
+
+/** Offset 0x0B3E - Enable/Disable IGFX RenderStandby
+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+ $EN_DIS
+**/
+ UINT8 RenderStandby;
+
+/** Offset 0x0B3F - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x0B40 - Enable/Disable CdynmaxClamp
+ Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
+ $EN_DIS
+**/
+ UINT8 CdynmaxClampEnable;
+
+/** Offset 0x0B41 - GT Frequency Limit
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+**/
+ UINT8 GtFreqMax;
+
+/** Offset 0x0B42 - Disable Turbo GT
+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
+ $EN_DIS
+**/
+ UINT8 DisableTurboGt;
+
+/** Offset 0x0B43 - Enable/Disable CdClock Init
+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
+ CD clock if not initialized by Gfx PEIM
+ $EN_DIS
+**/
+ UINT8 SkipCdClockInit;
+
+/** Offset 0x0B44 - Enable RC1p frequency request to PMA (provided all other conditions are met)
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 RC1pFreqEnable;
+
+/** Offset 0x0B45 - Enable TSN Multi-VC
+ Enable/disable Multi Virtual Channels(VC) in TSN.
+ $EN_DIS
+**/
+ UINT8 PchTsnMultiVcEnable;
+
+/** Offset 0x0B46 - SaPostMemTestRsvd
+ Reserved for SA Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPostMemTestRsvd[13];
+
+/** Offset 0x0B53 - RSR feature
+ Enable or Disable RSR feature; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableRsr;
+
+/** Offset 0x0B54 - 1-Core Ratio Limit
+ 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
+ to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
+**/
+ UINT8 OneCoreRatioLimit;
+
+/** Offset 0x0B55 - 2-Core Ratio Limit
+ 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 TwoCoreRatioLimit;
+
+/** Offset 0x0B56 - 3-Core Ratio Limit
+ 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 ThreeCoreRatioLimit;
+
+/** Offset 0x0B57 - 4-Core Ratio Limit
+ 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 FourCoreRatioLimit;
+
+/** Offset 0x0B58 - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable;
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x0B59 - Hardware Duty Cycle Control
+ Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 HdcControl;
+
+/** Offset 0x0B5A - Package Long duration turbo mode time
+ Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
+ 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PowerLimit1Time;
+
+/** Offset 0x0B5B - Short Duration Turbo Mode
+ Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit2;
+
+/** Offset 0x0B5C - Turbo settings Lock
+ Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable
+ $EN_DIS
+**/
+ UINT8 TurboPowerLimitLock;
+
+/** Offset 0x0B5D - Package PL3 time window
+ Package PL3 time window range for this policy from 0 to 64ms
+**/
+ UINT8 PowerLimit3Time;
+
+/** Offset 0x0B5E - Package PL3 Duty Cycle
+ Package PL3 Duty Cycle; Valid Range is 0 to 100
+**/
+ UINT8 PowerLimit3DutyCycle;
+
+/** Offset 0x0B5F - Package PL3 Lock
+ Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit3Lock;
+
+/** Offset 0x0B60 - Package PL4 Lock
+ Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit4Lock;
+
+/** Offset 0x0B61 - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
+ 10, For all other SKUs the recommended default are 0
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x0B62 - Tcc Offset Clamp Enable/Disable
+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
+ below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled,
+ For all other SKUs the recommended default are 0: Disabled.
+ $EN_DIS
+**/
+ UINT8 TccOffsetClamp;
+
+/** Offset 0x0B63 - Tcc Offset Lock
+ Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+ target; 0: Disabled; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 TccOffsetLock;
+
+/** Offset 0x0B64 - Custom Ratio State Entries
+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+ ratio table.Sets the number of custom P-states. At least 2 states must be present
+**/
+ UINT8 NumberOfEntries;
+
+/** Offset 0x0B65 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
+**/
+ UINT8 Custom1PowerLimit1Time;
+
+/** Offset 0x0B66 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
+**/
+ UINT8 Custom1TurboActivationRatio;
+
+/** Offset 0x0B67 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom1ConfigTdpControl;
+
+/** Offset 0x0B68 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
+**/
+ UINT8 Custom2PowerLimit1Time;
+
+/** Offset 0x0B69 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
+**/
+ UINT8 Custom2TurboActivationRatio;
+
+/** Offset 0x0B6A - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom2ConfigTdpControl;
+
+/** Offset 0x0B6B - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
+**/
+ UINT8 Custom3PowerLimit1Time;
+
+/** Offset 0x0B6C - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
+**/
+ UINT8 Custom3TurboActivationRatio;
+
+/** Offset 0x0B6D - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom3ConfigTdpControl;
+
+/** Offset 0x0B6E - ConfigTdp mode settings Lock
+ Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ConfigTdpLock;
+
+/** Offset 0x0B6F - Load Configurable TDP SSDT
+ Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ConfigTdpBios;
+
+/** Offset 0x0B70 - PL1 Enable value
+ PL1 Enable value to limit average platform power. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit1;
+
+/** Offset 0x0B71 - PL1 timewindow
+ PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
+ , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PsysPowerLimit1Time;
+
+/** Offset 0x0B72 - PL2 Enable Value
+ PL2 Enable activates the PL2 value to limit average platform power.0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit2;
+
+/** Offset 0x0B73 - Enable or Disable MLC Streamer Prefetcher
+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MlcStreamerPrefetcher;
+
+/** Offset 0x0B74 - Enable or Disable MLC Spatial Prefetcher
+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 MlcSpatialPrefetcher;
+
+/** Offset 0x0B75 - Enable or Disable Monitor /MWAIT instructions
+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x0B76 - Enable or Disable initialization of machine check registers
+ Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MachineCheckEnable;
+
+/** Offset 0x0B77 - AP Idle Manner of waiting for SIPI
+ AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop.
+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop
+**/
+ UINT8 ApIdleManner;
+
+/** Offset 0x0B78 - Control on Processor Trace output scheme
+ Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
+ 0: Single Range Output, 1: ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x0B79 - Enable or Disable Processor Trace feature
+ Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x0B7A - Enable or Disable Intel SpeedStep Technology
+ Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x0B7B - Enable or Disable Energy Efficient P-state
+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
+ 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientPState;
+
+/** Offset 0x0B7C - Enable or Disable Energy Efficient Turbo
+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
+ 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientTurbo;
+
+/** Offset 0x0B7D - Enable or Disable T states
+ Enable or Disable T states; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TStates;
+
+/** Offset 0x0B7E - Enable or Disable Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 BiProcHot;
+
+/** Offset 0x0B7F - Enable or Disable PROCHOT# signal being driven externally
+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableProcHotOut;
+
+/** Offset 0x0B80 - Enable or Disable PROCHOT# Response
+ Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcHotResponse;
+
+/** Offset 0x0B81 - Enable or Disable VR Thermal Alert
+ Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableVrThermalAlert;
+
+/** Offset 0x0B82 - Enable or Disable Thermal Reporting
+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 EnableAllThermalFunctions;
+
+/** Offset 0x0B83 - Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ThermalMonitor;
+
+/** Offset 0x0B84 - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x0B85 - Configure C-State Configuration Lock
+ Configure C-State Configuration Lock; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PmgCstCfgCtrlLock;
+
+/** Offset 0x0B86 - Enable or Disable Enhanced C-states
+ Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x0B87 - Enable or Disable Package Cstate Demotion
+ Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x0B88 - Enable or Disable Package Cstate UnDemotion
+ Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x0B89 - Enable or Disable CState-Pre wake
+ Enable or Disable CState-Pre wake. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 CStatePreWake;
+
+/** Offset 0x0B8A - Enable or Disable TimedMwait Support.
+ Enable or Disable TimedMwait Support. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 TimedMwait;
+
+/** Offset 0x0B8B - Enable or Disable IO to MWAIT redirection
+ Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CstCfgCtrIoMwaitRedirection;
+
+/** Offset 0x0B8C - Set the Max Pkg Cstate
+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x0B8D - TimeUnit for C-State Latency Control0
+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl0TimeUnit;
+
+/** Offset 0x0B8E - TimeUnit for C-State Latency Control1
+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl1TimeUnit;
+
+/** Offset 0x0B8F - TimeUnit for C-State Latency Control2
+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl2TimeUnit;
+
+/** Offset 0x0B90 - TimeUnit for C-State Latency Control3
+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl3TimeUnit;
+
+/** Offset 0x0B91 - TimeUnit for C-State Latency Control4
+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl4TimeUnit;
+
+/** Offset 0x0B92 - TimeUnit for C-State Latency Control5
+ TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl5TimeUnit;
+
+/** Offset 0x0B93 - Interrupt Redirection Mode Select
+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
+ No change.
+**/
+ UINT8 PpmIrmSetting;
+
+/** Offset 0x0B94 - Lock prochot configuration
+ Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ProcHotLock;
+
+/** Offset 0x0B95 - Configuration for boot TDP selection
+ Deprecated. Move to premem.
+**/
+ UINT8 DeprecatedConfigTdpLevel;
+
+/** Offset 0x0B96 - Max P-State Ratio
+ Max P-State Ratio, Valid Range 0 to 0x7F
+**/
+ UINT8 MaxRatio;
+
+/** Offset 0x0B97 - P-state ratios for custom P-state table
+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+ are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatio[40];
+
+/** Offset 0x0BBF - P-state ratios for max 16 version of custom P-state table
+ P-state ratios for max 16 version of custom P-state table. This table is used for
+ OS versions limited to a max of 16 P-States. If the first entry of this table is
+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
+ of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatioMax16[16];
+
+/** Offset 0x0BCF
+**/
+ UINT8 UnusedUpdSpace29;
+
+/** Offset 0x0BD0 - Platform Power Pmax
+ PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments.
+ Range 0-1024 Watts. Value of 800 = 100W
+**/
+ UINT16 PsysPmax;
+
+/** Offset 0x0BD2 - Interrupt Response Time Limit of C-State LatencyContol1
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl1Irtl;
+
+/** Offset 0x0BD4 - Interrupt Response Time Limit of C-State LatencyContol2
+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl2Irtl;
+
+/** Offset 0x0BD6 - Interrupt Response Time Limit of C-State LatencyContol3
+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl3Irtl;
+
+/** Offset 0x0BD8 - Interrupt Response Time Limit of C-State LatencyContol4
+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl4Irtl;
+
+/** Offset 0x0BDA - Interrupt Response Time Limit of C-State LatencyContol5
+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl5Irtl;
+
+/** Offset 0x0BDC - Package Long duration turbo mode power limit
+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ Valid Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit1;
+
+/** Offset 0x0BE0 - Package Short duration turbo mode power limit
+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit2Power;
+
+/** Offset 0x0BE4 - Package PL3 power limit
+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit3;
+
+/** Offset 0x0BE8 - Package PL4 power limit
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit4;
+
+/** Offset 0x0BEC - Tcc Offset Time Window for RATL
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 TccOffsetTimeWindowForRatl;
+
+/** Offset 0x0BF0 - Short term Power Limit value for custom cTDP level 1
+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit1;
+
+/** Offset 0x0BF4 - Long term Power Limit value for custom cTDP level 1
+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit2;
+
+/** Offset 0x0BF8 - Short term Power Limit value for custom cTDP level 2
+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit1;
+
+/** Offset 0x0BFC - Long term Power Limit value for custom cTDP level 2
+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit2;
+
+/** Offset 0x0C00 - Short term Power Limit value for custom cTDP level 3
+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit1;
+
+/** Offset 0x0C04 - Long term Power Limit value for custom cTDP level 3
+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit2;
+
+/** Offset 0x0C08 - Platform PL1 power
+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit1Power;
+
+/** Offset 0x0C0C - Platform PL2 power
+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit2Power;
+
+/** Offset 0x0C10 - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+ through MSR 1FC bit 20)Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x0C11 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents Three
+ Strike counter from incrementing; 0: False; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0C12 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 HwpInterruptControl;
+
+/** Offset 0x0C13 - 5-Core Ratio Limit
+ 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 FiveCoreRatioLimit;
+
+/** Offset 0x0C14 - 6-Core Ratio Limit
+ 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SixCoreRatioLimit;
+
+/** Offset 0x0C15 - 7-Core Ratio Limit
+ 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SevenCoreRatioLimit;
+
+/** Offset 0x0C16 - 8-Core Ratio Limit
+ 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 EightCoreRatioLimit;
+
+/** Offset 0x0C17 - Intel Turbo Boost Max Technology 3.0
+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 EnableItbm;
+
+/** Offset 0x0C18 - Intel Turbo Boost Max Technology 3.0 Driver
+ @Deprecated: Intel Turbo Boost Max Technology 3.0 Driver doesn't support for TGL
+ $EN_DIS
+**/
+ UINT8 EnableItbmDriver;
+
+/** Offset 0x0C19 - Enable or Disable C1 Cstate Demotion
+ Enable or Disable C1 Cstate Demotion. Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1StateAutoDemotion;
+
+/** Offset 0x0C1A - Enable or Disable C1 Cstate UnDemotion
+ Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 C1StateUnDemotion;
+
+/** Offset 0x0C1B - Minimum Ring ratio limit override
+ Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MinRingRatioLimit;
+
+/** Offset 0x0C1C - Maximum Ring ratio limit override
+ Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MaxRingRatioLimit;
+
+/** Offset 0x0C1D - Enable or Disable Per Core P State OS control
+ Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnablePerCorePState;
+
+/** Offset 0x0C1E - Enable or Disable HwP Autonomous Per Core P State OS control
+ Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1:
+ Enable
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoPerCorePstate;
+
+/** Offset 0x0C1F - Enable or Disable HwP Autonomous EPP Grouping
+ Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoEppGrouping;
+
+/** Offset 0x0C20 - Enable or Disable EPB override over PECI
+ Enable or Disable EPB override over PECI. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableEpbPeciOverride;
+
+/** Offset 0x0C21 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
+ Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableFastMsrHwpReq;
+
+/** Offset 0x0C22 - Enable Configurable TDP
+ Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP;
+ 1: Applies to cTDP
+ $EN_DIS
+**/
+ UINT8 ApplyConfigTdp;
+
+/** Offset 0x0C23 - Enable VccIn Demotion Override Configuration
+ Enable VccIn Demotion Override Configuration. The timing can be configured by VccInDemotionMs.
+ $EN_DIS
+**/
+ UINT8 VccInDemotionOverride;
+
+/** Offset 0x0C24 - Customize the VccIn Demotion in ms.
+ Customize the VccIn Demotion in ms accordingly. Values used by OEM expected to be
+ in lower end of 1-30 ms range. Value 1 means 1ms, value 2 means 2ms, and so on.
+ Value 0 will disable VccIn Demotion knob. It's 30ms by silicon default
+**/
+ UINT32 VccInDemotionMs;
+
+/** Offset 0x0C28 - ReservedCpuPostMemTest
+ Reserved for CPU Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemTest[11];
+
+/** Offset 0x0C33 - SgxSinitDataFromTpm
+ SgxSinitDataFromTpm default values
+**/
+ UINT8 SgxSinitDataFromTpm;
+
+/** Offset 0x0C34
+**/
+ UINT8 SecurityPostMemRsvd[16];
+
+/** Offset 0x0C44 - End of Post message
+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+ UINT8 EndOfPostMessage;
+
+/** Offset 0x0C45 - D0I3 Setting for HECI Disable
+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+ HECI devices
+ $EN_DIS
+**/
+ UINT8 DisableD0I3SettingForHeci;
+
+/** Offset 0x0C46 - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x0C47 - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x0C48 - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x0C49 - PCH Unlock SideBand access
+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+ $EN_DIS
+**/
+ UINT8 PchSbAccessUnlock;
+
+/** Offset 0x0C4A - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x0C7A - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0CAA - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0CC2 - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0CDA - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D0A - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0D22 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0D3A - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D6A - PCIE RP Slot Power Limit Scale
+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+ UINT8 PcieRpSlotPowerLimitScale[24];
+
+/** Offset 0x0D82 - PCIE RP Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+ UINT16 PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0DB2 - PCIE RP Enable Port8xh Decode
+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePort8xhDecode;
+
+/** Offset 0x0DB3 - PCIE Port8xh Decode Port Index
+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
+**/
+ UINT8 PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0DB4 - PCH Energy Reporting
+ Disable/Enable PCH to CPU energy report feature.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableEnergyReport;
+
+/** Offset 0x0DB5 - PCH Sata Test Mode
+ Allow entrance to the PCH SATA test modes.
+ $EN_DIS
+**/
+ UINT8 SataTestMode;
+
+/** Offset 0x0DB6 - PCH USB OverCurrent mapping lock enable
+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+ $EN_DIS
+**/
+ UINT8 PchXhciOcLock;
+
+/** Offset 0x0DB7 - Low Power Mode Enable/Disable config mask
+ Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+ to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+ LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. [ALIAS_NAME LpmStateEnableMask]
+**/
+ UINT8 PmcLpmS0ixSubStateEnableMask;
+
+/** Offset 0x0DB8 - Mctp Broadcast Cycle
+ Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MctpBroadcastCycle;
+
+/** Offset 0x0DB9
+**/
+ UINT8 UnusedUpdSpace30[1];
+
+/** Offset 0x0DBA - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 CpuPcieRpLtrMaxSnoopLatency[4];
+
+/** Offset 0x0DC2 - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4];
+
+/** Offset 0x0DCA - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 CpuPcieRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0DCE - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0DD2 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 CpuPcieRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x0DDA - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0DDE - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0DE2 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x0DEA - PCIE RP Upstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
+**/
+ UINT8 CpuPcieRpGen3Uptp[4];
+
+/** Offset 0x0DEE - PCIE RP Downstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
+**/
+ UINT8 CpuPcieRpGen3Dptp[4];
+
+/** Offset 0x0DF2 - PCIE RP Upstream Port Transmiter Preset
+ Used during Gen4 Link Equalization. Used for all lanes. Default is 8.
+**/
+ UINT8 CpuPcieRpGen4Uptp[4];
+
+/** Offset 0x0DF6 - PCIE RP Downstream Port Transmiter Preset
+ Used during Gen4 Link Equalization. Used for all lanes. Default is 9.
+**/
+ UINT8 CpuPcieRpGen4Dptp[4];
+
+/** Offset 0x0DFA - PMC C10 dynamic threshold dajustment enable
+ Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
+ $EN_DIS
+**/
+ UINT8 PmcC10DynamicThresholdAdjustment;
+
+/** Offset 0x0DFB - FOMS Control Policy
+ Choose the Foms Control Policy, Default = 0
+ 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+ UINT8 CpuPcieFomsCp[4];
+
+/** Offset 0x0DFF
+**/
+ UINT8 UnusedUpdSpace31;
+
+/** Offset 0x0E00 - LogoPixelHeight Address
+ Address of LogoPixelHeight
+**/
+ UINT32 LogoPixelHeight;
+
+/** Offset 0x0E04 - LogoPixelWidth Address
+ Address of LogoPixelWidth
+**/
+ UINT32 LogoPixelWidth;
+
+/** Offset 0x0E08 - P2P mode for PCIE RP
+ Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable.
+ 0: Disable, 1: Enable
+**/
+ UINT8 CpuPcieRpPeerToPeerMode[4];
+
+/** Offset 0x0E0C - Map port under VMD
+ Map/UnMap port under VMD
+ $EN_DIS
+**/
+ UINT8 VmdPort[31];
+
+/** Offset 0x0E2B - VMD Port Device
+ VMD Root port device number.
+**/
+ UINT8 VmdPortDev[31];
+
+/** Offset 0x0E4A - VMD Port Func
+ VMD Root port function number.
+**/
+ UINT8 VmdPortFunc[31];
+
+/** Offset 0x0E69
+**/
+ UINT8 UnusedUpdSpace32[3];
+
+/** Offset 0x0E6C - VMD Variable
+ VMD Variable Pointer.
+**/
+ UINT32 VmdVariablePtr;
+
+/** Offset 0x0E70 - Thermal Design Current time window
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 TdcTimeWindow1[5];
+
+/** Offset 0x0E84 - Temporary CfgBar address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdCfgBarBase;
+
+/** Offset 0x0E88 - Temporary MemBar1 address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdMemBar1Base;
+
+/** Offset 0x0E8C - Temporary MemBar2 address for VMD
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Range 1ms to 448s
+**/
+ UINT32 VmdMemBar2Base;
+
+/** Offset 0x0E90 - PCH TSN1 MAC Address High Bits
+ Set TSN1 MAC Address High.
+**/
+ UINT32 PchTsn1MacAddressHigh;
+
+/** Offset 0x0E94 - PCH TSN1 MAC Address Low Bits
+ Set TSN1 MAC Address Low.
+**/
+ UINT32 PchTsn1MacAddressLow;
+
+/** Offset 0x0E98 - FspEventHandler
+ Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
+**/
+ UINT32 FspEventHandler;
+
+/** Offset 0x0E9C - Enable VMD Global Mapping
+ Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 VmdGlobalMapping;
+
+/** Offset 0x0E9D - PCH XHCI LTR Mode Enable
+ Enable/Disable PCH XHCI LTR Mode.0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PchXhciLtrModeEnable;
+
+/** Offset 0x0E9E
+**/
+ UINT8 UnusedUpdSpace33[3];
+
+/** Offset 0x0EA1
+**/
+ UINT8 ReservedFspsUpd[7];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0EA8
+**/
+ UINT8 UnusedUpdSpace34[6];
+
+/** Offset 0x0EAE
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3060/FSP/Include/FsptUpd.h b/models/gaze16-3060/FSP/Include/FsptUpd.h
new file mode 100644
index 0000000..98f9bfc
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FsptUpd.h
@@ -0,0 +1,290 @@
+/** @file FsptUpd.h
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionSize;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - PcdSerialIoUartDebugEnable
+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0041 - PcdSerialIoUartNumber
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIoUartNumber;
+
+/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 PcdSerialIoUartMode;
+
+/** Offset 0x0043
+**/
+ UINT8 UnusedUpdSpace0;
+
+/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 PcdSerialIoUartBaudRate;
+
+/** Offset 0x0048 - Pci Express Base Address
+ Base address to be programmed for Pci Express
+**/
+ UINT64 PcdPciExpressBaseAddress;
+
+/** Offset 0x0050 - Pci Express Region Length
+ Region Length to be programmed for Pci Express
+**/
+ UINT32 PcdPciExpressRegionLength;
+
+/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 PcdSerialIoUartParity;
+
+/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 PcdSerialIoUartDataBits;
+
+/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 PcdSerialIoUartStopBits;
+
+/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
+ Enables UART hardware flow control, CTS and RTS lines.
+ 0: Disable, 1:Enable
+**/
+ UINT8 PcdSerialIoUartAutoFlow;
+
+/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 PcdSerialIoUartRxPinMux;
+
+/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
+ Select TX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 PcdSerialIoUartTxPinMux;
+
+/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
+ Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIoUartRtsPinMux;
+
+/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
+ Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIoUartCtsPinMux;
+
+/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 PcdSerialIoUartDebugMmioBase;
+
+/** Offset 0x006C - PcdLpcUartDebugEnable
+ Enable to initialize LPC Uart device in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 PcdLpcUartDebugEnable;
+
+/** Offset 0x006D - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x006E - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x006F - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x0070 - PcdSerialIo2ndUartEnable
+ Enable Additional SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIo2ndUartEnable;
+
+/** Offset 0x0071 - PcdSerialIo2ndUartNumber
+ Select SerialIo Uart Controller Number
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIo2ndUartNumber;
+
+/** Offset 0x0072 - PcdSerialIo2ndUartMode - FSPT
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 PcdSerialIo2ndUartMode;
+
+/** Offset 0x0073
+**/
+ UINT8 UnusedUpdSpace1;
+
+/** Offset 0x0074 - PcdSerialIo2ndUartBaudRate - FSPT
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 PcdSerialIo2ndUartBaudRate;
+
+/** Offset 0x0078 - PcdSerialIo2ndUartParity - FSPT
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 PcdSerialIo2ndUartParity;
+
+/** Offset 0x0079 - PcdSerialIo2ndUartDataBits - FSPT
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 PcdSerialIo2ndUartDataBits;
+
+/** Offset 0x007A - PcdSerialIo2ndUartStopBits - FSPT
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 PcdSerialIo2ndUartStopBits;
+
+/** Offset 0x007B - PcdSerialIo2ndUartAutoFlow - FSPT
+ Enables UART hardware flow control, CTS and RTS lines.
+ 0: Disable, 1:Enable
+**/
+ UINT8 PcdSerialIo2ndUartAutoFlow;
+
+/** Offset 0x007C - PcdSerialIo2ndUartRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART
+**/
+ UINT32 PcdSerialIo2ndUartRxPinMux;
+
+/** Offset 0x0080 - PcdSerialIo2ndUartTxPinMux - FSPT
+ Select TX pin muxing for SerialIo UART
+**/
+ UINT32 PcdSerialIo2ndUartTxPinMux;
+
+/** Offset 0x0084 - PcdSerialIo2ndUartRtsPinMux - FSPT
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIo2ndUartRtsPinMux;
+
+/** Offset 0x0088 - PcdSerialIo2ndUartCtsPinMux - FSPT
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 PcdSerialIo2ndUartCtsPinMux;
+
+/** Offset 0x008C - PcdSerialIo2ndUartMmioBase - FSPT
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 PcdSerialIo2ndUartMmioBase;
+
+/** Offset 0x0090
+**/
+ UINT32 TopMemoryCacheSize;
+
+/** Offset 0x0094 - FspDebugHandler
+ Optional pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
+**/
+ UINT32 FspDebugHandler;
+
+/** Offset 0x0098
+**/
+ UINT8 UnusedUpdSpace2[4];
+
+/** Offset 0x009C
+**/
+ UINT8 ReservedFsptUpd1[20];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSP_T_CONFIG FsptConfig;
+
+/** Offset 0x00B0
+**/
+ UINT8 UnusedUpdSpace3[6];
+
+/** Offset 0x00B6
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/models/gaze16-3060/FSP/Include/FusaInfoHob.h b/models/gaze16-3060/FSP/Include/FusaInfoHob.h
new file mode 100644
index 0000000..7b65b68
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/FusaInfoHob.h
@@ -0,0 +1,138 @@
+/** @file
+ This file contains definitions required for creation of TGL
+ end-to-end check-the-checker test result hob.
+
+ @copyright
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _FUSA_INFO_HOB_H_
+#define _FUSA_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiFusaInfoGuid;
+
+/**
+ FuSa Info HOB version
+ Use this to compare to the HOB retrieved from the FSP for the
+ exact match
+**/
+#define FUSA_INFO_VERSION 0x00000100
+
+/** Constants used for FUSA_TEST_RESULT->CheckResults[] and
+ * FUSA_TEST_RESULT->TestResult */
+/**@defgroup ResultConstant Check Result Constants*/
+/**@{*/
+#define FUSA_TEST_DEVICE_NOTAVAILABLE 0xFF /**TestNumber will have this value.
+
+ @note While the core4-7 (cbo4-7) that are strictly related to
+ the TGL-H are listed, there are not within the
+ implementation scope and validation scope yet.
+**/
+typedef enum
+{
+ FusaTestNumMc0Cmi = 0, ///
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination and voltage tolerance.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 2;
+ UINT32 RsvdBits : 17; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+
+
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ ///
+ /// Deprecated settings. Maintained only for compatibility.
+ ///
+ GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
+ GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
+ GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
+ GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
+
+ ///
+ /// New GPIO reset configuration options
+ ///
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Set GPIO termination and Pad Tolerance (applicable only for some pads)
+ Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F,
+ GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
+ GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioLockPadConfig and GpioLockOutputState can be OR'ed.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controllable
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad.
+**/
+typedef enum {
+ GpioLockDefault = 0x0, ///< Leave lock setting unmodified
+ GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
+ GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/models/gaze16-3060/FSP/Include/GpioSampleDef.h b/models/gaze16-3060/FSP/Include/GpioSampleDef.h
new file mode 100644
index 0000000..b5f2951
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/GpioSampleDef.h
@@ -0,0 +1,359 @@
+/** @file
+
+ @copyright
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __GPIOCONFIG_H__
+#define __GPIOCONFIG_H__
+#include
+#include
+#include
+
+/*
+ SKL LP GPIO pins
+ Use below for functions from PCH GPIO Lib which
+ require GpioPad as argument. Encoding used here
+ has all information required by library functions
+*/
+#define GPIO_SKL_LP_GPP_A0 0x02000000
+#define GPIO_SKL_LP_GPP_A1 0x02000001
+#define GPIO_SKL_LP_GPP_A2 0x02000002
+#define GPIO_SKL_LP_GPP_A3 0x02000003
+#define GPIO_SKL_LP_GPP_A4 0x02000004
+#define GPIO_SKL_LP_GPP_A5 0x02000005
+#define GPIO_SKL_LP_GPP_A6 0x02000006
+#define GPIO_SKL_LP_GPP_A7 0x02000007
+#define GPIO_SKL_LP_GPP_A8 0x02000008
+#define GPIO_SKL_LP_GPP_A9 0x02000009
+#define GPIO_SKL_LP_GPP_A10 0x0200000A
+#define GPIO_SKL_LP_GPP_A11 0x0200000B
+#define GPIO_SKL_LP_GPP_A12 0x0200000C
+#define GPIO_SKL_LP_GPP_A13 0x0200000D
+#define GPIO_SKL_LP_GPP_A14 0x0200000E
+#define GPIO_SKL_LP_GPP_A15 0x0200000F
+#define GPIO_SKL_LP_GPP_A16 0x02000010
+#define GPIO_SKL_LP_GPP_A17 0x02000011
+#define GPIO_SKL_LP_GPP_A18 0x02000012
+#define GPIO_SKL_LP_GPP_A19 0x02000013
+#define GPIO_SKL_LP_GPP_A20 0x02000014
+#define GPIO_SKL_LP_GPP_A21 0x02000015
+#define GPIO_SKL_LP_GPP_A22 0x02000016
+#define GPIO_SKL_LP_GPP_A23 0x02000017
+#define GPIO_SKL_LP_GPP_B0 0x02010000
+#define GPIO_SKL_LP_GPP_B1 0x02010001
+#define GPIO_SKL_LP_GPP_B2 0x02010002
+#define GPIO_SKL_LP_GPP_B3 0x02010003
+#define GPIO_SKL_LP_GPP_B4 0x02010004
+#define GPIO_SKL_LP_GPP_B5 0x02010005
+#define GPIO_SKL_LP_GPP_B6 0x02010006
+#define GPIO_SKL_LP_GPP_B7 0x02010007
+#define GPIO_SKL_LP_GPP_B8 0x02010008
+#define GPIO_SKL_LP_GPP_B9 0x02010009
+#define GPIO_SKL_LP_GPP_B10 0x0201000A
+#define GPIO_SKL_LP_GPP_B11 0x0201000B
+#define GPIO_SKL_LP_GPP_B12 0x0201000C
+#define GPIO_SKL_LP_GPP_B13 0x0201000D
+#define GPIO_SKL_LP_GPP_B14 0x0201000E
+#define GPIO_SKL_LP_GPP_B15 0x0201000F
+#define GPIO_SKL_LP_GPP_B16 0x02010010
+#define GPIO_SKL_LP_GPP_B17 0x02010011
+#define GPIO_SKL_LP_GPP_B18 0x02010012
+#define GPIO_SKL_LP_GPP_B19 0x02010013
+#define GPIO_SKL_LP_GPP_B20 0x02010014
+#define GPIO_SKL_LP_GPP_B21 0x02010015
+#define GPIO_SKL_LP_GPP_B22 0x02010016
+#define GPIO_SKL_LP_GPP_B23 0x02010017
+#define GPIO_SKL_LP_GPP_C0 0x02020000
+#define GPIO_SKL_LP_GPP_C1 0x02020001
+#define GPIO_SKL_LP_GPP_C2 0x02020002
+#define GPIO_SKL_LP_GPP_C3 0x02020003
+#define GPIO_SKL_LP_GPP_C4 0x02020004
+#define GPIO_SKL_LP_GPP_C5 0x02020005
+#define GPIO_SKL_LP_GPP_C6 0x02020006
+#define GPIO_SKL_LP_GPP_C7 0x02020007
+#define GPIO_SKL_LP_GPP_C8 0x02020008
+#define GPIO_SKL_LP_GPP_C9 0x02020009
+#define GPIO_SKL_LP_GPP_C10 0x0202000A
+#define GPIO_SKL_LP_GPP_C11 0x0202000B
+#define GPIO_SKL_LP_GPP_C12 0x0202000C
+#define GPIO_SKL_LP_GPP_C13 0x0202000D
+#define GPIO_SKL_LP_GPP_C14 0x0202000E
+#define GPIO_SKL_LP_GPP_C15 0x0202000F
+#define GPIO_SKL_LP_GPP_C16 0x02020010
+#define GPIO_SKL_LP_GPP_C17 0x02020011
+#define GPIO_SKL_LP_GPP_C18 0x02020012
+#define GPIO_SKL_LP_GPP_C19 0x02020013
+#define GPIO_SKL_LP_GPP_C20 0x02020014
+#define GPIO_SKL_LP_GPP_C21 0x02020015
+#define GPIO_SKL_LP_GPP_C22 0x02020016
+#define GPIO_SKL_LP_GPP_C23 0x02020017
+#define GPIO_SKL_LP_GPP_D0 0x02030000
+#define GPIO_SKL_LP_GPP_D1 0x02030001
+#define GPIO_SKL_LP_GPP_D2 0x02030002
+#define GPIO_SKL_LP_GPP_D3 0x02030003
+#define GPIO_SKL_LP_GPP_D4 0x02030004
+#define GPIO_SKL_LP_GPP_D5 0x02030005
+#define GPIO_SKL_LP_GPP_D6 0x02030006
+#define GPIO_SKL_LP_GPP_D7 0x02030007
+#define GPIO_SKL_LP_GPP_D8 0x02030008
+#define GPIO_SKL_LP_GPP_D9 0x02030009
+#define GPIO_SKL_LP_GPP_D10 0x0203000A
+#define GPIO_SKL_LP_GPP_D11 0x0203000B
+#define GPIO_SKL_LP_GPP_D12 0x0203000C
+#define GPIO_SKL_LP_GPP_D13 0x0203000D
+#define GPIO_SKL_LP_GPP_D14 0x0203000E
+#define GPIO_SKL_LP_GPP_D15 0x0203000F
+#define GPIO_SKL_LP_GPP_D16 0x02030010
+#define GPIO_SKL_LP_GPP_D17 0x02030011
+#define GPIO_SKL_LP_GPP_D18 0x02030012
+#define GPIO_SKL_LP_GPP_D19 0x02030013
+#define GPIO_SKL_LP_GPP_D20 0x02030014
+#define GPIO_SKL_LP_GPP_D21 0x02030015
+#define GPIO_SKL_LP_GPP_D22 0x02030016
+#define GPIO_SKL_LP_GPP_D23 0x02030017
+#define GPIO_SKL_LP_GPP_E0 0x02040000
+#define GPIO_SKL_LP_GPP_E1 0x02040001
+#define GPIO_SKL_LP_GPP_E2 0x02040002
+#define GPIO_SKL_LP_GPP_E3 0x02040003
+#define GPIO_SKL_LP_GPP_E4 0x02040004
+#define GPIO_SKL_LP_GPP_E5 0x02040005
+#define GPIO_SKL_LP_GPP_E6 0x02040006
+#define GPIO_SKL_LP_GPP_E7 0x02040007
+#define GPIO_SKL_LP_GPP_E8 0x02040008
+#define GPIO_SKL_LP_GPP_E9 0x02040009
+#define GPIO_SKL_LP_GPP_E10 0x0204000A
+#define GPIO_SKL_LP_GPP_E11 0x0204000B
+#define GPIO_SKL_LP_GPP_E12 0x0204000C
+#define GPIO_SKL_LP_GPP_E13 0x0204000D
+#define GPIO_SKL_LP_GPP_E14 0x0204000E
+#define GPIO_SKL_LP_GPP_E15 0x0204000F
+#define GPIO_SKL_LP_GPP_E16 0x02040010
+#define GPIO_SKL_LP_GPP_E17 0x02040011
+#define GPIO_SKL_LP_GPP_E18 0x02040012
+#define GPIO_SKL_LP_GPP_E19 0x02040013
+#define GPIO_SKL_LP_GPP_E20 0x02040014
+#define GPIO_SKL_LP_GPP_E21 0x02040015
+#define GPIO_SKL_LP_GPP_E22 0x02040016
+#define GPIO_SKL_LP_GPP_E23 0x02040017
+#define GPIO_SKL_LP_GPP_F0 0x02050000
+#define GPIO_SKL_LP_GPP_F1 0x02050001
+#define GPIO_SKL_LP_GPP_F2 0x02050002
+#define GPIO_SKL_LP_GPP_F3 0x02050003
+#define GPIO_SKL_LP_GPP_F4 0x02050004
+#define GPIO_SKL_LP_GPP_F5 0x02050005
+#define GPIO_SKL_LP_GPP_F6 0x02050006
+#define GPIO_SKL_LP_GPP_F7 0x02050007
+#define GPIO_SKL_LP_GPP_F8 0x02050008
+#define GPIO_SKL_LP_GPP_F9 0x02050009
+#define GPIO_SKL_LP_GPP_F10 0x0205000A
+#define GPIO_SKL_LP_GPP_F11 0x0205000B
+#define GPIO_SKL_LP_GPP_F12 0x0205000C
+#define GPIO_SKL_LP_GPP_F13 0x0205000D
+#define GPIO_SKL_LP_GPP_F14 0x0205000E
+#define GPIO_SKL_LP_GPP_F15 0x0205000F
+#define GPIO_SKL_LP_GPP_F16 0x02050010
+#define GPIO_SKL_LP_GPP_F17 0x02050011
+#define GPIO_SKL_LP_GPP_F18 0x02050012
+#define GPIO_SKL_LP_GPP_F19 0x02050013
+#define GPIO_SKL_LP_GPP_F20 0x02050014
+#define GPIO_SKL_LP_GPP_F21 0x02050015
+#define GPIO_SKL_LP_GPP_F22 0x02050016
+#define GPIO_SKL_LP_GPP_F23 0x02050017
+#define GPIO_SKL_LP_GPP_G0 0x02060000
+#define GPIO_SKL_LP_GPP_G1 0x02060001
+#define GPIO_SKL_LP_GPP_G2 0x02060002
+#define GPIO_SKL_LP_GPP_G3 0x02060003
+#define GPIO_SKL_LP_GPP_G4 0x02060004
+#define GPIO_SKL_LP_GPP_G5 0x02060005
+#define GPIO_SKL_LP_GPP_G6 0x02060006
+#define GPIO_SKL_LP_GPP_G7 0x02060007
+#define GPIO_SKL_LP_GPD0 0x02070000
+#define GPIO_SKL_LP_GPD1 0x02070001
+#define GPIO_SKL_LP_GPD2 0x02070002
+#define GPIO_SKL_LP_GPD3 0x02070003
+#define GPIO_SKL_LP_GPD4 0x02070004
+#define GPIO_SKL_LP_GPD5 0x02070005
+#define GPIO_SKL_LP_GPD6 0x02070006
+#define GPIO_SKL_LP_GPD7 0x02070007
+#define GPIO_SKL_LP_GPD8 0x02070008
+#define GPIO_SKL_LP_GPD9 0x02070009
+#define GPIO_SKL_LP_GPD10 0x0207000A
+#define GPIO_SKL_LP_GPD11 0x0207000B
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+//Sample GPIO Table
+
+static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
+{
+//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
+//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
+ {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+ {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+ {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
+ {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+ {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+ {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
+ {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
+ {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
+ {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
+ {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
+ {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
+ {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
+ {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
+ {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
+ {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
+ {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
+ {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
+ {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
+ {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
+ {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
+ // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
+ // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+ // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+ // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+ // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+ {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
+ {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
+ {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
+ {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
+ {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
+ {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+ {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
+ {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+ {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
+ {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+ {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+ {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+ {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+ {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
+ {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
+ {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+ {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
+ {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
+ {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+ {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
+ {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
+ {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
+ {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
+ {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
+ {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+ {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+ {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+ {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+ {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
+ {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
+ {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
+ {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
+ {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
+ {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
+ {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
+ {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
+ {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
+ {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
+ {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
+ {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
+ {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
+ {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
+ {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
+ {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
+ {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
+ {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
+ {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
+ {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
+ {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
+ {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+ {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+ {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+ {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
+ {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
+ {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
+ {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
+ {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
+ {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
+ {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
+ {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+ {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
+ {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+ {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
+ {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
+ {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+ {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
+ {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
+ {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
+ {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
+ {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+ {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
+ {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
+ {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
+ {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
+ {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+ {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
+ {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
+ {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
+ {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
+ {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
+ {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
+ {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
+ {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+ {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+ {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+ {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+ {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+ {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+ {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+ {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+ {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
+ {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
+ {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
+ {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
+ {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
+ {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
+ {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
+ {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
+ {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
+ {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
+ {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
+ {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+ {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
+ {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
+ {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
+ {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
+ {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
+ {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
+ {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
+ {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
+ {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
+ {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
+ {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+ {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
+ {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
+ {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
+ {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
+ {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+ {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
+ {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
+ {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
+ {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
+ {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
+};
+
+#endif //_GPIO_CONFIG_H_
diff --git a/models/gaze16-3060/FSP/Include/MemInfoHob.h b/models/gaze16-3060/FSP/Include/MemInfoHob.h
new file mode 100644
index 0000000..329bf34
--- /dev/null
+++ b/models/gaze16-3060/FSP/Include/MemInfoHob.h
@@ -0,0 +1,281 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ @copyright
+ Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_TRACE_CACHE_TYPE 3
+
+#define MAX_NODE 2
+#define MAX_CH 4
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
+ #ifndef INT32_MAX
+ #define INT32_MAX (0x7FFFFFFF)
+ #endif //INT32_MAX
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#ifndef MRC_DDR_TYPE_WIO2
+#define MRC_DDR_TYPE_WIO2 4
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 5
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT64 BaseAddress; ///< Trace Base Address
+ UINT64 TotalSize; ///< Total Trace Region of Same Cache type
+ UINT8 CacheType; ///< Trace Cache Type
+ UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
+ UINT8 Rsvd[2];
+} PSMI_MEM_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ Revision 1:
+ - Initial version.
+ Revision 2:
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT64 PrmrrBase;
+ UINT32 PramSize;
+ UINT64 PramBase;
+ UINT64 DismLimit;
+ UINT64 DismBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+ PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
diff --git a/models/gaze16-3060/FSP/LICENSE b/models/gaze16-3060/FSP/LICENSE
new file mode 100644
index 0000000..ef265ab
--- /dev/null
+++ b/models/gaze16-3060/FSP/LICENSE
@@ -0,0 +1,46 @@
+************************************************************************
+** **
+** **
+** IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING **
+** **
+** ANY PORTION OF THE SOFTWARE **
+** **
+************************************************************************
+
+Copyright (c) 2018 Intel Corporation.
+All rights reserved.
+
+Redistribution.
+
+Redistribution and use in binary form, without modification, are permitted
+provided that the following conditions are met:
+
+- Redistributions must reproduce the above copyright notice and the
+following disclaimer in the documentation and/or other materials provided
+with the distribution.
+
+- Neither the name of Intel Corporation nor the names of its suppliers
+may be used to endorse or promote products derived from this software
+without specific prior written permission.
+
+- No reverse engineering, decompilation, or disassembly of this software
+is permitted.
+
+"Binary form" includes any format that is commonly used for electronic
+conveyance that is a reversible, bit-exact translation of binary
+representation to ASCII or ISO text, for example "uuencode".
+
+DISCLAIMER.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/models/gaze16-3060/IntelGopDriver.efi b/models/gaze16-3060/IntelGopDriver.efi
new file mode 100644
index 0000000..c0cad76
--- /dev/null
+++ b/models/gaze16-3060/IntelGopDriver.efi
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:369d366e937b60784a38b9b46a701ca9c6f5441086670b1ec359e6c558fea605
+size 159776
diff --git a/models/gaze16-3060/IntelGopDriver.inf b/models/gaze16-3060/IntelGopDriver.inf
new file mode 100644
index 0000000..39b2eb9
--- /dev/null
+++ b/models/gaze16-3060/IntelGopDriver.inf
@@ -0,0 +1,9 @@
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IntelGopDriver
+ FILE_GUID = 767222f4-a9f4-41ba-9faa-edaa1405a486
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+[Binaries.X64]
+ PE32|IntelGopDriver.efi|*
diff --git a/models/gaze16-3060/README.md b/models/gaze16-3060/README.md
new file mode 100644
index 0000000..e7d7554
--- /dev/null
+++ b/models/gaze16-3060/README.md
@@ -0,0 +1,12 @@
+# System76 Gazelle (gaze16)
+
+## Contents
+
+- [EC](./ec.rom)
+ - *Read Error: No such file or directory (os error 2)*
+- [FD](./fd.rom)
+ - Size: 4 KB
+ - HAP: false
+- [ME](./me.rom)
+ - Size: 5116 KB
+ - Version: 15.0.30.1716
diff --git a/models/gaze16-3060/README.md.in b/models/gaze16-3060/README.md.in
new file mode 100644
index 0000000..42ee48c
--- /dev/null
+++ b/models/gaze16-3060/README.md.in
@@ -0,0 +1 @@
+# System76 Gazelle (gaze16)
diff --git a/models/gaze16-3060/chip.txt b/models/gaze16-3060/chip.txt
new file mode 100644
index 0000000..9b1d0de
--- /dev/null
+++ b/models/gaze16-3060/chip.txt
@@ -0,0 +1 @@
+GD25Q127C/GD25Q128C
diff --git a/models/gaze16-3060/coreboot-collector.txt b/models/gaze16-3060/coreboot-collector.txt
new file mode 100644
index 0000000..795ad3e
--- /dev/null
+++ b/models/gaze16-3060/coreboot-collector.txt
@@ -0,0 +1,313 @@
+## PCI ##
+PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x9A36, Revision 0x05
+PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0x9A01, Revision 0x05
+PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x9A60, Revision 0x01
+PCI Device: 0000:00:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x9A11, Revision 0x05
+PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0x9A0D, Revision 0x01
+PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0x9A17, Revision 0x05
+PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0x9A0B, Revision 0x00
+PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x43ED, Revision 0x11
+PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x43EF, Revision 0x11
+PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x43F0, Revision 0x11
+PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x43E8, Revision 0x11
+PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x43E0, Revision 0x11
+PCI Device: 0000:00:17.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
+PCI Device: 0000:00:19.0: Class 0x000C8000, Vendor 0x8086, Device 0x43AD, Revision 0x11
+PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x43BC, Revision 0x11
+PCI Device: 0000:00:1c.6: Class 0x00060400, Vendor 0x8086, Device 0x43BE, Revision 0x11
+PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x438B, Revision 0x11
+PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x43C8, Revision 0x11
+PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x43A3, Revision 0x11
+PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x43A4, Revision 0x11
+PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2520, Revision 0xA1
+PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x228E, Revision 0xA1
+PCI Device: 0000:02:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
+PCI Device: 0000:03:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
+PCI Device: 10000:e0:06.0: Class 0x00060400, Vendor 0x8086, Device 0x9A0F, Revision 0x05
+PCI Device: 10000:e0:17.0: Class 0x00010601, Vendor 0x8086, Device 0x43D3, Revision 0x11
+PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x15B7, Device 0x5009, Revision 0x01
+## GPIO ##
+500 Series PCH
+GPP_A0 (0x6E,0x10) 0x44000700 0x00003018 0x00000100 0x00000000
+GPP_A1 (0x6E,0x12) 0x44000702 0x00003019 0x00000100 0x00000000
+GPP_A2 (0x6E,0x14) 0x44000600 0x00003020 0x00000100 0x00000000
+GPP_A3 (0x6E,0x16) 0x44000700 0x00003021 0x00000100 0x00000000
+GPP_A4 (0x6E,0x18) 0x44000700 0x00003022 0x00000100 0x00000000
+GPP_A5 (0x6E,0x1A) 0x44000700 0x00001023 0x00000100 0x00000000
+GPP_A6 (0x6E,0x1C) 0x44000700 0x00000024 0x00000100 0x00000000
+GPP_A7 (0x6E,0x1E) 0x44000102 0x00003025 0x00000100 0x00000000
+GPP_A8 (0x6E,0x20) 0x44000102 0x00003026 0x00000100 0x00000000
+GPP_A9 (0x6E,0x22) 0x44000102 0x00003027 0x00000100 0x00000000
+GPP_A10 (0x6E,0x24) 0x44000102 0x00003028 0x00000100 0x00000000
+GPP_A11 (0x6E,0x26) 0x80100100 0x00000029 0x00000100 0x00000000
+GPP_A12 (0x6E,0x28) 0x44000102 0x0000302a 0x00000100 0x00000000
+GPP_A13 (0x6E,0x2A) 0x44000102 0x0000302b 0x00000100 0x00000000
+GPP_A14 (0x6E,0x2C) 0x44000102 0x00000030 0x00000100 0x00000000
+GPP_R0 (0x6E,0x32) 0x44000500 0x00000031 0x00000000 0x00000000
+GPP_R1 (0x6E,0x34) 0x44000500 0x00003c32 0x00000000 0x00000000
+GPP_R2 (0x6E,0x36) 0x44000500 0x00003c33 0x00000000 0x00000000
+GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
+GPP_R4 (0x6E,0x3A) 0x44000500 0x00000035 0x00000000 0x00000000
+GPP_R5 (0x6E,0x3C) 0x44000502 0x00000036 0x00000000 0x00000000
+GPP_R6 (0x6E,0x3E) 0x44000102 0x00000037 0x00000000 0x00000000
+GPP_R7 (0x6E,0x40) 0x44000102 0x00000038 0x00000000 0x00000000
+GPP_R8 (0x6E,0x42) 0x44000102 0x00000039 0x00000000 0x00000000
+GPP_R9 (0x6E,0x44) 0x44000102 0x0000003a 0x00000000 0x00000000
+GPP_R10 (0x6E,0x46) 0x44000102 0x0000003b 0x00000000 0x00000000
+GPP_R11 (0x6E,0x48) 0x44000102 0x0000003c 0x00000000 0x00000000
+GPP_R12 (0x6E,0x4A) 0x40100102 0x0000003d 0x00000000 0x00000000
+GPP_R13 (0x6E,0x4C) 0x44000102 0x0000003e 0x00000000 0x00000000
+GPP_R14 (0x6E,0x4E) 0x44000102 0x0000003f 0x00000000 0x00000000
+GPP_R15 (0x6E,0x50) 0x44000102 0x00000040 0x00000000 0x00000000
+GPP_R16 (0x6E,0x52) 0x44000102 0x00000041 0x00000000 0x00000000
+GPP_R17 (0x6E,0x54) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_R18 (0x6E,0x56) 0x44000102 0x00000043 0x00000000 0x00000000
+GPP_R19 (0x6E,0x58) 0x44000102 0x00000044 0x00000000 0x00000000
+GPP_B0 (0x6E,0x5A) 0x40100102 0x00000045 0x00000000 0x00000000
+GPP_B1 (0x6E,0x5C) 0x44000102 0x00000046 0x00000000 0x00000000
+GPP_B2 (0x6E,0x5E) 0x44000102 0x00000047 0x00000000 0x00000000
+GPP_B3 (0x6E,0x60) 0x44000201 0x00000048 0x00000000 0x00000000
+GPP_B4 (0x6E,0x62) 0x44000102 0x00000049 0x00000000 0x00000000
+GPP_B5 (0x6E,0x64) 0x44000102 0x0000004a 0x00000000 0x00000000
+GPP_B6 (0x6E,0x66) 0x44000102 0x0000004b 0x00000000 0x00000000
+GPP_B7 (0x6E,0x68) 0x44000702 0x0000004c 0x00000000 0x00000000
+GPP_B8 (0x6E,0x6A) 0x44000702 0x0000004d 0x00000000 0x00000000
+GPP_B9 (0x6E,0x6C) 0x44000102 0x0000004e 0x00000000 0x00000000
+GPP_B10 (0x6E,0x6E) 0x44000102 0x0000004f 0x00000000 0x00000000
+GPP_B11 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
+GPP_B12 (0x6E,0x72) 0x44000700 0x00000051 0x00000000 0x00000000
+GPP_B13 (0x6E,0x74) 0x44000700 0x00000052 0x00000000 0x00000000
+GPP_B14 (0x6E,0x76) 0x44000500 0x00000053 0x00000000 0x00000000
+GPP_B15 (0x6E,0x78) 0x44000201 0x00000054 0x00000000 0x00000000
+GPP_B16 (0x6E,0x7A) 0x44000102 0x00000055 0x00000000 0x00000000
+GPP_B17 (0x6E,0x7C) 0x44000102 0x00000056 0x00000000 0x00000000
+GPP_B18 (0x6E,0x7E) 0x44000102 0x00000057 0x00000000 0x00000000
+GPP_B19 (0x6E,0x80) 0x44000102 0x00000058 0x00000000 0x00000000
+GPP_B20 (0x6E,0x82) 0x44000102 0x00000059 0x00000000 0x00000000
+GPP_B21 (0x6E,0x84) 0x44000102 0x0000005a 0x00000000 0x00000000
+GPP_B22 (0x6E,0x86) 0x44000102 0x0000005b 0x00000000 0x00000000
+GPP_B23 (0x6E,0x88) 0x44000102 0x0000005c 0x00000000 0x00000000
+GPP_D0 (0x6D,0x00) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_D1 (0x6D,0x02) 0x44000102 0x0000005e 0x00000000 0x00000000
+GPP_D2 (0x6D,0x04) 0x44000102 0x0000005f 0x00000000 0x00000000
+GPP_D3 (0x6D,0x06) 0x44000102 0x00000060 0x00000000 0x00000000
+GPP_D4 (0x6D,0x08) 0x44000502 0x00000061 0x00000000 0x00000000
+GPP_D5 (0x6D,0x0A) 0x44000900 0x00000062 0x00000000 0x00000000
+GPP_D6 (0x6D,0x0C) 0x44000d00 0x00000063 0x00000000 0x00000000
+GPP_D7 (0x6D,0x0E) 0x44000102 0x00000064 0x00000000 0x00000000
+GPP_D8 (0x6D,0x10) 0x44000102 0x00000065 0x00000000 0x00000000
+GPP_D9 (0x6D,0x12) 0x44000502 0x00000066 0x00000000 0x00000000
+GPP_D10 (0x6D,0x14) 0x44000502 0x00000067 0x00000000 0x00000000
+GPP_D11 (0x6D,0x16) 0x44000102 0x00003c68 0x00000000 0x00000000
+GPP_D12 (0x6D,0x18) 0x44000102 0x00000069 0x00000000 0x00000000
+GPP_D13 (0x6D,0x1A) 0x44000102 0x0000006a 0x00000000 0x00000000
+GPP_D14 (0x6D,0x1C) 0x44000102 0x0000006b 0x00000000 0x00000000
+GPP_D15 (0x6D,0x1E) 0x44000502 0x0000006c 0x00000000 0x00000000
+GPP_D16 (0x6D,0x20) 0x44000102 0x0000006d 0x00000000 0x00000000
+GPP_D17 (0x6D,0x22) 0x44000102 0x0000006e 0x00000000 0x00000000
+GPP_D18 (0x6D,0x24) 0x44000102 0x0000006f 0x00000000 0x00000000
+GPP_D19 (0x6D,0x26) 0x44000102 0x00000070 0x00000000 0x00000000
+GPP_D20 (0x6D,0x28) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_D21 (0x6D,0x2A) 0x44000102 0x00000072 0x00000000 0x00000000
+GPP_D22 (0x6D,0x2C) 0x44000102 0x00000073 0x00000000 0x00000000
+GPP_D23 (0x6D,0x2E) 0x44000201 0x00000074 0x00000000 0x00000000
+GPP_C0 (0x6D,0x34) 0x44000502 0x00000075 0x00000000 0x00000000
+GPP_C1 (0x6D,0x36) 0x44000502 0x00000076 0x00000000 0x00000000
+GPP_C2 (0x6D,0x38) 0x44000102 0x00000077 0x00000800 0x00000000
+GPP_C3 (0x6D,0x3A) 0x44000102 0x00000018 0x00000000 0x00000000
+GPP_C4 (0x6D,0x3C) 0x44000102 0x00000019 0x00000000 0x00000000
+GPP_C5 (0x6D,0x3E) 0x44000100 0x00000020 0x00000000 0x00000000
+GPP_C6 (0x6D,0x40) 0x44000102 0x00000021 0x00000000 0x00000000
+GPP_C7 (0x6D,0x42) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_C8 (0x6D,0x44) 0x44000102 0x00000023 0x00000000 0x00000000
+GPP_C9 (0x6D,0x46) 0x44000100 0x00000024 0x00000000 0x00000000
+GPP_C10 (0x6D,0x48) 0x44000100 0x00000025 0x00000000 0x00000000
+GPP_C11 (0x6D,0x4A) 0x44000100 0x00000026 0x00000000 0x00000000
+GPP_C12 (0x6D,0x4C) 0x44000102 0x00000027 0x00000000 0x00000000
+GPP_C13 (0x6D,0x4E) 0x44000102 0x00000028 0x00000000 0x00000000
+GPP_C14 (0x6D,0x50) 0x44000102 0x00000029 0x00000000 0x00000000
+GPP_C15 (0x6D,0x52) 0x44000102 0x0000002a 0x00000000 0x00000000
+GPP_C16 (0x6D,0x54) 0x44000502 0x0000002b 0x00000000 0x00000000
+GPP_C17 (0x6D,0x56) 0x44000502 0x00000030 0x00000000 0x00000000
+GPP_C18 (0x6D,0x58) 0x44000102 0x00000031 0x00000000 0x00000000
+GPP_C19 (0x6D,0x5A) 0x44000102 0x00000032 0x00000000 0x00000000
+GPP_C20 (0x6D,0x5C) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_C21 (0x6D,0x5E) 0x44000102 0x00000034 0x00000000 0x00000000
+GPP_C22 (0x6D,0x60) 0x44000201 0x00000035 0x00000000 0x00000000
+GPP_C23 (0x6D,0x62) 0x44000102 0x00000036 0x00000000 0x00000000
+GPP_S0 (0x6D,0x64) 0x44000100 0x01800037 0x00000000 0x00000000
+GPP_S1 (0x6D,0x66) 0x44000100 0x01800038 0x00000000 0x00000000
+GPP_S2 (0x6D,0x68) 0x44000100 0x01800039 0x00000000 0x00000000
+GPP_S3 (0x6D,0x6A) 0x44000100 0x0180003a 0x00000000 0x00000000
+GPP_S4 (0x6D,0x6C) 0x44000100 0x0180003b 0x00000000 0x00000000
+GPP_S5 (0x6D,0x6E) 0x44000100 0x0180003c 0x00000000 0x00000000
+GPP_S6 (0x6D,0x70) 0x44000100 0x0180003d 0x00000000 0x00000000
+GPP_S7 (0x6D,0x72) 0x44000100 0x0180003e 0x00000000 0x00000000
+GPP_G0 (0x6D,0x74) 0x44000102 0x0000003f 0x00000000 0x00000000
+GPP_G1 (0x6D,0x76) 0x44000102 0x00000040 0x00000000 0x00000000
+GPP_G2 (0x6D,0x78) 0x44000100 0x00001041 0x00000000 0x00000000
+GPP_G3 (0x6D,0x7A) 0x44000102 0x00000042 0x00000000 0x00000000
+GPP_G4 (0x6D,0x7C) 0x44000102 0x00000043 0x00000000 0x00000000
+GPP_G5 (0x6D,0x7E) 0x44000102 0x00000044 0x00000000 0x00000000
+GPP_G6 (0x6D,0x80) 0x44000102 0x00000045 0x00000000 0x00000000
+GPP_G7 (0x6D,0x82) 0x44000102 0x00000046 0x00000000 0x00000000
+GPP_G8 (0x6D,0x84) 0x44000102 0x00003c47 0x00000100 0x00000000
+GPP_G9 (0x6D,0x86) 0x44000102 0x00000048 0x00000100 0x00000000
+GPP_G10 (0x6D,0x88) 0x44000102 0x00003c49 0x00000100 0x00000000
+GPP_G11 (0x6D,0x8A) 0x44000102 0x0000004a 0x00000100 0x00000000
+GPP_G12 (0x6D,0x8C) 0x44000300 0x00003c4b 0x00000000 0x00000000
+GPP_G13 (0x6D,0x8E) 0x44000300 0x00003c4c 0x00000000 0x00000000
+GPP_G14 (0x6D,0x90) 0x44000102 0x00003c4d 0x00000100 0x00000000
+GPP_G15 (0x6D,0x92) 0x44000102 0x0000004e 0x00000100 0x00000000
+GPD0 (0x6C,0x00) 0x04000702 0x00003050 0x00000000 0x00000000
+GPD1 (0x6C,0x02) 0x04000702 0x00003c51 0x00000000 0x00000000
+GPD2 (0x6C,0x04) 0x04000102 0x00003c52 0x00000000 0x00000000
+GPD3 (0x6C,0x06) 0x04000702 0x00003053 0x00000010 0x00000000
+GPD4 (0x6C,0x08) 0x04000600 0x00000054 0x00000000 0x00000000
+GPD5 (0x6C,0x0A) 0x04000600 0x00000055 0x00000000 0x00000000
+GPD6 (0x6C,0x0C) 0x04000600 0x00000056 0x00000000 0x00000000
+GPD7 (0x6C,0x0E) 0x04000100 0x00000057 0x00000000 0x00000000
+GPD8 (0x6C,0x10) 0x04000700 0x00000058 0x00000000 0x00000000
+GPD9 (0x6C,0x12) 0x04000200 0x00000059 0x00000000 0x00000000
+GPD10 (0x6C,0x14) 0x04000600 0x0000005a 0x00000000 0x00000000
+GPD11 (0x6C,0x16) 0x04000102 0x0000005b 0x00000000 0x00000000
+GPD12 (0x6C,0x18) 0x04000300 0x0000005c 0x00000000 0x00000000
+GPP_E0 (0x6B,0x00) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_E1 (0x6B,0x02) 0x44000702 0x0000305e 0x00000000 0x00000000
+GPP_E2 (0x6B,0x04) 0x44000102 0x0000005f 0x00000000 0x00000000
+GPP_E3 (0x6B,0x06) 0x44000102 0x00000060 0x00000000 0x00000000
+GPP_E4 (0x6B,0x08) 0x04000500 0x00000061 0x00000000 0x00000000
+GPP_E5 (0x6B,0x0A) 0x44000500 0x00000062 0x00000000 0x00000000
+GPP_E6 (0x6B,0x0C) 0x44000102 0x00000063 0x00000000 0x00000000
+GPP_E7 (0x6B,0x0E) 0x44000102 0x00000064 0x00000000 0x00000000
+GPP_E8 (0x6B,0x10) 0x44000500 0x00000065 0x00000000 0x00000000
+GPP_E9 (0x6B,0x12) 0x44000102 0x00000066 0x00000800 0x00000000
+GPP_E10 (0x6B,0x14) 0x44000102 0x00000067 0x00000800 0x00000000
+GPP_E11 (0x6B,0x16) 0x44000102 0x00000068 0x00000800 0x00000000
+GPP_E12 (0x6B,0x18) 0x44000102 0x00000069 0x00000000 0x00000000
+GPP_F0 (0x6B,0x1A) 0x44000902 0x0000006a 0x00000000 0x00000000
+GPP_F1 (0x6B,0x1C) 0x44000102 0x0000006b 0x00000000 0x00000000
+GPP_F2 (0x6B,0x1E) 0x84000201 0x0000006c 0x00000000 0x00000000
+GPP_F3 (0x6B,0x20) 0x44000201 0x0000006d 0x00000000 0x00000000
+GPP_F4 (0x6B,0x22) 0x44000201 0x0000006e 0x00000000 0x00000000
+GPP_F5 (0x6B,0x24) 0x44000500 0x0000006f 0x00000000 0x00000000
+GPP_F6 (0x6B,0x26) 0x44000102 0x00000070 0x00000000 0x00000000
+GPP_F7 (0x6B,0x28) 0x44000102 0x00000071 0x00000000 0x00000000
+GPP_F8 (0x6B,0x2A) 0x44000201 0x00000072 0x00000000 0x00000000
+GPP_F9 (0x6B,0x2C) 0x44000201 0x00000073 0x00000000 0x00000000
+GPP_F10 (0x6B,0x2E) 0x44000102 0x00000074 0x00000000 0x00000000
+GPP_F11 (0x6B,0x30) 0x44000102 0x00000075 0x00000000 0x00000000
+GPP_F12 (0x6B,0x32) 0x44000102 0x00000076 0x00000000 0x00000000
+GPP_F13 (0x6B,0x34) 0x44000102 0x00000077 0x00000000 0x00000000
+GPP_F14 (0x6B,0x36) 0x44000102 0x00000018 0x00000000 0x00000000
+GPP_F15 (0x6B,0x38) 0x44000100 0x00000019 0x00000000 0x00000000
+GPP_F16 (0x6B,0x3A) 0x44000102 0x00000020 0x00000000 0x00000000
+GPP_F17 (0x6B,0x3C) 0x44000201 0x00000021 0x00000000 0x00000000
+GPP_F18 (0x6B,0x3E) 0x44000102 0x00000022 0x00000000 0x00000000
+GPP_F19 (0x6B,0x40) 0x44000700 0x00000023 0x00000000 0x00000000
+GPP_F20 (0x6B,0x42) 0x44000700 0x00000024 0x00000000 0x00000000
+GPP_F21 (0x6B,0x44) 0x44000700 0x00000025 0x00000000 0x00000000
+GPP_F22 (0x6B,0x46) 0x44000300 0x00000026 0x00000000 0x00000000
+GPP_F23 (0x6B,0x48) 0x44000201 0x00000027 0x00000000 0x00000000
+GPP_H0 (0x6A,0x00) 0x44000102 0x00000024 0x00000000 0x00000000
+GPP_H1 (0x6A,0x02) 0x44000700 0x00000025 0x00000000 0x00000000
+GPP_H2 (0x6A,0x04) 0x44000700 0x00000026 0x00000000 0x00000000
+GPP_H3 (0x6A,0x06) 0x44000702 0x00000027 0x00000000 0x00000000
+GPP_H4 (0x6A,0x08) 0x44000702 0x00000028 0x00000000 0x00000000
+GPP_H5 (0x6A,0x0A) 0x44000102 0x00000029 0x00000000 0x00000000
+GPP_H6 (0x6A,0x0C) 0x44000102 0x0000002a 0x00000000 0x00000000
+GPP_H7 (0x6A,0x0E) 0x44000102 0x0000002b 0x00000000 0x00000000
+GPP_H8 (0x6A,0x10) 0x44000102 0x00000030 0x00000000 0x00000000
+GPP_H9 (0x6A,0x12) 0x44000102 0x00000031 0x00000000 0x00000000
+GPP_H10 (0x6A,0x14) 0x44000102 0x00000032 0x00000000 0x00000000
+GPP_H11 (0x6A,0x16) 0x44000102 0x00000033 0x00000000 0x00000000
+GPP_H12 (0x6A,0x18) 0x44000102 0x00000034 0x00000000 0x00000000
+GPP_H13 (0x6A,0x1A) 0x44000102 0x00000035 0x00000000 0x00000000
+GPP_H14 (0x6A,0x1C) 0x44000102 0x00000036 0x00000000 0x00000000
+GPP_H15 (0x6A,0x1E) 0x84000102 0x00000037 0x00000800 0x00000000
+GPP_H16 (0x6A,0x20) 0x44000102 0x00000038 0x00000000 0x00000000
+GPP_H17 (0x6A,0x22) 0x44000201 0x00000039 0x00000000 0x00000000
+GPP_H18 (0x6A,0x24) 0x44000102 0x0000003a 0x00000000 0x00000000
+GPP_H19 (0x6A,0x26) 0x44000102 0x0000003b 0x00000000 0x00000000
+GPP_H20 (0x6A,0x28) 0x44000102 0x0000003c 0x00000000 0x00000000
+GPP_H21 (0x6A,0x2A) 0x84000102 0x0000003d 0x00000000 0x00000000
+GPP_H22 (0x6A,0x2C) 0x84000102 0x0000003e 0x00000000 0x00000000
+GPP_H23 (0x6A,0x2E) 0x44000201 0x0000003f 0x00000000 0x00000000
+GPP_J0 (0x6A,0x30) 0x44000500 0x04000040 0x00000000 0x00000000
+GPP_J1 (0x6A,0x32) 0x44000700 0x04000041 0x00000000 0x00000000
+GPP_J2 (0x6A,0x34) 0x44000500 0x04000042 0x00000000 0x00000000
+GPP_J3 (0x6A,0x36) 0x44000502 0x04003043 0x00000000 0x00000000
+GPP_J4 (0x6A,0x38) 0x44000500 0x04000044 0x00000000 0x00000000
+GPP_J5 (0x6A,0x3A) 0x44000500 0x04003045 0x00000000 0x00000000
+GPP_J6 (0x6A,0x3C) 0x44000500 0x04000046 0x00000000 0x00000000
+GPP_J7 (0x6A,0x3E) 0x44000500 0x04000047 0x00000000 0x00000000
+GPP_J8 (0x6A,0x40) 0x84000102 0x04000048 0x00000000 0x00000000
+GPP_J9 (0x6A,0x42) 0x44000100 0x04000049 0x00000000 0x00000000
+GPP_K0 (0x6A,0x44) 0x44000200 0x0000004a 0x00000000 0x00000000
+GPP_K1 (0x6A,0x46) 0x44000102 0x0000004b 0x00000000 0x00000000
+GPP_K2 (0x6A,0x48) 0x44000102 0x0000004c 0x00000000 0x00000000
+GPP_K3 (0x6A,0x4A) 0x44000102 0x0000004d 0x00000000 0x00000000
+GPP_K4 (0x6A,0x4C) 0x44000102 0x0000004e 0x00000000 0x00000000
+GPP_K5 (0x6A,0x4E) 0x44000102 0x0000004f 0x00000000 0x00000000
+GPP_K6 (0x6A,0x50) 0x44000702 0x00000050 0x00000000 0x00000000
+GPP_K7 (0x6A,0x52) 0x44000500 0x00000051 0x00000000 0x00000000
+GPP_K8 (0x6A,0x54) 0x44000700 0x00000052 0x00000000 0x00000000
+GPP_K9 (0x6A,0x56) 0x44000700 0x00000053 0x00000000 0x00000000
+GPP_K10 (0x6A,0x58) 0x44000102 0x00000054 0x00000000 0x00000000
+GPP_K11 (0x6A,0x5A) 0x84000100 0x00000055 0x00000000 0x00000000
+GPP_I0 (0x69,0x00) 0x04000702 0x00000056 0x00000000 0x00000000
+GPP_I1 (0x69,0x02) 0x46880100 0x00000057 0x00000000 0x00000000
+GPP_I2 (0x69,0x04) 0x46880100 0x00000058 0x00000000 0x00000000
+GPP_I3 (0x69,0x06) 0x44000102 0x00000059 0x00000000 0x00000000
+GPP_I4 (0x69,0x08) 0x44000102 0x0000005a 0x00000000 0x00000000
+GPP_I5 (0x69,0x0A) 0x44000500 0x0000005b 0x00000000 0x00000000
+GPP_I6 (0x69,0x0C) 0x44000502 0x0000005c 0x00000000 0x00000000
+GPP_I7 (0x69,0x0E) 0x44000102 0x0000005d 0x00000000 0x00000000
+GPP_I8 (0x69,0x10) 0x44000102 0x0000005e 0x00000000 0x00000000
+GPP_I9 (0x69,0x12) 0x44000201 0x0000005f 0x00000000 0x00000000
+GPP_I10 (0x69,0x14) 0x44000200 0x00001060 0x00000000 0x00000000
+GPP_I11 (0x69,0x16) 0x44000902 0x00000061 0x00000000 0x00000000
+GPP_I12 (0x69,0x18) 0x44000902 0x00000062 0x00000000 0x00000000
+GPP_I13 (0x69,0x1A) 0x84000102 0x00000063 0x00000000 0x00000000
+GPP_I14 (0x69,0x1C) 0x84000102 0x00000064 0x00000000 0x00000000
+## HDAUDIO ##
+hdaudioC0D0
+ vendor_name: Realtek
+ chip_name: ALC256
+ vendor_id: 0x10ec0256
+ subsystem_id: 0x155850e2
+ revision_id: 0x100002
+ 0x12: 0x90a60130
+ 0x13: 0x40000000
+ 0x14: 0x90170110
+ 0x18: 0x411111f0
+ 0x19: 0x411111f0
+ 0x1a: 0x02a11040
+ 0x1b: 0x411111f0
+ 0x1d: 0x41789c6d
+ 0x1e: 0x411111f0
+ 0x21: 0x02211020
+hdaudioC0D2
+ vendor_name: Intel
+ chip_name: Tigerlake HDMI
+ vendor_id: 0x80862812
+ subsystem_id: 0x80860101
+ revision_id: 0x100000
+ 0x04: 0x18560010
+ 0x06: 0x18560010
+ 0x08: 0x18560010
+ 0x0a: 0x18560010
+ 0x0b: 0x18560010
+ 0x0c: 0x18560010
+ 0x0d: 0x18560010
+ 0x0e: 0x18560010
+ 0x0f: 0x18560010
+hdaudioC1D0
+ vendor_name: Nvidia
+ chip_name: GPU 9f HDMI/DP
+ vendor_id: 0x10de009f
+ subsystem_id: 0x10de0000
+ revision_id: 0x100100
+ 0x04: 0x185600f0
+ 0x05: 0x185600f0
diff --git a/models/gaze16-3060/coreboot.config b/models/gaze16-3060/coreboot.config
new file mode 100644
index 0000000..83548f9
--- /dev/null
+++ b/models/gaze16-3060/coreboot.config
@@ -0,0 +1,24 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_GAZE16_3060=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_CCACHE=y
+CONFIG_CONSOLE_SERIAL=n
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_FSP_M_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_M.fd"
+CONFIG_FSP_S_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_S.fd"
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
+CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
+CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
+CONFIG_POST_IO=n
+CONFIG_RUN_FSP_GOP=y
+CONFIG_SMMSTORE=y
+CONFIG_SUBSYSTEM_DEVICE_ID=0x50e1
+CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+#CONFIG_CONSOLE_SYSTEM76_EC=y
diff --git a/models/gaze16-3060/ec.config b/models/gaze16-3060/ec.config
new file mode 100644
index 0000000..5529ddf
--- /dev/null
+++ b/models/gaze16-3060/ec.config
@@ -0,0 +1 @@
+BOARD=system76/gaze16-3060
diff --git a/models/gaze16-3060/ecspy.txt b/models/gaze16-3060/ecspy.txt
new file mode 100644
index 0000000..f7876de
--- /dev/null
+++ b/models/gaze16-3060/ecspy.txt
@@ -0,0 +1,89 @@
+id 5570 rev 2
+A0: data 1 mirror 1 pot 0 control 00
+A1: data 0 mirror 0 pot 0 control 00
+A2: data 0 mirror 0 pot 0 control 00
+A3: data 1 mirror 1 pot 0 control 44
+A4: data 1 mirror 1 pot 0 control 00
+A5: data 0 mirror 0 pot 0 control 00
+A6: data 0 mirror 0 pot 0 control 00
+A7: data 1 mirror 1 pot 0 control 00
+B0: data 0 mirror 0 pot 0 control 84
+B1: data 1 mirror 1 pot 0 control 84
+B2: data 1 mirror 1 pot 0 control 84
+B3: data 1 mirror 1 pot 0 control 80
+B4: data 1 mirror 1 pot 0 control 40
+B5: data 1 mirror 1 pot 0 control 80
+B6: data 1 mirror 1 pot 0 control 44
+B7: data 1 mirror 1 pot 0 control 80
+C0: data 1 mirror 1 pot 0 control 80
+C1: data 1 mirror 1 pot 0 control 04
+C2: data 1 mirror 1 pot 0 control 04
+C3: data 0 mirror 0 pot 0 control 04
+C4: data 0 mirror 0 pot 0 control 84
+C5: data 0 mirror 0 pot 0 control 04
+C6: data 1 mirror 1 pot 0 control 40
+C7: data 1 mirror 1 pot 0 control 44
+D0: data 1 mirror 1 pot 0 control 44
+D1: data 1 mirror 1 pot 0 control 44
+D2: data 1 mirror 1 pot 0 control 00
+D3: data 1 mirror 1 pot 0 control 40
+D4: data 1 mirror 1 pot 0 control 40
+D5: data 1 mirror 1 pot 0 control 44
+D6: data 1 mirror 1 pot 0 control 02
+D7: data 0 mirror 0 pot 0 control 02
+E0: data 1 mirror 1 pot 0 control 04
+E1: data 1 mirror 1 pot 0 control 44
+E2: data 0 mirror 0 pot 0 control 84
+E3: data 0 mirror 0 pot 0 control 44
+E4: data 1 mirror 1 pot 0 control 42
+E5: data 1 mirror 1 pot 0 control 40
+E6: data 1 mirror 1 pot 0 control 80
+E7: data 1 mirror 1 pot 0 control 04
+F0: data 0 mirror 0 pot 0 control 44
+F1: data 1 mirror 1 pot 0 control 44
+F2: data 1 mirror 1 pot 0 control 44
+F3: data 1 mirror 1 pot 0 control 80
+F4: data 1 mirror 1 pot 0 control 04
+F5: data 1 mirror 1 pot 0 control 04
+F6: data 0 mirror 0 pot 0 control 00
+F7: data 1 mirror 1 pot 0 control 44
+G0: data 1 mirror 1 pot 0 control 80
+G1: data 1 mirror 1 pot 0 control 44
+G2: data 1 mirror 1 pot 0 control 80
+G3: data 0 mirror 0 pot 0 control 00
+G4: data 0 mirror 0 pot 0 control 00
+G5: data 0 mirror 0 pot 0 control 00
+G6: data 1 mirror 1 pot 0 control 44
+G7: data 0 mirror 0 pot 0 control 00
+H0: data 1 mirror 1 pot 0 control 80
+H1: data 1 mirror 1 pot 0 control 80
+H2: data 0 mirror 0 pot 0 control 44
+H3: data 0 mirror 0 pot 0 control 44
+H4: data 1 mirror 1 pot 0 control 80
+H5: data 1 mirror 1 pot 0 control 44
+H6: data 1 mirror 1 pot 0 control 80
+H7: data 1 mirror 1 pot 0 control 44
+I0: data 0 mirror 0 pot 0 control 00
+I1: data 0 mirror 0 pot 0 control 00
+I2: data 0 mirror 0 pot 0 control 40
+I3: data 0 mirror 0 pot 0 control 80
+I4: data 0 mirror 0 pot 0 control 00
+I5: data 0 mirror 0 pot 0 control 80
+I6: data 1 mirror 1 pot 0 control 80
+I7: data 0 mirror 0 pot 0 control 00
+J0: data 1 mirror 1 pot 0 control 44
+J1: data 1 mirror 1 pot 0 control 40
+J2: data 1 mirror 1 pot 0 control 80
+J3: data 0 mirror 0 pot 0 control 80
+J4: data 1 mirror 1 pot 0 control 40
+J5: data 0 mirror 0 pot 0 control 40
+J6: data 0 mirror 0 pot 0 control 44
+J7: data 1 mirror 1 pot 0 control 84
+M0: data 1 mirror 1 control 06
+M1: data 1 mirror 1 control 06
+M2: data 1 mirror 1 control 06
+M3: data 1 mirror 1 control 06
+M4: data 0 mirror 0 control 06
+M5: data 1 mirror 1 control 00
+M6: data 1 mirror 1 control 86
+M7: data 0 mirror 0 control 00
diff --git a/models/gaze16-3060/edk2.config b/models/gaze16-3060/edk2.config
new file mode 100644
index 0000000..eb4f1b9
--- /dev/null
+++ b/models/gaze16-3060/edk2.config
@@ -0,0 +1,2 @@
+PCIE_BASE=0xC0000000
+#SYSTEM76_EC_LOGGING=TRUE
diff --git a/models/gaze16-3060/fd.rom b/models/gaze16-3060/fd.rom
new file mode 100644
index 0000000..dab2b36
--- /dev/null
+++ b/models/gaze16-3060/fd.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1b7513b54decff272c8f6be203386ea354623f55e9bbb59b5565be7e53260f1b
+size 4096
diff --git a/models/gaze16-3060/gpio.h b/models/gaze16-3060/gpio.h
new file mode 100644
index 0000000..ab1cc6c
--- /dev/null
+++ b/models/gaze16-3060/gpio.h
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include
+#include
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+ PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPD7, NONE, PWROK),
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+ PAD_CFG_GPO(GPD9, 0, PWROK),
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+ PAD_CFG_GPI(GPD11, NONE, PWROK),
+ _PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
+ _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
+ PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
+ PAD_CFG_GPI(GPP_A14, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
+ PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+ PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+ PAD_CFG_GPO(GPP_B15, 1, DEEP),
+ PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+ PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+ PAD_CFG_GPO(GPP_C22, 1, DEEP),
+ PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+ PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+ PAD_CFG_GPO(GPP_D23, 1, DEEP),
+ PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F2, 1, PLTRST),
+ PAD_CFG_GPO(GPP_F3, 1, DEEP),
+ PAD_CFG_GPO(GPP_F4, 1, DEEP),
+ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F8, 1, DEEP),
+ PAD_CFG_GPO(GPP_F9, 1, DEEP),
+ PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ PAD_NC(GPP_F22, NONE),
+ PAD_CFG_GPO(GPP_F23, 1, DEEP),
+ PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+ PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G11, NONE, DEEP),
+ PAD_NC(GPP_G12, NATIVE),
+ PAD_NC(GPP_G13, NATIVE),
+ PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
+ PAD_CFG_GPI(GPP_G15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H0, NONE, DEEP),
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+ PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+ PAD_CFG_GPI(GPP_H21, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+ PAD_CFG_GPO(GPP_H23, 1, DEEP),
+ PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
+ _PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
+ _PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
+ PAD_CFG_GPI(GPP_I3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I4, NONE, DEEP),
+ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_I8, NONE, DEEP),
+ PAD_CFG_GPO(GPP_I9, 1, DEEP),
+ PAD_CFG_TERM_GPO(GPP_I10, 0, DN_20K, DEEP),
+ PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2),
+ PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2),
+ PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
+ PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
+ PAD_CFG_GPI(GPP_J9, NONE, DEEP),
+ PAD_CFG_GPO(GPP_K0, 0, DEEP),
+ PAD_CFG_GPI(GPP_K1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+ PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_K11, NONE, PLTRST),
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
+ PAD_CFG_GPI(GPP_R6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R7, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R8, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R10, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R11, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
+ PAD_CFG_GPI(GPP_R13, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R14, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R15, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R16, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R18, NONE, DEEP),
+ PAD_CFG_GPI(GPP_R19, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S0, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S1, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S2, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S3, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S4, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S5, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S6, NONE, DEEP),
+ PAD_CFG_GPI(GPP_S7, NONE, DEEP),
+};
+
+#endif
+
+#endif
diff --git a/models/gaze16-3060/hda_verb.c b/models/gaze16-3060/hda_verb.c
new file mode 100644
index 0000000..9d4552e
--- /dev/null
+++ b/models/gaze16-3060/hda_verb.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC256 */
+ 0x10ec0256, /* Vendor ID */
+ 0x155850e2, /* Subsystem ID */
+ 11, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x155850e2),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+ /* Intel, TigerlakeHDMI */
+ 0x80862812, /* Vendor ID */
+ 0x80860101, /* Subsystem ID */
+ 10, /* Number of entries */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+ /* Nvidia, GPU9fHDMI/DP */
+ 0x10de009f, /* Vendor ID */
+ 0x10de0000, /* Subsystem ID */
+ 3, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x10de0000),
+ AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+ AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/models/gaze16-3060/me.rom b/models/gaze16-3060/me.rom
new file mode 100644
index 0000000..57d8737
--- /dev/null
+++ b/models/gaze16-3060/me.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:038396bfe7dcb0dadd1a68121042667dfa4e1d3af7e248c424787c4098792075
+size 5238784
diff --git a/models/gaze16-3060/microcode.rom b/models/gaze16-3060/microcode.rom
new file mode 100644
index 0000000..46c7b75
--- /dev/null
+++ b/models/gaze16-3060/microcode.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:e2b82f224a767a8a9a0336dac3539808b1d03a2d388a858d8ce4beb94e81a1f3
+size 100352
diff --git a/models/gaze16-3060/vbt.rom b/models/gaze16-3060/vbt.rom
new file mode 100644
index 0000000..baf95b4
--- /dev/null
+++ b/models/gaze16-3060/vbt.rom
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ffdae6b3d3b64d94aed487f8205ddbf0e9ffdc04245370cd4475608ace5fe2e7
+size 8704
diff --git a/tools/coreboot-collector b/tools/coreboot-collector
index 328924c..669cadf 160000
--- a/tools/coreboot-collector
+++ b/tools/coreboot-collector
@@ -1 +1 @@
-Subproject commit 328924cfc0b2b71959472b2b3cca4b1c1fe0c986
+Subproject commit 669cadfeee655b774d4a9845219835e0f16aab6c