From fdf724c6a226f777146db43bd4971185123bc386 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 3 Dec 2020 08:46:38 -0700 Subject: [PATCH] Update coreboot and configs --- coreboot | 2 +- models/galp5/coreboot.config | 2 +- models/lemp10/coreboot.config | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/coreboot b/coreboot index d95db48..869eebb 160000 --- a/coreboot +++ b/coreboot @@ -1 +1 @@ -Subproject commit d95db48cd718b080485b3f70183f58a5dd6a375e +Subproject commit 869eebbbb5e22accd5021e1496ab289f9263b56a diff --git a/models/galp5/coreboot.config b/models/galp5/coreboot.config index 87a119f..4372722 100644 --- a/models/galp5/coreboot.config +++ b/models/galp5/coreboot.config @@ -175,6 +175,7 @@ CONFIG_BOARD_SYSTEM76_GALP5=y CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include" CONFIG_FSP_FD_PATH="3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE=0x1c +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -248,7 +249,6 @@ CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 CONFIG_UART_PCI_ADDR=0x0 CONFIG_SOC_INTEL_TIGERLAKE=y -CONFIG_VBT_DATA_SIZE_KB=9 CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT=0 # CONFIG_EARLY_TCSS_DISPLAY is not set CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y diff --git a/models/lemp10/coreboot.config b/models/lemp10/coreboot.config index 753a098..e28d9db 100644 --- a/models/lemp10/coreboot.config +++ b/models/lemp10/coreboot.config @@ -175,6 +175,7 @@ CONFIG_BOARD_SYSTEM76_LEMP10=y CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include" CONFIG_FSP_FD_PATH="3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE=0x01 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -248,7 +249,6 @@ CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 CONFIG_UART_PCI_ADDR=0x0 CONFIG_SOC_INTEL_TIGERLAKE=y -CONFIG_VBT_DATA_SIZE_KB=9 CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT=0 # CONFIG_EARLY_TCSS_DISPLAY is not set CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y