Update kudu6 chip

Add PSPTool
Update EC
2022-07-09 19:51:55 -06:00 · 2022-07-09 19:51:55 -06:00 · 2022-07-09 19:51:55 -06:00 · 2022-07-09 19:51:55 -06:00 · 2022-07-09 19:51:55 -06:00 · 2022-07-09 19:42:09 -06:00
362 changed files with 154505 additions and 60309 deletions
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,30 @@
 ---
 name: Bug report
 about: Report a problem
 title: ''
 labels: []
 assignees: []
 ---
 - Model: <!-- `cat /sys/class/dmi/id/product_version` (e.g.: gaze16-3050) -->
 - BIOS version: <!-- `cat /sys/class/dmi/id/bios_version` (e.g.: 2021-09-30_14b8a6e)-->
 - EC version: <!-- This will match the BIOS version unless you flashed it separately. -->
 - OS: <!-- e.g.: Pop!_OS 21.10, Fedora 35, Windows 11 -->
 <!-- Briefly describe the problem. -->
 ### Steps to reproduce
 <!-- Provide a list of steps to reproduce the issue. -->
 ### Expected behavior
 <!-- Describe what you think should happen. -->
 ### Actual behavior
 <!-- Describe what actually happens. -->
 ### Additional info
 <!-- Any extra info you think may be relevant. -->
--- a/.github/ISSUE_TEMPLATE/config.yml
+++ b/.github/ISSUE_TEMPLATE/config.yml
@@ -0,0 +1,8 @@
 blank_issues_enabled: true
 contact_links:
  - name: Open a Support Ticket
    url: https://system76.com/my-account/support-tickets/new
    about: Get support for your System76 hardware
  - name: Pop!_OS chat
    url: https://chat.pop-os.org/
    about: Pop!_OS Mattermost
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,14 +10,6 @@
 	path = edk2-platforms
 	url = https://github.com/system76/edk2-platforms.git
 	branch = system76
 [submodule "tools/unME12"]
 	path = tools/unME12
 	url = https://github.com/ptresearch/unME12.git
 	branch = master
 [submodule "tools/unME11"]
 	path = tools/unME11
 	url = https://github.com/ptresearch/unME11.git
 	branch = master
 [submodule "tools/UEFITool"]
 	path = tools/UEFITool
 	url = https://github.com/LongSoft/UEFITool.git
@@ -30,14 +22,6 @@
 	path = libs/uefi
 	url = https://gitlab.redox-os.org/redox-os/uefi.git
 	branch = master
 [submodule "libs/uefi_alloc"]
 	path = libs/uefi_alloc
 	url = https://gitlab.redox-os.org/redox-os/uefi_alloc.git
 	branch = master
 [submodule "libs/uefi_std"]
 	path = libs/uefi_std
 	url = https://gitlab.redox-os.org/redox-os/uefi_std.git
 	branch = master
 [submodule "libs/coreboot-table"]
 	path = libs/coreboot-table
 	url = https://gitlab.redox-os.org/redox-os/coreboot-table.git
@@ -46,10 +30,6 @@
 	path = libs/intel-spi
 	url = https://github.com/system76/intel-spi.git
 	branch = master
 [submodule "libs/ecflash"]
 	path = libs/ecflash
 	url = https://github.com/system76/ecflash.git
 	branch = master
 [submodule "tools/coreboot-collector"]
 	path = tools/coreboot-collector
 	url = https://github.com/system76/coreboot-collector.git
@@ -82,10 +62,6 @@
 	path = FSP
 	url = https://github.com/IntelFsp/FSP.git
 	branch = master
 [submodule "libs/smmstore"]
 	path = libs/smmstore
 	url = https://github.com/system76/smmstore.git
 	branch = master
 [submodule "apps/firmware-smmstore"]
 	path = apps/firmware-smmstore
 	url = https://github.com/system76/firmware-smmstore.git
@@ -102,3 +78,7 @@
 	path = tools/apobtool
 	url = https://github.com/system76/apobtool.git
 	branch = master
 [submodule "tools/PSPTool"]
 	path = tools/PSPTool
 	url = https://github.com/PSPReverse/PSPTool.git
 	branch = master
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,12 +4,46 @@ Changes are identified by the date of the released firmware including them. If
 you are running System76 Open Firmware, opening the boot menu will show this
 date followed by an underscore and a short git revision.
 ## 2022-07-05
 - lemp11: Fix power off under load while on battery power
 ## 2022-06-29
 - lemp11: Release of open firmare with System76 EC
 ## 2022-06-23
 - darp8: Release of open firmware with System76 EC
 ## 2022-06-07
 - Fixed building for QEMU
 - Updated coreboot to upstream commit 670572ff6a
 - Improved NVIDIA Optimus support
 - gaze17-3060-b: Release of open firmware with System76 EC
 ## 2022-02-15
 - Update ME for all supported systems
 - Ensure that system powers off S5 plane if it fails to reach S0
 ## 2022-01-06
 - Added support to enable/disable Intel ME via the CMOS option `me_state`
 - Enabled coreboot measured boot
 - Updated Rust toolchain to nightly-2021-06-15
 - Updated coreboot to 4.15
 - Updated EDK2 to edk2-stabke202108
 - Updated TGL-U microcode blobs to revision 0x9a
 - Updated TGL-H microcode blobs to revision 0x3c
 - Updated all other boards to use microcode blobs from Intel's public repo
 - Updated TGL FSP to A.0.51.31 from Intel's public repo
 - Removed behavior of erasing NVRAM on CMOS reset
 ## 2021-09-30
 - gaze16: Do not require unplugging the AC adapter after flashing
 ## 2021-09-29
 - gaze16: Fix using USB 2.0 devices in Type-C port
 ## 2021-09-23
--- a/LICENSE.md
+++ b/LICENSE.md
@@ -0,0 +1,43 @@
 # License
 System76 Open Firmware consists of multiple projects under different licenses.
 The source components are made available under the following licenses:
 | Component       | License             |
 | ---------       | -------             |
 | coreboot        | GPL-2.0-only        |
 | edk2            | BSD-2-Clause-Patent |
 | firmware-setup  | GPL-3.0-only        |
 | ec              | GPL-3.0-only        |
 | Intel CSME      | Proprietary         |
 | Intel FSP       | Proprietary         |
 | Intel microcode | Proprietary         |
 ## Binaries
 ### `ec.rom`
 The license for the embedded controller firmware depends on the binary used.
 - System76 EC firmware: GPL-3.0-only
 - ODM-provided firmware: Proprietary
 ### `firmware.rom`
 `firmware.rom` contains multiple projects under different licenses.
 - coreboot: GPL-2.0-only
 - edk2-based payload: GPL-3.0-only
 - Intel binaries: Proprietary
 #### Intel binaries
 Intel provides biniaries under a redistributable license, which may be
 different per binary.
 - `me.rom`: Intel CSME
 - `Fsp.fd`: [Intel FSP](https://github.com/intel/fsp)
  - [`FSP_License.pdf`](https://github.com/intel/FSP/blob/master/FSP_License.pdf)
 - `microcode.rom`: [Intel microcode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files)
  - [`license`](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license)
--- a/LICENSES/BSD-2-Clause-Patent.txt
+++ b/LICENSES/BSD-2-Clause-Patent.txt
@@ -0,0 +1,49 @@
 Copyright (c) <YEAR>, <COPYRIGHT HOLDERS>
 Redistribution and use in source and binary forms, with or without
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--- a/LICENSES/GPL-2.0-only.txt
+++ b/LICENSES/GPL-2.0-only.txt
@@ -0,0 +1,339 @@
                    GNU GENERAL PUBLIC LICENSE
                       Version 2, June 1991
 Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 Everyone is permitted to copy and distribute verbatim copies
 of this license document, but changing it is not allowed.
                            Preamble
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 License is intended to guarantee your freedom to share and change free
 software--to make sure the software is free for all its users.  This
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--- a/LICENSES/GPL-3.0-only.txt
+++ b/LICENSES/GPL-3.0-only.txt
@@ -0,0 +1,674 @@
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                     END OF TERMS AND CONDITIONS
            How to Apply These Terms to Your New Programs
  If you develop a new program, and you want it to be of the greatest
 possible use to the public, the best way to achieve this is to make it
 free software which everyone can redistribute and change under these terms.
  To do so, attach the following notices to the program.  It is safest
 to attach them to the start of each source file to most effectively
 state the exclusion of warranty; and each file should have at least
 the "copyright" line and a pointer to where the full notice is found.
    <one line to give the program's name and a brief idea of what it does.>
    Copyright (C) <year>  <name of author>
    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    GNU General Public License for more details.
    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <https://www.gnu.org/licenses/>.
 Also add information on how to contact you by electronic and paper mail.
  If the program does terminal interaction, make it output a short
 notice like this when it starts in an interactive mode:
    <program>  Copyright (C) <year>  <name of author>
    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
    This is free software, and you are welcome to redistribute it
    under certain conditions; type `show c' for details.
 The hypothetical commands `show w' and `show c' should show the appropriate
 parts of the General Public License.  Of course, your program's commands
 might be different; for a GUI interface, you would use an "about box".
  You should also get your employer (if you work as a programmer) or school,
 if any, to sign a "copyright disclaimer" for the program, if necessary.
 For more information on this, and how to apply and follow the GNU GPL, see
 <https://www.gnu.org/licenses/>.
  The GNU General Public License does not permit incorporating your program
 into proprietary programs.  If your program is a subroutine library, you
 may consider it more useful to permit linking proprietary applications with
 the library.  If this is what you want to do, use the GNU Lesser General
 Public License instead of this License.  But first, please read
 <https://www.gnu.org/licenses/why-not-lgpl.html>.
--- a/LICENSES/Intel-redist.txt
+++ b/LICENSES/Intel-redist.txt
@@ -0,0 +1,37 @@
 Copyright (c) <YEAR> Intel Corporation.
 All rights reserved.
 Redistribution.
 Redistribution and use in binary form, without modification, are permitted,
 provided that the following conditions are met:
 1.  Redistributions must reproduce the above copyright notice and the
    following disclaimer in the documentation and/or other materials provided
    with the distribution.
 2.  Neither the name of Intel Corporation nor the names of its suppliers may
    be used to endorse or promote products derived from this software without
    specific prior written permission.
 3.  No reverse engineering, decompilation, or disassembly of this software
    is permitted.
 "Binary form" includes any format that is commonly used for electronic
 conveyance that is a reversible, bit-exact translation of binary
 representation to ASCII or ISO text, for example "uuencode".
 DISCLAIMER.
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 POSSIBILITY OF SUCH DAMAGE.
--- a/README.md
+++ b/README.md
@@ -10,15 +10,14 @@ manager:
 - addw2
 - bonw14
 - darp5
 - darp6
 - darp7
 - galp3-c
 - galp4
 - galp5
 - gaze15
 - gaze16-3050
 - gaze16-3060
 - gaze16-3060-b
 - lemp9
 - lemp10
 - oryp6
@@ -31,52 +30,47 @@ seen in the `models/` directory.
 If the device becomes bricked it will require restoring the current firmware
 using an external programmer. See [flashing](./docs/flashing.md) for details.
 ### Schematics
 System76 customers may request board schematics for their system by sending an
 email to firmware@system76.com with the subject line  "Schematics for _model_",
 where _model_ is one of the supported models listed above. Please include the
 serial number of your system for verification.
 You may not share these without explicit permission from System76.
 ## Changelog
 For a list of important changes please see the [changelog](./CHANGELOG.md).
-## Schematics
+## Building
-System76 customers may request board schematics by sending an email to
+Dependencies can be installed with the provided script.
 firmware@system76.com with the subject line  "Schematics for _model_", where
 _model_ is the name of a directory in the `models/` directory, such as darp6.
 Please include the serial number of your system for verification.
 You may not share these without explicit permission from System76.
 ## Dependencies
 ### Install toolchain
 ```
 ./scripts/deps.sh
 ```
-### Load Rust environment (or optionally reboot)
+If rustup was installed for the first time, it will be required to source the
 environment file it installed to use the correct Rust toolchain.
 ```
 source ~/.cargo/env
 ```
-### Build firmware, replace qemu with your model (look in the models directory for examples)
+A script is provided to build the firmware. The available targets for building
 are the model folders in `models/`. For example, to build for QEMU:
 ```
 ./scripts/build.sh qemu
 ```
-### Emulate firmware, only available after building the qemu model
+Once built, the firmware must be flashed to use. Several scripts are available
-```
+to flash the new firmware, depending on how it is going to be written.
 ./scripts/qemu.sh
 ```
-## Contents
+- `scripts/qemu.sh`: [Run the firmware in QEMU](./docs/debugging.md#using-qemu) (specific to the QEMU model)
 - `scripts/flash.sh`: Flash using the internal flasher
 - `scripts/ch341a-flash.sh`: Flash using a CH341A programmer
 - `scripts/spipi-flash.sh`: Flash using a Raspberry Pi
- [apps](./apps) - Applications
+See [Flashing firmware](./docs/flashing.md) for more details.
 - [coreboot](https://github.com/system76/coreboot.git) - coreboot README
 - [docs](./docs) - System76 Open Firmware Documentation
 - [ec](https://github.com/system76/ec.git) - System76 EC
 - [edk2](https://github.com/system76/edk2.git) - EDK II Project
 - [edk2-non-osi](https://github.com/tianocore/edk2-non-osi.git)
 - [edk2-platforms](https://github.com/system76/edk2-platforms.git) - This branch holds all platforms actively maintained against the
 - [FSP](https://github.com/IntelFsp/FSP.git) - Intel® Firmware Support Package (Intel® FSP) Binaries
 - [libs](./libs) - Libraries
 - [models](./models) - Models
 - [scripts](./scripts)
 - [tools](./tools) - Tools
--- a/README.md.in
+++ b/README.md.in
@@ -1,64 +0,0 @@
 # System76 Open Firmware
 An open source distribution of firmware utilizing coreboot, EDK2, and System76
 firmware applications.
 ## Supported models
 These models are supported and will receive updates through the firmware
 manager:
 - addw2
 - bonw14
 - darp5
 - darp6
 - darp7
 - galp3-c
 - galp4
 - galp5
 - gaze15
 - lemp9
 - lemp10
 - oryp6
 - oryp7
 Other models may be in development or available without support, and can be
 seen in the `models/` directory.
 If the device becomes bricked it will require restoring the current firmware
 using an external programmer. See [flashing](./docs/flashing.md) for details.
 ## Changelog
 For a list of important changes please see the [changelog](./CHANGELOG.md).
 ## Schematics
 System76 customers may request board schematics by sending an email to
 firmware@system76.com with the subject line  "Schematics for _model_", where
 _model_ is the name of a directory in the `models/` directory, such as darp6.
 Please include the serial number of your system for verification.
 You may not share these without explicit permission from System76.
 ## Dependencies
 ### Install toolchain
 ```
 ./scripts/deps.sh
 ```
 ### Load Rust environment (or optionally reboot)
 ```
 source ~/.cargo/env
 ```
 ### Build firmware, replace qemu with your model (look in the models directory for examples)
 ```
 ./scripts/build.sh qemu
 ```
 ### Emulate firmware, only available after building the qemu model
 ```
 ./scripts/qemu.sh
 ```
--- a/apps/firmware-setup
+++ b/apps/firmware-setup
--- a/apps/firmware-smmstore
+++ b/apps/firmware-smmstore
--- a/apps/firmware-update
+++ b/apps/firmware-update
--- a/apps/gop-policy
+++ b/apps/gop-policy
--- a/2
+++ b/2
--- a/docs/adding-a-new-board.md
+++ b/docs/adding-a-new-board.md
@@ -78,6 +78,12 @@ cp coreboot/.config models/<model>/coreboot.config
 `generate.sh` does not create `devicetree.cb`. Some values for this file can be
 produced using the `devicetree.py` script.
 ## Configuring Intel CSME
 The CSME image may need to be regenerated. Common changes that may be required
 are disabling Platform Trust Technology (PTT) so the discrete TPM device will
 work, and changing the Boot Guard profile to disable verified boot.
 ## Porting System76 EC
 To port System76 EC firmware to a new board, see the EC documentation.
--- a/docs/debugging.md
+++ b/docs/debugging.md
@@ -0,0 +1,97 @@
 # Debugging
 ## Component
 ### coreboot
 coreboot debug logging is enabled by default at the level of `Debug`. This can
 be changed using `nvramtool` to set the CMOS option `debug_level`.
 ```
 sudo nvramtool -w debug_level=<level>
 ```
 Available log levels are:
 - Emergency
 - Alert
 - Critical
 - Error
 - Warning
 - Notice
 - Info
 - Debug
 - Spew
 ### edk2
 Modify `./scripts/_build/edk2.sh` so `BUILD_TYPE` is set to `DEBUG` instead of
 `RELEASE`.
 ```sh
 #BUILD_TYPE=RELEASE
 BUILD_TYPE=DEBUG
 ```
 The default PCD values are used, so a lot of ouput will be generated. This can
 have a significant impact on the boot time.
 This also unconditionally enables asserts, so any failures will result in edk2
 hanging and require a reflash to fix.
 ### Rust UEFI apps
 Debug logging can be enabled in the Rust UEFI apps (e.g., `firmware-setup`) by
 selecting the `debug` feature in `Cargo.toml`.
 ## Method
 A couple of methods can be used to get debug logging.
 ### Parallel port
 This method requires no soldering of board components.
 See [Debugging the EC firmware](./ec/doc/debugging.md) for details on setting
 up EC debugging over the parallel port.
 cbmem output can be passed through the EC by enabling the driver in coreboot.
 Uncomment the config in `models/<model>/coreboot.config` to enable logging the
 cbmem console through the EC.
 ```
 CONFIG_CONSOLE_SYSTEM76_EC=y
 ```
 edk2 output can be passed through as well by enabling the driver in edk2.
 This causes boot to be *very* slow, as edk2 generates a lot of output.
 Uncomment the config in `models/<model>/edk2.config` to enable the driver.
 ```
 SYSTEM76_EC_LOGGING=TRUE
 ```
 ### Using QEMU
 A `qemu` target is provided to allow development and debugging in a VM.
 ```
 ./scripts/build.sh qemu
 ```
 Install QEMU:
 ```sh
 # Arch
 sudo pacman -S qemu
 # Fedora
 sudo dnf install qemu-system-x86
 # Ubuntu
 sudo apt install qemu-system-x86
 ```
 And run the image in a VM:
 ```
 ./scripts/qemu.sh
 ```
--- a/docs/intel-me.md
+++ b/docs/intel-me.md
@@ -1,19 +1,35 @@
 # Intel Management Engine
-Intel-based machines by System76 come with the [Intel Management Engine][wiki]
+[Intel Management Engine][wiki] is a proprietary, mostly undocumented, firmware
-disabled. It is a proprietary, mostly undocumented, system that provides many
+system that provides many extraneous features that are generally not usable or
-extraneous features that are generally not usable or useful to our users, with
+useful to our users, with multiple known vulnerabilities that compromise the
-multiple known vulnerabilities that compromise the entire system.
+entire system.
 The Intel ME is _required_ (since Nehalem, 2008), so cannot be removed. The
-[me\_cleaner] project is able to remove non-essential components, but currently
+[me\_cleaner] project is able to remove non-essential components, but does not
-does not support the ME version used on many of our systems. Instead, we [send
+support the ME version used on many of our systems. Instead, we [send a HECI
-a HECI command][heci_disable] to tell the Intel ME to disable runtime
+command][CB52800] to tell the Intel ME to disable runtime components during
-components during early boot.
+early boot.
 Most Intel-based machines from System76 come with the IME disabled.
 ## Configuring
 The IME can be enabled or disabled via the coreboot CMOS option `me_state`.
 The value can be set using coreboot's nvramtool.
 ```
 make -C coreboot/util/nvramtool
 sudo ./coreboot/util/nvramtool/nvramtool -w me_state={Enable,Disable}
 ```
 A restart is required for the change to take effect. On the boot after changing
 the value, the system will perform a global reset (power off again) to complete
 the change and ensure the IME is operating in a valid state.
 ## Tiger Lake-U
-Models using TGL-U processors currently leave the IME enabled. TGL-U removes
+Models using TGL-U processors default to having the IME enabled. TGL-U removes
 support for S3 and requires S0ix. This requires all CPU, PCH, and PCIe devices
 to have ACPI defined low power states. With S0ix, the CPU has numerous states
 for low power, with the lowest being C10. In order to reach this C10 state, the
@@ -21,6 +37,7 @@ IME must report that it is in a low power state. Disabling the ME with the HAP
 bit keeps the CPU in the C8 state. This nearly triples the power usage in S0ix
 suspend, from around 1 watt to around 3 watts.
 [wiki]: https://en.wikipedia.org/wiki/Intel_Management_Engine
 [me\_cleaner]: https://github.com/corna/me_cleaner
-[heci_disable]: https://github.com/system76/coreboot/blob/011439cb9196d6a71d394ead8c98dfd8ead325d4/src/soc/intel/cannonlake/me.c#L186
+[CB52800]: https://review.coreboot.org/c/coreboot/+/52800
--- a/docs/uefi.md
+++ b/docs/uefi.md
@@ -0,0 +1,27 @@
 # UEFI
 System76 uses [EDK2](https://github.com/tianocore/edk2) to implement UEFI.
 [coreboot](https://coreboot.org/) is used for Platform Initialization (PI).
 ## Booting
 System76 Open Firmware only supports UEFI booting. Legacy BIOS-MBR booting is
 not supported. `\EFI\BOOT\BOOTX64.EFI` must exist on the EFI System Partition
 to be considered valid.
 Network functionality is disabled. Native PXE booting is not supported.
 ### Secure Boot
 Secure Boot support is currently disabled.
 The implementation from 9elements is in development. If building a custom
 image, the edk2 config `SECURE_BOOT_ENABLE` can be set to enable support.
 There is currently no firmware UI to view or configure Secure Boot.
 ## Shell
 The internal UEFI shell is disabled. A separate binary on a bootable drive
 must be used to access the shell environment.
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/libs/README.md
+++ b/libs/README.md
@@ -4,10 +4,6 @@
 - [coreboot-fs](https://gitlab.redox-os.org/redox-os/coreboot-fs.git) - coreboot-fs
 - [coreboot-table](https://gitlab.redox-os.org/redox-os/coreboot-table.git) - coreboot-table
 - [ecflash](https://github.com/system76/ecflash.git) - ecflash
 - [intelflash](https://gitlab.redox-os.org/redox-os/intelflash.git) - intelflash
 - [intel-spi](https://github.com/system76/intel-spi.git) - intel-spi
- [smmstore](https://github.com/system76/smmstore.git) - smmstore
+- [uefi](https://gitlab.redox-os.org/redox-os/uefi.git) - Redox UEFI
 - [uefi](https://gitlab.redox-os.org/redox-os/uefi.git)
 - [uefi_alloc](https://gitlab.redox-os.org/redox-os/uefi_alloc.git)
 - [uefi_std](https://gitlab.redox-os.org/redox-os/uefi_std.git) - uefi_std
--- a/libs/coreboot-table
+++ b/libs/coreboot-table
--- a/libs/ecflash
+++ b/libs/ecflash
--- a/libs/intel-spi
+++ b/libs/intel-spi
--- a/libs/smmstore
+++ b/libs/smmstore
--- a/libs/uefi
+++ b/libs/uefi
--- a/libs/uefi_alloc
+++ b/libs/uefi_alloc
--- a/libs/uefi_std
+++ b/libs/uefi_std
--- a/models/README.md
+++ b/models/README.md
@@ -8,6 +8,7 @@
 - [darp5](./darp5) - System76 Darter Pro (darp5)
 - [darp6](./darp6) - System76 Darter Pro (darp6)
 - [darp7](./darp7) - System76 Darter Pro (darp7)
 - [darp8](./darp8) - System76 Darter Pro (darp8)
 - [galp2](./galp2) - System76 Galago Pro (galp2)
 - [galp3](./galp3) - System76 Galago Pro (galp3)
 - [galp3-b](./galp3-b) - System76 Galago Pro (galp3-b)
@@ -20,7 +21,11 @@
 - [gaze16-3050](./gaze16-3050) - System76 Gazelle (gaze16)
 - [gaze16-3060](./gaze16-3060) - System76 Gazelle (gaze16)
 - [gaze16-3060-b](./gaze16-3060-b) - System76 Gazelle (gaze16)
 - [gaze17-3050](./gaze17-3050) - System76 Gazelle (gaze17)
 - [gaze17-3060-b](./gaze17-3060-b) - System76 Gazelle (gaze17-3060-b)
 - [kudu6](./kudu6) - System76 Kudu (kudu6)
 - [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
 - [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
 - [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
 - [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
 - [oryp6](./oryp6) - System76 Oryx Pro (oryp6)
--- a/models/addw1/README.md
+++ b/models/addw1/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/addw1
  - HAP: false
 - [ME](./me.rom)
  - Size: 6140 KB
-  - Version: 12.0.49.1536
+  - Version: 12.0.85.1919
--- a/models/addw1/coreboot.config
+++ b/models/addw1/coreboot.config
@@ -14,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x65d1
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/addw1/edk2.config
+++ b/models/addw1/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw1/fd.rom
+++ b/models/addw1/fd.rom
--- a/models/addw1/me.rom
+++ b/models/addw1/me.rom
--- a/models/addw2/README.md
+++ b/models/addw2/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/addw2
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.30.1114
+  - Version: 14.0.60.1807
--- a/models/addw2/coreboot.config
+++ b/models/addw2/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_ADDW2=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
@@ -15,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x65e1
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/addw2/edk2.config
+++ b/models/addw2/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw2/fd.rom
+++ b/models/addw2/fd.rom
--- a/models/addw2/me.rom
+++ b/models/addw2/me.rom
--- a/models/addw2/microcode.rom
+++ b/models/addw2/microcode.rom
--- a/models/bonw14/README.md
+++ b/models/bonw14/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.30.1114
+  - Version: 14.0.60.1807
--- a/models/bonw14/coreboot.config
+++ b/models/bonw14/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_BONW14=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
@@ -15,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x7714
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/bonw14/edk2.config
+++ b/models/bonw14/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/bonw14/fd.rom
+++ b/models/bonw14/fd.rom
--- a/models/bonw14/me.rom
+++ b/models/bonw14/me.rom
--- a/models/bonw14/microcode.rom
+++ b/models/bonw14/microcode.rom
--- a/models/darp5/coreboot.config
+++ b/models/darp5/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP5=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
 CONFIG_MAINBOARD_VERSION="darp5"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1325
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp5/edk2.config
+++ b/models/darp5/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp6/FSP/Fsp_M.fd
+++ b/models/darp6/FSP/Fsp_M.fd
--- a/models/darp6/FSP/Fsp_S.fd
+++ b/models/darp6/FSP/Fsp_S.fd
--- a/models/darp6/FSP/Fsp_T.fd
+++ b/models/darp6/FSP/Fsp_T.fd
--- a/models/darp6/FSP/Include
+++ b/models/darp6/FSP/Include
@@ -1 +0,0 @@
 ../../../FSP/CometLakeFspBinPkg/CometLake1/Include
--- a/models/darp6/FSP/LICENSE
+++ b/models/darp6/FSP/LICENSE
@@ -1,46 +0,0 @@
 ************************************************************************
 **                                                                    **
 **                                                                    **
 **      IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING     **
 **                                                                    **
 **                     ANY PORTION OF THE SOFTWARE                    **
 **                                                                    **
 ************************************************************************
 Copyright (c) 2018 Intel Corporation.
 All rights reserved.
 Redistribution.
 Redistribution and use in binary form, without modification, are permitted
 provided that the following conditions are met:
 - Redistributions must reproduce the above copyright notice and the 
 following disclaimer in the documentation and/or other materials provided 
 with the distribution.
 - Neither the name of Intel Corporation nor the names of its suppliers 
 may be used to endorse or promote products derived from this software 
 without specific prior written permission.
 - No reverse engineering, decompilation, or disassembly of this software 
 is permitted.
 "Binary form" includes any format that is commonly used for electronic 
 conveyance that is a reversible, bit-exact translation of binary 
 representation to ASCII or ISO text, for example "uuencode".
 DISCLAIMER.
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
 THE POSSIBILITY OF SUCH DAMAGE.
--- a/models/darp6/README.md
+++ b/models/darp6/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/darp6
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.10.1204
+  - Version: 14.0.60.1807
--- a/models/darp6/coreboot.config
+++ b/models/darp6/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP6=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
 CONFIG_MAINBOARD_VERSION="darp6"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1404
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp6/edk2.config
+++ b/models/darp6/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp6/fd.rom
+++ b/models/darp6/fd.rom
--- a/models/darp6/me.rom
+++ b/models/darp6/me.rom
--- a/models/darp7/FSP/Fsp_M.fd
+++ b/models/darp7/FSP/Fsp_M.fd
--- a/models/darp7/FSP/Fsp_S.fd
+++ b/models/darp7/FSP/Fsp_S.fd
--- a/models/darp7/FSP/Fsp_T.fd
+++ b/models/darp7/FSP/Fsp_T.fd
--- a/models/darp7/FSP/Include/FirmwareVersionInfoHob.h
+++ b/models/darp7/FSP/Include/FirmwareVersionInfoHob.h
@@ -1,69 +0,0 @@
 /** @file
  Header file for Firmware Version Information
 @copyright
  INTEL CONFIDENTIAL
  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
  This program and the accompanying materials are licensed and made available under
  the terms and conditions of the BSD License which accompanies this distribution.
  The full text of the license may be found at
  http://opensource.org/licenses/bsd-license.php
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 #ifndef _FIRMWARE_VERSION_INFO_HOB_H_
 #define _FIRMWARE_VERSION_INFO_HOB_H_
 #include <Uefi/UefiMultiPhase.h>
 #include <Pi/PiBootMode.h>
 #include <Pi/PiHob.h>
 #pragma pack(1)
 ///
 /// Firmware Version Structure
 ///
 typedef struct {
  UINT8                          MajorVersion;
  UINT8                          MinorVersion;
  UINT8                          Revision;
  UINT16                         BuildNumber;
 } FIRMWARE_VERSION;
 ///
 /// Firmware Version Information Structure
 ///
 typedef struct {
  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
 } FIRMWARE_VERSION_INFO;
 #ifndef __SMBIOS_STANDARD_H__
 ///
 /// The Smbios structure header.
 ///
 typedef struct {
  UINT8                          Type;
  UINT8                          Length;
  UINT16                         Handle;
 } SMBIOS_STRUCTURE;
 #endif
 ///
 /// Firmware Version Information HOB Structure
 ///
 typedef struct {
  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
 ///
 /// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
 ///
 } FIRMWARE_VERSION_INFO_HOB;
 #pragma pack()
 #endif // _FIRMWARE_VERSION_INFO_HOB_H_
--- a/models/darp7/FSP/Include/FspUpd.h
+++ b/models/darp7/FSP/Include/FspUpd.h
@@ -1,48 +0,0 @@
 /** @file
 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
 * Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.
 * Redistributions in binary form must reproduce the above copyright notice, this
  list of conditions and the following disclaimer in the documentation and/or
  other materials provided with the distribution.
 * Neither the name of Intel Corporation nor the names of its contributors may
  be used to endorse or promote products derived from this software without
  specific prior written permission.
  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  THE POSSIBILITY OF SUCH DAMAGE.
  This file is automatically generated. Please do NOT modify !!!
 **/
 #ifndef __FSPUPD_H__
 #define __FSPUPD_H__
 #include <FspEas.h>
 #pragma pack(1)
 #define FSPT_UPD_SIGNATURE               0x545F4450554C4754        /* 'TGLUPD_T' */
 #define FSPM_UPD_SIGNATURE               0x4D5F4450554C4754        /* 'TGLUPD_M' */
 #define FSPS_UPD_SIGNATURE               0x535F4450554C4754        /* 'TGLUPD_S' */
 #pragma pack()
 #endif
--- a/models/darp7/FSP/Include/FspsUpd.h
+++ b/models/darp7/FSP/Include/FspsUpd.h
--- a/models/darp7/FSP/Include/FusaInfoHob.h
+++ b/models/darp7/FSP/Include/FusaInfoHob.h
@@ -1,161 +0,0 @@
 /** @file
  This file contains definitions required for creation of TGL
  end-to-end check-the-checker test result hob.
@copyright
  INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.
  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
  and licensors. The Material may contain trade secrets and proprietary and
  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.
  No license under any patent, copyright, trade secret or other intellectual
  property right is granted to or conferred upon you by disclosure or delivery
  of the Materials, either expressly, by implication, inducement, estoppel or
  otherwise. Any license under such intellectual property rights must be
  express and approved by Intel in writing.
  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.
  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
 **/
 #ifndef _FUSA_INFO_HOB_H_
 #define _FUSA_INFO_HOB_H_
 #pragma pack (push, 1)
 extern EFI_GUID gSiFusaInfoGuid;
 /**
  FuSa Info HOB version
  Use this to compare to the HOB retrieved from the FSP for the
  exact match
 **/
 #define FUSA_INFO_VERSION 0x00000100
 /** Constants used for FUSA_TEST_RESULT->CheckResults[] and
 *  FUSA_TEST_RESULT->TestResult */
 /**@defgroup ResultConstant Check Result Constants*/
 /**@{*/
 #define FUSA_TEST_DEVICE_NOTAVAILABLE  0xFF    /**<device is not available*/
 #define FUSA_TEST_NOTRUN               0x0U    /**<check is not run*/
 #define FUSA_TEST_FAIL                 0xD2U   /**<check fail*/
 #define FUSA_TEST_PASS                 0x2DU   /**<check pass*/
 /**@}*/
 /** Fusa test result structure
 **/
 typedef struct
 {
  UINT32 TestNumber;            /**< test number assigned to this test */
  UINT32 TotalChecks;           /**< total number of checks in this test */
  UINT8  TestResult;            /**< if all tests passed then this is FUSA_TEST_PASS.
                                  if at least one check fails, then this is TEST_FAIL
                                  if the device (eg. MC channel DIMM) is not available
                                  then this is FUSA_TEST_DEVICE_NOTAVAILABLE.
                                  if the test has not been run, then this is FUSA_TEST_NOTRUN*/
  UINT8  ReservedByte[3];       /**< reserved, as padding for 4 byte-alignment */
  UINT8  CheckResults[32];      /**< test result for each check.*/
  UINT32 Crc32;                 /**< crc32 of the structure */
 } FUSA_TEST_RESULT;
 /**
  Fusa Test Number assigned to each Fusa test.
  This will be used for the unique id for each test.
  FUSA_TEST_RESULT->TestNumber will have this value.
  @note While the core4-7 (cbo4-7) that are strictly related to
        the TGL-H are listed, there are not within the
        implementation scope and validation scope yet.
 **/
 typedef enum
 {
  FusaTestNumMc0Cmi = 0,          ///<Check MC0 CMI path, valid if there is DIMM using MC0
  FusaTestNumMc1Cmi,              ///<Check MC1 CMI path, valid if there is DIMM using MC1
  FusaTestNumMc0CmiCh0Data,       ///<Check MC0 CH0 CMI path, valid if there is DIMM using MC0 CH0
  FusaTestNumMc0CmiCh1Data,       ///<Check MC0 CH1 CMI path, valid if there is DIMM using MC0 CH1
  FusaTestNumMc0CmiCh2Data,       ///<Check MC0 CH2 CMI path, valid if there is DIMM using MC0 CH2
  FusaTestNumMc0CmiCh3Data,       ///<Check MC0 CH3 CMI path, valid if there is DIMM using MC0 CH3
  FusaTestNumMc1CmiCh0Data,       ///<Check MC1 CH0 CMI path, valid if there is DIMM using MC1 CH0
  FusaTestNumMc1CmiCh1Data,       ///<Check MC1 CH1 CMI path, valid if there is DIMM using MC1 CH1
  FusaTestNumMc1CmiCh2Data,       ///<Check MC1 CH2 CMI path, valid if there is DIMM using MC1 CH2
  FusaTestNumMc1CmiCh3Data,       ///<Check MC1 CH3 CMI path, valid if there is DIMM using MC1 CH3
  FusaTestNumIbecc0Cmi,           ///<Check Ibecc0 CMI path, valid if there is IBECC range covering MC0 DIMMs
  FusaTestNumIbecc1Cmi,           ///<Check Ibecc1 CMI path, valid if there is IBECC range covering MC1 DIMMs
  FusaTestNumIbecc0EccCorrError,  ///<Check Ibecc0 ECC correctable error, valid if there is IBECC range covering MC0 DIMMs
  FusaTestNumIbecc1EccCorrError,  ///<Check Ibecc1 ECC correctable error, valid if there is IBECC range covering MC1 DIMMs
  FusaTestNumIbecc0EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC0 DIMMs
  FusaTestNumIbecc1EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC1 DIMMs
  FusaTestNumMc0Mbist,            ///<Check MC0 MBIST
  FusaTestNumMc1Mbist,            ///<Check MC1 MBIST
  FusaTestNumMc0Ch0Mbist,         ///<Check MC0 CH0 MBIST
  FusaTestNumMc0Ch1Mbist,         ///<Check MC0 CH1 MBIST
  FusaTestNumMc0Ch2Mbist,         ///<Check MC0 CH2 MBIST
  FusaTestNumMc0Ch3Mbist,         ///<Check MC0 CH3 MBIST
  FusaTestNumMc1Ch0Mbist,         ///<Check MC1 CH0 MBIST
  FusaTestNumMc1Ch1Mbist,         ///<Check MC1 CH1 MBIST
  FusaTestNumMc1Ch2Mbist,         ///<Check MC1 CH2 MBIST
  FusaTestNumMc1Ch3Mbist,         ///<Check MC1 CH3 MBIST
  FusaTestNumIbecc0Mbist,         ///<Check Ibecc0 MBIST
  FusaTestNumIbecc1Mbist,         ///<Check Ibecc1 MBIST
  FusaTestNumCpu0Idi,             ///<Check core0 IDI path, valid if there is core0 in the SKU
  FusaTestNumCpu1Idi,             ///<Check core1 IDI path, valid if there is core1 in the SKU
  FusaTestNumCpu2Idi,             ///<Check core2 IDI path, valid if there is core2 in the SKU
  FusaTestNumCpu3Idi,             ///<Check core3 IDI path, valid if there is core3 in the SKU
  FusaTestNumCpu4Idi,             ///<Check core4 IDI path, valid if there is core4 in the SKU
  FusaTestNumCpu5Idi,             ///<Check core5 IDI path, valid if there is core5 in the SKU
  FusaTestNumCpu6Idi,             ///<Check core6 IDI path, valid if there is core6 in the SKU
  FusaTestNumCpu7Idi,             ///<Check core7 IDI path, valid if there is core7 in the SKU
  FusaTestNumCpu0Mbist,             ///<Check core0 Mbist, valid if there is core0 in the SKU
  FusaTestNumCpu1Mbist,             ///<Check core1 Mbist, valid if there is core1 in the SKU
  FusaTestNumCpu2Mbist,             ///<Check core2 Mbist, valid if there is core2 in the SKU
  FusaTestNumCpu3Mbist,             ///<Check core3 Mbist, valid if there is core3 in the SKU
  FusaTestNumCpu4Mbist,             ///<Check core4 Mbist, valid if there is core4 in the SKU
  FusaTestNumCpu5Mbist,             ///<Check core5 Mbist, valid if there is core5 in the SKU
  FusaTestNumCpu6Mbist,             ///<Check core6 Mbist, valid if there is core6 in the SKU
  FusaTestNumCpu7Mbist,             ///<Check core7 Mbist, valid if there is core7 in the SKU
  FusaTestNumCboSlice0Ingress,    ///<Check CBO0 ingress path, valid if there is core0 in the SKU
  FusaTestNumCboSlice1Ingress,    ///<Check CBO1 ingress path, valid if there is core1 in the SKU
  FusaTestNumCboSlice2Ingress,    ///<Check CBO2 ingress path, valid if there is core2 in the SKU
  FusaTestNumCboSlice3Ingress,    ///<Check CBO3 ingress path, valid if there is core3 in the SKU
  FusaTestNumCboSlice4Ingress,    ///<Check CBO4 ingress path, valid if there is core4 in the SKU
  FusaTestNumCboSlice5Ingress,    ///<Check CBO5 ingress path, valid if there is core5 in the SKU
  FusaTestNumCboSlice6Ingress,    ///<Check CBO6 ingress path, valid if there is core6 in the SKU
  FusaTestNumCboSlice7Ingress,    ///<Check CBO7 ingress path, valid if there is core7 in the SKU
  FusaTestNumOpiLinkIosfData,     ///<Check OPI Link path
  FusaTestNumDip,                 ///<Check DIP path
  FusaTestNumIop,                 ///<Check IOP path
  FusaTestNumTotal                ///<Totak CTC groups count
 } FUSA_TEST_NUMBER;
 /**
  Fusa test result HOB structure
 **/
 typedef struct {
  UINT32 Version;
  FUSA_TEST_RESULT FspDxCtcTestResult[FusaTestNumTotal];
 } FUSA_INFO_HOB;
 #pragma pack (pop)
 #endif // _FUSA_INFO_HOB_H_
--- a/models/darp7/FSP/Include/MemInfoHob.h
+++ b/models/darp7/FSP/Include/MemInfoHob.h
@@ -1,286 +0,0 @@
 /** @file
  This file contains definitions required for creation of
  Memory S3 Save data, Memory Info data and Memory Platform
  data hobs.
  @copyright
  Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
  This program and the accompanying materials are licensed and made available under
  the terms and conditions of the BSD License that accompanies this distribution.
  The full text of the license may be found at
  http://opensource.org/licenses/bsd-license.php.
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
 **/
 #ifndef _MEM_INFO_HOB_H_
 #define _MEM_INFO_HOB_H_
 #pragma pack (push, 1)
 extern EFI_GUID gSiMemoryS3DataGuid;
 extern EFI_GUID gSiMemoryInfoDataGuid;
 extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define MAX_TRACE_CACHE_TYPE  3
 #define MAX_NODE        2
 #define MAX_CH          4
 #define MAX_DIMM        2
 ///
 /// Host reset states from MRC.
 ///
 #define  WARM_BOOT        2
 #define R_MC_CHNL_RANK_PRESENT  0x7C
 #define   B_RANK0_PRS           BIT0
 #define   B_RANK1_PRS           BIT1
 #define   B_RANK2_PRS           BIT4
 #define   B_RANK3_PRS           BIT5
 // @todo remove and use the MdePkg\Include\Pi\PiHob.h
 #if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
 #ifndef __HOB__H__
 typedef struct _EFI_HOB_GENERIC_HEADER {
  UINT16  HobType;
  UINT16  HobLength;
  UINT32  Reserved;
 } EFI_HOB_GENERIC_HEADER;
 typedef struct _EFI_HOB_GUID_TYPE {
  EFI_HOB_GENERIC_HEADER  Header;
  EFI_GUID                Name;
  ///
  /// Guid specific data goes here
  ///
 } EFI_HOB_GUID_TYPE;
 #endif
 #endif
 ///
 /// Defines taken from MRC so avoid having to include MrcInterface.h
 ///
 //
 // Matches MAX_SPD_SAVE define in MRC
 //
 #ifndef MAX_SPD_SAVE
 #define MAX_SPD_SAVE 29
 #endif
 //
 // MRC version description.
 //
 typedef struct {
  UINT8  Major;     ///< Major version number
  UINT8  Minor;     ///< Minor version number
  UINT8  Rev;       ///< Revision number
  UINT8  Build;     ///< Build number
 } SiMrcVersion;
 //
 // Matches MrcChannelSts enum in MRC
 //
 #ifndef CHANNEL_NOT_PRESENT
 #define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
 #endif
 #ifndef CHANNEL_DISABLED
 #define CHANNEL_DISABLED     1  // There is a channel present but it is disabled.
 #endif
 #ifndef CHANNEL_PRESENT
 #define CHANNEL_PRESENT     2  // There is a channel present and it is enabled.
 #endif
 //
 // Matches MrcDimmSts enum in MRC
 //
 #ifndef DIMM_ENABLED
 #define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
 #endif
 #ifndef DIMM_DISABLED
 #define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
 #endif
 #ifndef DIMM_PRESENT
 #define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
 #endif
 #ifndef DIMM_NOT_PRESENT
 #define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
 #endif
 //
 // Matches MrcBootMode enum in MRC
 //
 #ifndef __MRC_BOOT_MODE__
 #define __MRC_BOOT_MODE__                 //The below values are originated from MrcCommonTypes.h
  #ifndef INT32_MAX
  #define INT32_MAX                       (0x7FFFFFFF)
  #endif  //INT32_MAX
 typedef enum {
  bmCold,                                 ///< Cold boot
  bmWarm,                                 ///< Warm boot
  bmS3,                                   ///< S3 resume
  bmFast,                                 ///< Fast boot
  MrcBootModeMax,                         ///< MRC_BOOT_MODE enumeration maximum value.
  MrcBootModeDelim = INT32_MAX            ///< This value ensures the enum size is consistent on both sides of the PPI.
 } MRC_BOOT_MODE;
 #endif  //__MRC_BOOT_MODE__
 //
 // Matches MrcDdrType enum in MRC
 //
 #ifndef MRC_DDR_TYPE_DDR4
 #define MRC_DDR_TYPE_DDR4     0
 #endif
 #ifndef MRC_DDR_TYPE_DDR3
 #define MRC_DDR_TYPE_DDR3     1
 #endif
 #ifndef MRC_DDR_TYPE_LPDDR3
 #define MRC_DDR_TYPE_LPDDR3   2
 #endif
 #ifndef MRC_DDR_TYPE_LPDDR4
 #define MRC_DDR_TYPE_LPDDR4   3
 #endif
 #ifndef MRC_DDR_TYPE_WIO2
 #define MRC_DDR_TYPE_WIO2     4
 #endif
 #ifndef MRC_DDR_TYPE_UNKNOWN
 #define MRC_DDR_TYPE_UNKNOWN  5
 #endif
 #define MAX_PROFILE_NUM     4 // number of memory profiles supported
 #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
 //
 // DIMM timings
 //
 typedef struct {
  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
 } MRC_CH_TIMING;
 ///
 /// Memory SMBIOS & OC Memory Data Hob
 ///
 typedef struct {
  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
  UINT8            DimmId;
  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
  UINT16           MfgId;
  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz
  UINT8            MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
 } DIMM_INFO;
 typedef struct {
  UINT8            Status;                  ///< Indicates whether this channel should be used.
  UINT8            ChannelId;
  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
 } CHANNEL_INFO;
 typedef struct {
  UINT8            Status;                  ///< Indicates whether this controller should be used.
  UINT16           DeviceId;                ///< The PCI device id of this memory controller.
  UINT8            RevisionId;              ///< The PCI revision id of this memory controller.
  UINT8            ChannelCount;            ///< Number of valid channels that exist on the controller.
  CHANNEL_INFO     ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
 } CONTROLLER_INFO;
 typedef struct {
  UINT64   BaseAddress;   ///< Trace Base Address
  UINT64   TotalSize;     ///< Total Trace Region of Same Cache type
  UINT8    CacheType;     ///< Trace Cache Type
  UINT8    ErrorCode;     ///< Trace Region Allocation Fail Error code
  UINT8    Rsvd[2];
 } PSMI_MEM_INFO;
 typedef struct {
  UINT8             Revision;
  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
  /** As defined in SMBIOS 3.0 spec
    Section 7.18.2 and Table 75
  **/
  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
  /** As defined in SMBIOS 3.0 spec
    Section 7.17.3 and Table 72
  **/
  UINT8             ErrorCorrectionType;
  SiMrcVersion      Version;
  BOOLEAN           EccSupport;
  UINT8             MemoryProfile;
  UINT32            TotalPhysicalMemorySize;
  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
  UINT8             XmpProfileEnable;                  ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
  UINT8             Ratio;
  UINT8             RefClk;
  UINT32            VddVoltage[MAX_PROFILE_NUM];
  CONTROLLER_INFO   Controller[MAX_NODE];
 } MEMORY_INFO_DATA_HOB;
 /**
  Memory Platform Data Hob
  <b>Revision 1:</b>
  - Initial version.
  <b>Revision 2:</b>
  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
 **/
 typedef struct {
  UINT8             Revision;
  UINT8             Reserved[3];
  UINT32            BootMode;
  UINT32            TsegSize;
  UINT32            TsegBase;
  UINT32            PrmrrSize;
  UINT64            PrmrrBase;
  UINT32            PramSize;
  UINT64            PramBase;
  UINT64            DismLimit;
  UINT64            DismBase;
  UINT32            GttBase;
  UINT32            MmioSize;
  UINT32            PciEBaseAddress;
  PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
 } MEMORY_PLATFORM_DATA;
 typedef struct {
  EFI_HOB_GUID_TYPE    EfiHobGuidType;
  MEMORY_PLATFORM_DATA Data;
  UINT8                *Buffer;
 } MEMORY_PLATFORM_DATA_HOB;
 #pragma pack (pop)
 #endif // _MEM_INFO_HOB_H_
--- a/models/darp7/FSP/LICENSE
+++ b/models/darp7/FSP/LICENSE
@@ -1,46 +0,0 @@
 ************************************************************************
 **                                                                    **
 **                                                                    **
 **      IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING     **
 **                                                                    **
 **                     ANY PORTION OF THE SOFTWARE                    **
 **                                                                    **
 ************************************************************************
 Copyright (c) 2018 Intel Corporation.
 All rights reserved.
 Redistribution.
 Redistribution and use in binary form, without modification, are permitted
 provided that the following conditions are met:
 - Redistributions must reproduce the above copyright notice and the 
 following disclaimer in the documentation and/or other materials provided 
 with the distribution.
 - Neither the name of Intel Corporation nor the names of its suppliers 
 may be used to endorse or promote products derived from this software 
 without specific prior written permission.
 - No reverse engineering, decompilation, or disassembly of this software 
 is permitted.
 "Binary form" includes any format that is commonly used for electronic 
 conveyance that is a reversible, bit-exact translation of binary 
 representation to ASCII or ISO text, for example "uuencode".
 DISCLAIMER.
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
 THE POSSIBILITY OF SUCH DAMAGE.
--- a/models/darp7/README.md
+++ b/models/darp7/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 5116 KB
-  - Version: 15.0.10.1447
+  - Version: 15.0.35.2039
--- a/models/darp7/coreboot.config
+++ b/models/darp7/coreboot.config
@@ -1,29 +1,21 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP7=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
 CONFIG_MAINBOARD_VERSION="darp7"
 CONFIG_ADD_FSP_BINARIES=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
 CONFIG_FSP_M_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_M.fd"
 CONFIG_FSP_S_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_S.fd"
 CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x51a1
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp7/edk2.config
+++ b/models/darp7/edk2.config
@@ -1,2 +1,9 @@
-PCIE_BASE=0xC0000000
+BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp7/me.rom
+++ b/models/darp7/me.rom
--- a/models/darp7/microcode.rom
+++ b/models/darp7/microcode.rom
--- a/models/darp8/FSP
+++ b/models/darp8/FSP
@@ -0,0 +1 @@
 ../gaze17-3050/FSP
--- a/models/darp8/IntelGopDriver.efi
+++ b/models/darp8/IntelGopDriver.efi
--- a/models/darp8/IntelGopDriver.inf
+++ b/models/darp8/IntelGopDriver.inf
@@ -0,0 +1,9 @@
 [Defines]
  INF_VERSION                    = 0x00010005
  BASE_NAME                      = IntelGopDriver
  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
  MODULE_TYPE                    = UEFI_DRIVER
  VERSION_STRING                 = 1.0
 [Binaries.X64]
  PE32|IntelGopDriver.efi|*
--- a/models/darp8/README.md
+++ b/models/darp8/README.md
@@ -0,0 +1,12 @@
 # System76 Darter Pro (darp8)
 ## Contents
 - [EC](./ec.rom)
  - *Read Error: No such file or directory (os error 2)*
 - [FD](./fd.rom)
  - Size: 4 KB
  - HAP: false
 - [ME](./me.rom)
  - Size: 4824 KB
  - Version: 16.0.15.1810
--- a/models/darp8/README.md.in
+++ b/models/darp8/README.md.in
@@ -0,0 +1 @@
 # System76 Darter Pro (darp8)
--- a/models/darp8/chip.txt
+++ b/models/darp8/chip.txt
@@ -0,0 +1 @@
 GD25Q256D
--- a/models/darp8/coreboot-collector.txt
+++ b/models/darp8/coreboot-collector.txt
@@ -0,0 +1,258 @@
 ## PCI ##
 PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x4621, Revision 0x02
 PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x46A6, Revision 0x0C
 PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0x461D, Revision 0x02
 PCI Device: 0000:00:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
 PCI Device: 0000:00:07.0: Class 0x00060400, Vendor 0x8086, Device 0x466E, Revision 0x02
 PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x464F, Revision 0x02
 PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0x467D, Revision 0x01
 PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0x461E, Revision 0x02
 PCI Device: 0000:00:0d.2: Class 0x000C0340, Vendor 0x8086, Device 0x463E, Revision 0x02
 PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0x467F, Revision 0x00
 PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x51ED, Revision 0x01
 PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x51EF, Revision 0x01
 PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x51F0, Revision 0x01
 PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x51E8, Revision 0x01
 PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x51E9, Revision 0x01
 PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x51E0, Revision 0x01
 PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x51BD, Revision 0x01
 PCI Device: 0000:00:1c.7: Class 0x00060400, Vendor 0x8086, Device 0x51BF, Revision 0x01
 PCI Device: 0000:00:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
 PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x5182, Revision 0x01
 PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x51C8, Revision 0x01
 PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x51A3, Revision 0x01
 PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x51A4, Revision 0x01
 PCI Device: 0000:2a:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
 PCI Device: 0000:2b:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
 PCI Device: 10000:e0:06.0: Class 0x00060400, Vendor 0x8086, Device 0x464D, Revision 0x02
 PCI Device: 10000:e0:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x51B0, Revision 0x01
 PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
 PCI Device: 10000:e2:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA808, Revision 0x00
 ## GPIO ##
 600 Series PCH-LP
 GPP_B0 (0x6E,0x00) 0x44000700 0x0003c018 0x00000100 0x00000000
 GPP_B1 (0x6E,0x02) 0x44000700 0x0003c019 0x00000100 0x00000000
 GPP_B2 (0x6E,0x04) 0x44000102 0x0000001a 0x00000000 0x00000000
 GPP_B3 (0x6E,0x06) 0x44000102 0x0000001b 0x00000000 0x00000000
 GPP_B4 (0x6E,0x08) 0x44000100 0x0000001c 0x00000000 0x00000000
 GPP_B5 (0x6E,0x0A) 0x44000102 0x0000001d 0x00000000 0x00000000
 GPP_B6 (0x6E,0x0C) 0x44000102 0x0000001e 0x00000000 0x00000000
 GPP_B7 (0x6E,0x0E) 0x44000102 0x0000001f 0x00000000 0x00000000
 GPP_B8 (0x6E,0x10) 0x44000102 0x00000020 0x00000000 0x00000000
 GPP_B9 (0x6E,0x12) 0x44000102 0x00000021 0x00000000 0x00000000
 GPP_B10 (0x6E,0x14) 0x44000102 0x00000022 0x00000000 0x00000000
 GPP_B11 (0x6E,0x16) 0x04000702 0x00000023 0x00000000 0x00000000
 GPP_B12 (0x6E,0x18) 0x44000700 0x0003c024 0x00000000 0x00000000
 GPP_B13 (0x6E,0x1A) 0x44000700 0x0003c025 0x00000000 0x00000000
 GPP_B14 (0x6E,0x1C) 0x44000500 0x00000026 0x00000000 0x00000000
 GPP_B15 (0x6E,0x1E) 0x44000102 0x00000027 0x00000000 0x00000000
 GPP_B16 (0x6E,0x20) 0x84000201 0x00000028 0x00000000 0x00000000
 GPP_B17 (0x6E,0x22) 0x84000201 0x00000029 0x00000000 0x00000000
 GPP_B18 (0x6E,0x24) 0x44000102 0x0000002a 0x00000100 0x00000000
 GPP_B19 (0x6E,0x26) 0x44000102 0x0000002b 0x00000000 0x00000000
 GPP_B20 (0x6E,0x28) 0x44000102 0x0000002c 0x00000000 0x00000000
 GPP_B21 (0x6E,0x2A) 0x44000102 0x0000002d 0x00000000 0x00000000
 GPP_B22 (0x6E,0x2C) 0x44000102 0x0000002e 0x00000000 0x00000000
 GPP_B23 (0x6E,0x2E) 0x44000102 0x0000002f 0x00000000 0x00000000
 GPP_T2 (0x6E,0x38) 0x44000b00 0x00001032 0x00000000 0x00000000
 GPP_T3 (0x6E,0x3A) 0x44000b00 0x00001033 0x00000000 0x00000000
 GPP_A0 (0x6E,0x54) 0x44000700 0x0003f040 0x00000100 0x00000000
 GPP_A1 (0x6E,0x56) 0x44000702 0x0003f041 0x00000100 0x00000000
 GPP_A2 (0x6E,0x58) 0x44000700 0x0003f042 0x00000100 0x00000000
 GPP_A3 (0x6E,0x5A) 0x44000700 0x0003f043 0x00000100 0x00000000
 GPP_A4 (0x6E,0x5C) 0x44000700 0x0003f044 0x00000100 0x00000000
 GPP_A5 (0x6E,0x5E) 0x44000702 0x00003045 0x00000100 0x00000000
 GPP_A6 (0x6E,0x60) 0x44000102 0x00003046 0x00000100 0x00000000
 GPP_A7 (0x6E,0x62) 0x44000102 0x00000047 0x00000000 0x00000000
 GPP_A8 (0x6E,0x64) 0x84000201 0x00000048 0x00000000 0x00000000
 GPP_A9 (0x6E,0x66) 0x44000700 0x0003d049 0x00000100 0x00000000
 GPP_A10 (0x6E,0x68) 0x44000700 0x0003c04a 0x00000100 0x00000000
 GPP_A11 (0x6E,0x6A) 0x44000102 0x0000004b 0x00000000 0x00000000
 GPP_A12 (0x6E,0x6C) 0x44000702 0x0000304c 0x00000000 0x00000000
 GPP_A13 (0x6E,0x6E) 0x84000201 0x0000004d 0x00000000 0x00000000
 GPP_A14 (0x6E,0x70) 0x44000102 0x0000004e 0x00000000 0x00000000
 GPP_A15 (0x6E,0x72) 0x44000102 0x0000004f 0x00000000 0x00000000
 GPP_A16 (0x6E,0x74) 0x44000702 0x00000050 0x00000000 0x00000000
 GPP_A17 (0x6E,0x76) 0x44000102 0x00000051 0x00000000 0x00000000
 GPP_A18 (0x6E,0x78) 0x44000500 0x00024052 0x00000000 0x00000000
 GPP_A19 (0x6E,0x7A) 0x44000102 0x00000053 0x00000000 0x00000000
 GPP_A20 (0x6E,0x7C) 0x44000102 0x00000054 0x00000000 0x00000000
 GPP_A21 (0x6E,0x7E) 0x44000102 0x00000055 0x00000000 0x00000000
 GPP_A22 (0x6E,0x80) 0x44000102 0x00000056 0x00000000 0x00000000
 GPP_A23 (0x6E,0x82) 0x44000700 0x00003057 0x00000100 0x00000000
 GPP_S0 (0x6D,0x00) 0x44000100 0x0180006c 0x00000000 0x00000000
 GPP_S1 (0x6D,0x02) 0x44000100 0x0180006d 0x00000000 0x00000000
 GPP_S2 (0x6D,0x04) 0x44000100 0x0180006e 0x00000000 0x00000000
 GPP_S3 (0x6D,0x06) 0x44000100 0x0180006f 0x00000000 0x00000000
 GPP_S4 (0x6D,0x08) 0x44000100 0x01800070 0x00000000 0x00000000
 GPP_S5 (0x6D,0x0A) 0x44000100 0x01800071 0x00000000 0x00000000
 GPP_S6 (0x6D,0x0C) 0x44000100 0x01800072 0x00000000 0x00000000
 GPP_S7 (0x6D,0x0E) 0x44000100 0x01800073 0x00000000 0x00000000
 GPP_H0 (0x6D,0x10) 0x84000201 0x00000074 0x00000000 0x00000000
 GPP_H1 (0x6D,0x12) 0x84000201 0x00000075 0x00000000 0x00000000
 GPP_H2 (0x6D,0x14) 0x84000201 0x00000076 0x00000000 0x00000000
 GPP_H3 (0x6D,0x16) 0x44000102 0x00000077 0x00000000 0x00000000
 GPP_H4 (0x6D,0x18) 0x44000502 0x00000018 0x00000000 0x00000000
 GPP_H5 (0x6D,0x1A) 0x44000502 0x00000019 0x00000000 0x00000000
 GPP_H6 (0x6D,0x1C) 0x44000502 0x0000001a 0x00000000 0x00000000
 GPP_H7 (0x6D,0x1E) 0x44000502 0x0000001b 0x00000000 0x00000000
 GPP_H8 (0x6D,0x20) 0x44000902 0x0000001c 0x00000100 0x00000000
 GPP_H9 (0x6D,0x22) 0x44000900 0x0000001d 0x00000100 0x00000000
 GPP_H10 (0x6D,0x24) 0x44000102 0x0000001e 0x00000000 0x00000000
 GPP_H11 (0x6D,0x26) 0x44000102 0x0000001f 0x00000000 0x00000000
 GPP_H12 (0x6D,0x28) 0x44001500 0x00000020 0x00000000 0x00000000
 GPP_H13 (0x6D,0x2A) 0x44000102 0x00000021 0x00000000 0x00000000
 GPP_H14 (0x6D,0x2C) 0x44000102 0x00000022 0x00000000 0x00000000
 GPP_H15 (0x6D,0x2E) 0x44000500 0x0003c023 0x00000000 0x00000000
 GPP_H16 (0x6D,0x30) 0x44000102 0x00000024 0x00000000 0x00000000
 GPP_H17 (0x6D,0x32) 0x44000502 0x0003c025 0x00000000 0x00000000
 GPP_H18 (0x6D,0x34) 0x44000700 0x0003c026 0x00000000 0x00000000
 GPP_H19 (0x6D,0x36) 0x44000700 0x00000027 0x00000000 0x00000000
 GPP_H20 (0x6D,0x38) 0x44000102 0x00000028 0x00000000 0x00000000
 GPP_H21 (0x6D,0x3A) 0x44000102 0x00000029 0x00000000 0x00000000
 GPP_H22 (0x6D,0x3C) 0x44000102 0x0000002a 0x00000000 0x00000000
 GPP_H23 (0x6D,0x3E) 0x44000b02 0x0000002b 0x00000000 0x00000000
 GPP_D0 (0x6D,0x40) 0x44000201 0x0000002c 0x00000000 0x00000000
 GPP_D1 (0x6D,0x42) 0x44000102 0x0000002d 0x00000000 0x00000000
 GPP_D2 (0x6D,0x44) 0x44000200 0x0000002e 0x00000000 0x00000000
 GPP_D3 (0x6D,0x46) 0x44000102 0x0000002f 0x00000000 0x00000000
 GPP_D4 (0x6D,0x48) 0x44000201 0x00000030 0x00000000 0x00000000
 GPP_D5 (0x6D,0x4A) 0x44000700 0x00000031 0x00000000 0x00000000
 GPP_D6 (0x6D,0x4C) 0x44000201 0x00000032 0x00000000 0x00000000
 GPP_D7 (0x6D,0x4E) 0x44000702 0x00000033 0x00000000 0x00000000
 GPP_D8 (0x6D,0x50) 0x44000102 0x00000034 0x00000000 0x00000000
 GPP_D9 (0x6D,0x52) 0x44000102 0x00003c35 0x00000100 0x00000000
 GPP_D10 (0x6D,0x54) 0x44000102 0x00003c36 0x00000100 0x00000000
 GPP_D11 (0x6D,0x56) 0x44000102 0x00003c37 0x00000100 0x00000000
 GPP_D12 (0x6D,0x58) 0x44000102 0x00003c38 0x00000100 0x00000000
 GPP_D13 (0x6D,0x5A) 0x44000102 0x00000039 0x00000000 0x00000000
 GPP_D14 (0x6D,0x5C) 0x84000201 0x0000003a 0x00000000 0x00000000
 GPP_D15 (0x6D,0x5E) 0x44000201 0x0000003b 0x00000000 0x00000000
 GPP_D16 (0x6D,0x60) 0x44000201 0x0000003c 0x00000000 0x00000000
 GPP_D17 (0x6D,0x62) 0x44000102 0x0000003d 0x00000000 0x00000000
 GPP_D18 (0x6D,0x64) 0x44000102 0x0000003e 0x00000000 0x00000000
 GPP_D19 (0x6D,0x66) 0x44000102 0x0000003f 0x00000000 0x00000000
 GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
 GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
 GPD2 (0x6C,0x04) 0x04000702 0x00003c62 0x00000000 0x00000000
 GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
 GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
 GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
 GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
 GPD7 (0x6C,0x0E) 0x04000102 0x00000067 0x00000000 0x00000000
 GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
 GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
 GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
 GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
 GPP_C0 (0x6A,0x00) 0x44000502 0x0003c06e 0x00000000 0x00000000
 GPP_C1 (0x6A,0x02) 0x44000502 0x0003c06f 0x00000000 0x00000000
 GPP_C2 (0x6A,0x04) 0x84000201 0x00000070 0x00000800 0x00000000
 GPP_C3 (0x6A,0x06) 0x44000502 0x00000071 0x00000000 0x00000000
 GPP_C4 (0x6A,0x08) 0x44000502 0x00000072 0x00000000 0x00000000
 GPP_C5 (0x6A,0x0A) 0x44000102 0x00000073 0x00000000 0x00000000
 GPP_C6 (0x6A,0x0C) 0x44000502 0x00000074 0x00000000 0x00000000
 GPP_C7 (0x6A,0x0E) 0x44000502 0x00000075 0x00000000 0x00000000
 GPP_C8 (0x6A,0x10) 0x44000300 0x00000076 0x00000000 0x00000000
 GPP_C9 (0x6A,0x12) 0x44000300 0x00000077 0x00000000 0x00000000
 GPP_C10 (0x6A,0x14) 0x44000300 0x00000018 0x00000000 0x00000000
 GPP_C11 (0x6A,0x16) 0x44000300 0x00000019 0x00000000 0x00000000
 GPP_C12 (0x6A,0x18) 0x44000300 0x0000001a 0x00000000 0x00000000
 GPP_C13 (0x6A,0x1A) 0x44000300 0x0000001b 0x00000000 0x00000000
 GPP_C14 (0x6A,0x1C) 0x44000300 0x0000001c 0x00000000 0x00000000
 GPP_C15 (0x6A,0x1E) 0x44000300 0x0000001d 0x00000000 0x00000000
 GPP_C16 (0x6A,0x20) 0x44000300 0x0000001e 0x00000000 0x00000000
 GPP_C17 (0x6A,0x22) 0x44000300 0x0000001f 0x00000000 0x00000000
 GPP_C18 (0x6A,0x24) 0x44000300 0x00000020 0x00000000 0x00000000
 GPP_C19 (0x6A,0x26) 0x44000300 0x00000021 0x00000000 0x00000000
 GPP_C20 (0x6A,0x28) 0x44000300 0x00000022 0x00000000 0x00000000
 GPP_C21 (0x6A,0x2A) 0x44000300 0x00000023 0x00000000 0x00000000
 GPP_C22 (0x6A,0x2C) 0x44000300 0x00000024 0x00000000 0x00000000
 GPP_C23 (0x6A,0x2E) 0x44000300 0x00000025 0x00000000 0x00000000
 GPP_F0 (0x6A,0x30) 0x44000500 0x0003c056 0x00000100 0x00000000
 GPP_F1 (0x6A,0x32) 0x44000502 0x0003f057 0x00000100 0x00000000
 GPP_F2 (0x6A,0x34) 0x44000500 0x0003c058 0x00000100 0x00000000
 GPP_F3 (0x6A,0x36) 0x44000500 0x0003f059 0x00000100 0x00000000
 GPP_F4 (0x6A,0x38) 0x44000500 0x0003c05a 0x00000100 0x00000000
 GPP_F5 (0x6A,0x3A) 0x44000900 0x0003c05b 0x00000100 0x00000000
 GPP_F6 (0x6A,0x3C) 0x44000502 0x0000005c 0x00000100 0x00000000
 GPP_F7 (0x6A,0x3E) 0x44000102 0x0000005d 0x00000000 0x00000000
 GPP_F8 (0x6A,0x40) 0x44000102 0x0000005e 0x00000000 0x00000000
 GPP_F9 (0x6A,0x42) 0x44000102 0x0000005f 0x00000000 0x00000000
 GPP_F10 (0x6A,0x44) 0x44000102 0x00000060 0x00000000 0x00000000
 GPP_F11 (0x6A,0x46) 0x44000102 0x00000061 0x00000000 0x00000000
 GPP_F12 (0x6A,0x48) 0x44000102 0x00000062 0x00000100 0x00000000
 GPP_F13 (0x6A,0x4A) 0x44000102 0x00000063 0x00000000 0x00000000
 GPP_F14 (0x6A,0x4C) 0x44000100 0x00000064 0x00000000 0x00000000
 GPP_F15 (0x6A,0x4E) 0x44000102 0x00000065 0x00000000 0x00000000
 GPP_F16 (0x6A,0x50) 0x44000102 0x00000066 0x00000000 0x00000000
 GPP_F17 (0x6A,0x52) 0x84000201 0x00000067 0x00000000 0x00000000
 GPP_F18 (0x6A,0x54) 0x44000200 0x00000068 0x00000000 0x00000000
 GPP_F19 (0x6A,0x56) 0x44000702 0x00000069 0x00000000 0x00000000
 GPP_F20 (0x6A,0x58) 0x84000201 0x0003c06a 0x00000000 0x00000000
 GPP_F21 (0x6A,0x5A) 0x44000102 0x0003c06b 0x00000000 0x00000000
 GPP_F22 (0x6A,0x5C) 0x44000500 0x0003c06c 0x00000000 0x00000000
 GPP_F23 (0x6A,0x5E) 0x44000500 0x0003c06d 0x00000000 0x00000000
 GPP_E0 (0x6A,0x6E) 0x44000102 0x00000026 0x00000000 0x00000000
 GPP_E1 (0x6A,0x70) 0x40100102 0x00003027 0x00000000 0x00000000
 GPP_E2 (0x6A,0x72) 0x44000102 0x00000028 0x00000000 0x00000000
 GPP_E3 (0x6A,0x74) 0x84000201 0x00000029 0x00000000 0x00000000
 GPP_E4 (0x6A,0x76) 0x84000200 0x00000030 0x00000000 0x00000000
 GPP_E5 (0x6A,0x78) 0x44000102 0x00000031 0x00000000 0x00000000
 GPP_E6 (0x6A,0x7A) 0x44000102 0x00000032 0x00000900 0x00000000
 GPP_E7 (0x6A,0x7C) 0x44000102 0x00000033 0x00000000 0x00000000
 GPP_E8 (0x6A,0x7E) 0x44000100 0x00000034 0x00000000 0x00000000
 GPP_E9 (0x6A,0x80) 0x44000502 0x00000035 0x00000800 0x00000000
 GPP_E10 (0x6A,0x82) 0x44000102 0x00000036 0x00000800 0x00000000
 GPP_E11 (0x6A,0x84) 0x44000102 0x00000037 0x00000800 0x00000000
 GPP_E12 (0x6A,0x86) 0x40100102 0x00000038 0x00000000 0x00000000
 GPP_E13 (0x6A,0x88) 0x44000102 0x00000039 0x00000000 0x00000000
 GPP_E14 (0x6A,0x8A) 0x44000702 0x0002403a 0x00000000 0x00000000
 GPP_E15 (0x6A,0x8C) 0x44000102 0x0000003b 0x00000000 0x00000000
 GPP_E16 (0x6A,0x8E) 0x44000102 0x0000003c 0x00000000 0x00000000
 GPP_E17 (0x6A,0x90) 0x44000102 0x0000003d 0x00000000 0x00000000
 GPP_E18 (0x6A,0x92) 0x44000300 0x00003c3e 0x00000000 0x00000000
 GPP_E19 (0x6A,0x94) 0x44000300 0x00003c3f 0x00000000 0x00000000
 GPP_E20 (0x6A,0x96) 0x44000102 0x00003c40 0x00000100 0x00000000
 GPP_E21 (0x6A,0x98) 0x44000102 0x00003c41 0x00000100 0x00000000
 GPP_E22 (0x6A,0x9A) 0x44000100 0x00001042 0x00000000 0x00000000
 GPP_E23 (0x6A,0x9C) 0x44000102 0x00000043 0x00000000 0x00000000
 GPP_R0 (0x69,0x00) 0x44000500 0x0003c058 0x00000000 0x00000000
 GPP_R1 (0x69,0x02) 0x44000500 0x0003fc59 0x00000000 0x00000000
 GPP_R2 (0x69,0x04) 0x44000500 0x0003fc5a 0x00000000 0x00000000
 GPP_R3 (0x69,0x06) 0x44000500 0x0003fc5b 0x00000000 0x00000000
 GPP_R4 (0x69,0x08) 0x44000500 0x0003c05c 0x00000000 0x00000000
 GPP_R5 (0x69,0x0A) 0x44000102 0x0000005d 0x00000000 0x00000000
 GPP_R6 (0x69,0x0C) 0x44000102 0x0000005e 0x00000000 0x00000000
 GPP_R7 (0x69,0x0E) 0x44000102 0x0000005f 0x00000000 0x00000000
 ## HDAUDIO ##
 hdaudioC0D0
  vendor_name: Realtek
  chip_name: ALC256
  vendor_id: 0x10ec0256
  subsystem_id: 0x15587716
  revision_id: 0x100002
  0x12: 0x90a60130
  0x13: 0x40000000
  0x14: 0x90170110
  0x18: 0x411111f0
  0x19: 0x411111f0
  0x1a: 0x411111f0
  0x1b: 0x411111f0
  0x1d: 0x41700001
  0x1e: 0x411111f0
  0x21: 0x02211020
 hdaudioC0D2
  vendor_name: Intel
  chip_name: Alderlake-P HDMI
  vendor_id: 0x8086281c
  subsystem_id: 0x80860101
  revision_id: 0x100000
  0x04: 0x18560010
  0x06: 0x18560010
  0x08: 0x18560010
  0x0a: 0x18560010
  0x0b: 0x18560010
  0x0c: 0x18560010
  0x0d: 0x18560010
  0x0e: 0x18560010
  0x0f: 0x18560010
--- a/models/darp8/coreboot.config
+++ b/models/darp8/coreboot.config
@@ -0,0 +1,23 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP8=y
 CONFIG_ADD_FSP_BINARIES=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
 CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
 CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp.fd"
 CONFIG_FSP_FULL_FD=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
 CONFIG_SMMSTORE_V2=y
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp8/ec.config
+++ b/models/darp8/ec.config
@@ -0,0 +1 @@
 BOARD=system76/darp8
--- a/models/darp8/ecspy.txt
+++ b/models/darp8/ecspy.txt
@@ -0,0 +1,89 @@
 id 5570 rev 6
 A0: data 1 mirror 1 pot 0 control 00
 A1: data 0 mirror 0 pot 0 control 00
 A2: data 1 mirror 1 pot 0 control 00
 A3: data 0 mirror 0 pot 0 control 80
 A4: data 1 mirror 1 pot 0 control 44
 A5: data 0 mirror 0 pot 0 control 00
 A6: data 0 mirror 0 pot 0 control 00
 A7: data 0 mirror 1 pot 0 control 00
 B0: data 0 mirror 0 pot 0 control 84
 B1: data 1 mirror 1 pot 0 control 84
 B2: data 1 mirror 1 pot 0 control 44
 B3: data 1 mirror 1 pot 0 control 80
 B4: data 1 mirror 1 pot 0 control 40
 B5: data 0 mirror 0 pot 0 control 44
 B6: data 1 mirror 1 pot 0 control 44
 B7: data 1 mirror 1 pot 0 control 82
 C0: data 1 mirror 1 pot 0 control 80
 C1: data 1 mirror 1 pot 0 control 04
 C2: data 1 mirror 1 pot 0 control 04
 C3: data 0 mirror 0 pot 0 control 04
 C4: data 0 mirror 0 pot 0 control 84
 C5: data 0 mirror 0 pot 0 control 04
 C6: data 0 mirror 0 pot 0 control 82
 C7: data 0 mirror 0 pot 0 control 44
 D0: data 1 mirror 1 pot 0 control 44
 D1: data 1 mirror 1 pot 0 control 44
 D2: data 1 mirror 1 pot 0 control 00
 D3: data 1 mirror 1 pot 0 control 82
 D4: data 1 mirror 1 pot 0 control 80
 D5: data 1 mirror 1 pot 0 control 44
 D6: data 1 mirror 1 pot 0 control 02
 D7: data 0 mirror 0 pot 0 control 80
 E0: data 1 mirror 1 pot 0 control 04
 E1: data 1 mirror 1 pot 0 control 44
 E2: data 0 mirror 0 pot 0 control 84
 E3: data 1 mirror 1 pot 0 control 40
 E4: data 1 mirror 1 pot 0 control 42
 E5: data 1 mirror 1 pot 0 control 40
 E6: data 1 mirror 1 pot 0 control 80
 E7: data 1 mirror 1 pot 0 control 04
 F0: data 0 mirror 0 pot 0 control 44
 F1: data 1 mirror 1 pot 0 control 44
 F2: data 1 mirror 1 pot 0 control 44
 F3: data 0 mirror 0 pot 0 control 82
 F4: data 1 mirror 1 pot 0 control 04
 F5: data 1 mirror 1 pot 0 control 04
 F6: data 0 mirror 0 pot 0 control 00
 F7: data 1 mirror 1 pot 0 control 44
 G0: data 1 mirror 1 pot 0 control 80
 G1: data 1 mirror 1 pot 0 control 44
 G2: data 1 mirror 1 pot 0 control 80
 G3: data 0 mirror 0 pot 0 control 00
 G4: data 0 mirror 0 pot 0 control 00
 G5: data 0 mirror 0 pot 0 control 00
 G6: data 0 mirror 0 pot 0 control 44
 G7: data 0 mirror 0 pot 0 control 00
 H0: data 0 mirror 0 pot 0 control 44
 H1: data 1 mirror 1 pot 0 control 80
 H2: data 1 mirror 1 pot 0 control 44
 H3: data 1 mirror 1 pot 0 control 80
 H4: data 1 mirror 1 pot 0 control 84
 H5: data 0 mirror 0 pot 0 control 40
 H6: data 1 mirror 1 pot 0 control 80
 H7: data 0 mirror 0 pot 0 control 82
 I0: data 0 mirror 0 pot 0 control 00
 I1: data 0 mirror 0 pot 0 control 00
 I2: data 0 mirror 0 pot 0 control 80
 I3: data 0 mirror 0 pot 0 control 80
 I4: data 0 mirror 0 pot 0 control 00
 I5: data 1 mirror 1 pot 0 control 80
 I6: data 1 mirror 1 pot 0 control 80
 I7: data 0 mirror 0 pot 0 control 00
 J0: data 1 mirror 1 pot 0 control 44
 J1: data 1 mirror 1 pot 0 control 40
 J2: data 0 mirror 0 pot 0 control 82
 J3: data 1 mirror 1 pot 0 control 80
 J4: data 1 mirror 1 pot 0 control 40
 J5: data 1 mirror 1 pot 0 control 80
 J6: data 0 mirror 0 pot 0 control 80
 J7: data 1 mirror 1 pot 0 control 80
 M0: data 0 mirror 0 control 06
 M1: data 1 mirror 1 control 06
 M2: data 1 mirror 1 control 06
 M3: data 1 mirror 1 control 06
 M4: data 1 mirror 1 control 06
 M5: data 0 mirror 0 control 00
 M6: data 1 mirror 1 control 86
 M7: data 0 mirror 0 control 00
--- a/models/darp8/edk2.config
+++ b/models/darp8/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp8/fd.rom
+++ b/models/darp8/fd.rom
--- a/models/darp8/gpio.h
+++ b/models/darp8/gpio.h
@@ -0,0 +1,211 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #ifndef __ACPI__
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
 	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
 	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
 	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
 	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
 	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
 	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
 	PAD_CFG_GPI(GPD7, NONE, PWROK),
 	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 	PAD_CFG_GPO(GPD9, 0, PWROK),
 	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
 	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
 	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
 	PAD_CFG_GPI(GPP_A6, UP_20K, DEEP),
 	PAD_CFG_GPI(GPP_A7, NONE, DEEP),
 	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
 	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_A11, NONE, DEEP),
 	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
 	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
 	PAD_CFG_GPI(GPP_A14, NONE, DEEP),
 	PAD_CFG_GPI(GPP_A15, NONE, DEEP),
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_A19, NONE, DEEP),
 	PAD_CFG_GPI(GPP_A20, NONE, DEEP),
 	PAD_CFG_GPI(GPP_A21, NONE, DEEP),
 	PAD_CFG_GPI(GPP_A22, NONE, DEEP),
 	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B4, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B5, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B6, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B7, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B8, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B9, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B10, NONE, DEEP),
 	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_B15, NONE, DEEP),
 	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
 	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
 	PAD_CFG_GPI(GPP_B18, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B19, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B20, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B21, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B22, NONE, DEEP),
 	PAD_CFG_GPI(GPP_B23, NONE, DEEP),
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_C5, NONE, DEEP),
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 	PAD_NC(GPP_C8, NONE),
 	PAD_NC(GPP_C9, NONE),
 	PAD_NC(GPP_C10, NONE),
 	PAD_NC(GPP_C11, NONE),
 	PAD_NC(GPP_C12, NONE),
 	PAD_NC(GPP_C13, NONE),
 	PAD_NC(GPP_C14, NONE),
 	PAD_NC(GPP_C15, NONE),
 	PAD_NC(GPP_C16, NONE),
 	PAD_NC(GPP_C17, NONE),
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_NC(GPP_C20, NONE),
 	PAD_NC(GPP_C21, NONE),
 	PAD_NC(GPP_C22, NONE),
 	PAD_NC(GPP_C23, NONE),
 	PAD_CFG_GPO(GPP_D0, 1, DEEP),
 	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
 	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
 	PAD_CFG_GPO(GPP_D4, 1, DEEP),
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_D8, NONE, DEEP),
 	PAD_CFG_GPI(GPP_D9, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_D10, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_D13, NONE, DEEP),
 	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
 	PAD_CFG_GPO(GPP_D15, 1, DEEP),
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
 	PAD_CFG_GPI(GPP_D18, NONE, DEEP),
 	PAD_CFG_GPI(GPP_D19, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E0, NONE, DEEP),
 	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
 	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
 	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
 	PAD_CFG_GPO(GPP_E4, 0, PLTRST),
 	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E6, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E8, NONE, DEEP),
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
 	_PAD_CFG_STRUCT(GPP_E12, 0x40100100, 0x0000),
 	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_E15, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	PAD_CFG_GPI(GPP_E17, NONE, DEEP),
 	PAD_NC(GPP_E18, NATIVE),
 	PAD_NC(GPP_E19, NATIVE),
 	PAD_CFG_GPI(GPP_E20, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_E21, NATIVE, DEEP),
 	PAD_CFG_GPI(GPP_E22, DN_20K, DEEP),
 	PAD_CFG_GPI(GPP_E23, NONE, DEEP),
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
 	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_F7, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F9, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F10, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F11, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F12, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F13, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F14, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
 	PAD_CFG_GPI(GPP_F16, NONE, DEEP),
 	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
 	PAD_CFG_GPO(GPP_F18, 0, DEEP),
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
 	PAD_CFG_GPI(GPP_F21, NONE, DEEP),
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	PAD_CFG_GPO(GPP_H1, 1, PLTRST),
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	PAD_CFG_GPI(GPP_H3, NONE, DEEP),
 	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
 	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
 	PAD_CFG_GPI(GPP_H10, NONE, DEEP),
 	PAD_CFG_GPI(GPP_H11, NONE, DEEP),
 	_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000),
 	PAD_CFG_GPI(GPP_H13, NONE, DEEP),
 	PAD_CFG_GPI(GPP_H14, NONE, DEEP),
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_H16, NONE, DEEP),
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_H20, NONE, DEEP),
 	PAD_CFG_GPI(GPP_H21, NONE, DEEP),
 	PAD_CFG_GPI(GPP_H22, NONE, DEEP),
 	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
 	PAD_CFG_GPI(GPP_R5, NONE, DEEP),
 	PAD_CFG_GPI(GPP_R6, NONE, DEEP),
 	PAD_CFG_GPI(GPP_R7, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S1, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S2, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S3, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S4, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S5, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S6, NONE, DEEP),
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP),
 	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),
 	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),
 };
 #endif
 #endif
--- a/models/darp8/hda_verb.c
+++ b/models/darp8/hda_verb.c
@@ -0,0 +1,39 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 #include <device/azalia_device.h>
 const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x15587716, /* Subsystem ID */
 	11, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15587716),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
 	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
 	/* Intel, Alderlake-PHDMI */
 	0x8086281c, /* Vendor ID */
 	0x80860101, /* Subsystem ID */
 	10, /* Number of entries */
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
 };
 const u32 pc_beep_verbs[] = {};
 AZALIA_ARRAY_SIZES;
--- a/models/darp8/me.rom
+++ b/models/darp8/me.rom
--- a/models/darp8/microcode.rom
+++ b/models/darp8/microcode.rom
--- a/models/darp8/vbt.rom
+++ b/models/darp8/vbt.rom
--- a/models/galp2/coreboot.config
+++ b/models/galp2/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP2=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
 CONFIG_MAINBOARD_VERSION="galp2"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,14 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1303
+CONFIG_SMMSTORE_V2=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
 CONFIG_USE_ME_CLEANER=y
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp2/edk2.config
+++ b/models/galp2/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3-b/coreboot.config
+++ b/models/galp3-b/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3_B=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
 CONFIG_MAINBOARD_VERSION="galp3-b"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,14 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1413
+CONFIG_SMMSTORE_V2=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
 CONFIG_USE_ME_CLEANER=y
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3-b/edk2.config
+++ b/models/galp3-b/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3-c/coreboot.config
+++ b/models/galp3-c/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3_C=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
 CONFIG_MAINBOARD_VERSION="galp3-c"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,7 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1323
+CONFIG_SMMSTORE_V2=y
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3-c/edk2.config
+++ b/models/galp3-c/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3/coreboot.config
+++ b/models/galp3/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3=y
 CONFIG_MAINBOARD_VERSION="galp3"
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,14 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
 CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1313
+CONFIG_SMMSTORE_V2=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
 CONFIG_USE_ME_CLEANER=y
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3/edk2.config
+++ b/models/galp3/edk2.config
@@ -0,0 +1,9 @@
 BOOTLOADER=COREBOOT
 DISABLE_SERIAL_TERMINAL=TRUE
 PLATFORM_BOOT_TIMEOUT=2
 PS2_KEYBOARD_ENABLE=TRUE
 #SECURE_BOOT_ENABLE=TRUE
 SERIAL_DRIVER_ENABLE=FALSE
 SHELL_TYPE=NONE
 TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp4/FSP/Fsp_M.fd
+++ b/models/galp4/FSP/Fsp_M.fd
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Jeremy Soller	e83d313a57	Update kudu6 chip	2022-07-09 19:51:55 -06:00
Jeremy Soller	29e8b9e68f	Add PSPTool	2022-07-09 19:51:55 -06:00
Jeremy Soller	8f0130d4ba	Update EC	2022-07-09 19:51:55 -06:00
Jeremy Soller	71e796f2a7	Make kudu6 buildable	2022-07-09 19:51:55 -06:00
Jeremy Soller	daed802178	Update coreboot	2022-07-09 19:51:55 -06:00
Jeremy Soller	5568ec8eba	Add kudu6 extract	2022-07-09 19:42:09 -06:00
Tim Crawford	1add7eec31	Add info and text for firmware binaries licenses Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-07 22:56:47 -06:00
Tim Crawford	62f4da99a1	lemp11: Fix PL2/PL4 power limits Fix power limit config override so board does not power off under load while on battery power. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-07-05 14:52:33 -06:00
Tim Crawford	fb33c3f984	changelog: Update for lemp11 release Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-29 16:21:17 -06:00
Tim Crawford	dda04c8be5	lemp11: Update CSME Disable Boot Guard, PTT, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-29 16:21:17 -06:00
Tim Crawford	21725b41da	lemp11: Add Lemur Pro 11 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-29 16:21:17 -06:00
Tim Crawford	fe2ff86412	changelog: Update for darp8 release Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-23 13:25:14 -06:00
Tim Crawford	0fc98006e0	darp8: Fix SATA detection Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-23 13:25:14 -06:00
Tim Crawford	b2d8bda2b9	docs: Add note about regenerating CSME CSME image may need to be configured to disable PTT, Boot Guard, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-22 09:36:04 -06:00
Tim Crawford	143af4d549	darp8: Update CSME Disable Boot Guard, PTT, and locking of the descriptor. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-22 09:36:04 -06:00
Tim Crawford	3af446e772	darp8: Add Darter Pro 8 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-06-22 09:36:04 -06:00
Jeremy Soller	090f9e035d	Update coreboot	2022-06-07 07:12:55 -06:00
Jeremy Soller	6d75138d2f	Update coreboot	2022-06-06 11:43:08 -06:00
Jeremy Soller	54b0f83ec1	Update submodules	2022-05-27 12:55:17 -06:00
Tim Crawford	4aa8a81be1	deps: Call EC deps script Remove EC-specific dependencies and call the EC script to install them instead. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-05-25 13:10:29 -06:00
Jeremy Soller	774517b8ff	gaze17-3060-b: run end of manufacturing on first boot	2022-05-24 08:23:06 -06:00
Tim Crawford	3a5b4224ac	coreboot: Drop custom TPM configs The `TPM_MEASURED_BOOT` configs have been enabled upstream so are not needed. TPM2 is working on gaze17, so drop the `TPM2` selection as well. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-05-16 12:40:59 -07:00
Jeremy Soller	c69ca152da	Update changelog	2022-05-16 12:40:59 -07:00
Jeremy Soller	f855f47ad6	Update firmware-update	2022-05-16 12:40:59 -07:00
Jeremy Soller	0f5d4de779	Add gaze17	2022-05-16 12:40:59 -07:00
Jeremy Soller	fd9d73bdb9	Update submodules	2022-05-16 12:40:59 -07:00
Jeremy Soller	ef56bc8925	scripts/generate: Fix use of wrong Rust toolchain	2022-05-16 12:40:59 -07:00
Tim Crawford	650b9843d3	Update submodules Updates: - apps/firmware-setup - libs/coreboot-table - libs/uefi - tools/MEAnalyzer - tools/UEFITool - tools/coreboot-collector - tools/ipxe Removes: - libs/ecflash: Available through ec - libs/uefi_alloc: Part of uefi - libs/uefi_std: Part of uefi Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-04-26 13:21:49 -06:00
Tim Crawford	a3de5620ab	Remove unME11/unME12 The Positive Technologies org is no longer available on GitHub. As these tools were never directly used, just remove them. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-04-14 07:21:25 -06:00
Tim Crawford	05577baab2	qemu: Enable KVM Fixes performance issues when running a QEMU VM. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-03-10 10:14:09 -07:00
Tim Crawford	b3242efba6	docs: Add info for enabling debug logging Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-02-28 16:00:54 -07:00
Tim Crawford	cf7fc2c540	scripts: Update rustup or inform user of env vars Ensure rustup is up-to-date to avoid users having a version that is too old to support the TOML format. If rustup was just installed, tell the user to source the new env vars to use the correct version of the toolchain. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-02-28 16:00:54 -07:00
Tim Crawford	10c256d6fa	readme: Rewrite info for building Replace the headers with setences. Provide a brief description on the different methods to flash and link to `flashing.md` for more details. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-02-28 16:00:54 -07:00
Tim Crawford	998378efcc	models: Add edk2 config for QEMU Ensure QEMU builds with the correct edk2 options by providing a config file like the other models. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-02-28 16:00:54 -07:00
Tim Crawford	9e09461c65	scripts: Change QEMU binary name `kvm` is a symlink to the `qemu-system-x86_64`. Use this name instead so the script can be used on other distros without modification. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-02-28 16:00:54 -07:00
Jeremy Soller	8c343acafe	Update changelog	2022-02-15 07:53:49 -07:00
Jeremy Soller	aff1f133d7	Update EC	2022-02-15 07:50:36 -07:00
Jeremy Soller	e8d7c8e636	Update IFD and ME for all models	2022-02-03 08:58:23 -07:00
Tim Crawford	239e2cbaed	build.sh: Set git-describe length Specify `abbrev` to ensure the length of the commit hash is always the same, in case `core.abbrev` is set or the default changes. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-18 11:57:12 -07:00
Tim Crawford	417e5898da	models: Set coreboot, PS/2 keyboard in edk2 config Set BOOTLOADER and PS2_KEYBOARD_ENABLE in the edk2 config. This will allow us to drop the corresponding commits in edk2 when rebasing on the next stable release. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-12 13:49:19 -07:00
Tim Crawford	17cf8b1334	github: Add issue template Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-07 18:32:50 -07:00
Tim Crawford	c73e48228b	coreboot: Fix lemp10 boot - Fix lemp10 memory info to prevent an error message in cbmem. - Fix booting lemp10 with DIMM not present. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-06 13:20:17 -07:00
Tim Crawford	1dc7780b1c	edk2: Add back boot text about Pop!_OS Recovery Preserve existing UI and add the note about pressing Space to go to the systemd-boot menu for Pop!_OS Recovery. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 15:43:49 -07:00
Tim Crawford	d38ec4e972	changelog: Set date for release Use the date of this commit as the release date. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	8d9fbd1e3c	models: Enable coreboot measured boot All the laptops contain a TPM 2.0 chip. Enable the measured boot security feature by default. Link: https://doc.coreboot.org/security/vboot/measured_boot.html Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	8c88ca0252	docs: Add notes about UEFI features Document that only UEFI booting is supported, the current status of Secure Boot, and that the shell and networking are disabled. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	9c63db4c9f	docs: Update Intel ME info Document the new CMOS option for enabling/disabling the IME. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	92a601fbb7	Add changelog entry Remove 2021-09-29 section, as the change was released in 2021-09-30. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	dbe7213ecf	Remove top-level README.md.in - The generated "Contents" section isn't useful - Non-standard, causing confusion on how to update README.md - It's already out of sync Remove galp3-c and darp5, as we never released the firmware due to issues with the touchpad and keyboard. Add gaze16-3060-b variant. Make "Schematics" a subsection of "Supported models". Remove directory from list of paths to update in `scripts/readmes.sh`. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	3e4688fcbc	Remove libs/smmstore Replace the stand-alone smmstore app in favor of the read example in firmware-smmstore. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	ffdceb5f0b	Update Rust toolchain to 2021-06-15 Update the toolchain to the version used by Redox. Update a lot of the submodules, which have been updated to build on the new toolchain. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	fa98ecae1f	edk2: Rebase on edk2-stable202108 Set options in edk2.config for each board. PCIE_BASE is no longer an edk2 option. The value is expected to be in AcpiBoardInfo HOB, generated from the bootloader's ACPI table. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	af955613e0	models: Enable SMMSTOREv2 in coreboot Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	5b4dbd9c53	coreboot: Rebase on 4.15 Rebase on upstream coreboot/coreboot@5622666396. The is slightly ahead of the 4.15 tag, but includes all of our boards and most Intel SoC changes we need. We are now ~10 patches on top of upstream. The following boards have been upstreamed: - addw1 - addw2 - bonw14 - darp5 - darp6 - darp7 - galp2 - galp3-b - galp3-c - galp4 - galp5 - gaze14 - gaze15 - gaze16 - lemp10 - oryp5 - oryp6 - oryp7 - oryp8 The following drivers have been upstreamed: - tas5825m microcode: - TGL-U boards have been updated to rev 0x9a from private repo - TGL-H boards have been updated to rev 0x3c from private repo - Remaining boards changed to use blobs from public repo FSP: - TGL changed to use A.0.51.31 from public repo Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
		`@@ -1 +0,0 @@`
			`../../../FSP/CometLakeFspBinPkg/CometLake1/Include`