358 lines
12 KiB
C
358 lines
12 KiB
C
/** @file
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Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0040
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0044
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0048
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x004C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0050
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0060 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0061 - PcdSerialIoUartNumber
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x0063
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**/
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UINT8 Rsvd00;
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/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0068 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0070 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartRtsPinMux;
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/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
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Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartCtsPinMux;
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/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIoUartDebugMmioBase;
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/** Offset 0x008C - PcdLpcUartDebugEnable
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Enable to initialize LPC Uart device in FSP.
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0:Disable, 1:Enable
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**/
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UINT8 PcdLpcUartDebugEnable;
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/** Offset 0x008D - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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BIT2 - Not used.
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**/
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UINT8 PcdDebugInterfaceFlags;
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/** Offset 0x008E - PcdSerialDebugLevel
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Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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/** Offset 0x008F - ISA Serial Base selection
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Select ISA Serial Base address. Default is 0x3F8.
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0:0x3F8, 1:0x2F8
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**/
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UINT8 PcdIsaSerialUartBase;
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/** Offset 0x0090 - PcdSerialIo2ndUartEnable
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Enable Additional SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIo2ndUartEnable;
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/** Offset 0x0091 - PcdSerialIo2ndUartNumber
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Select SerialIo Uart Controller Number
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIo2ndUartNumber;
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/** Offset 0x0092 - PcdSerialIo2ndUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIo2ndUartMode;
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/** Offset 0x0093
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**/
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UINT8 Rsvd01;
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/** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIo2ndUartBaudRate;
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/** Offset 0x0098 - PcdSerialIo2ndUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIo2ndUartParity;
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/** Offset 0x0099 - PcdSerialIo2ndUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIo2ndUartDataBits;
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/** Offset 0x009A - PcdSerialIo2ndUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIo2ndUartStopBits;
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/** Offset 0x009B - PcdSerialIo2ndUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIo2ndUartAutoFlow;
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/** Offset 0x009C - PcdSerialIo2ndUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartRxPinMux;
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/** Offset 0x00A0 - PcdSerialIo2ndUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartTxPinMux;
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/** Offset 0x00A4 - PcdSerialIo2ndUartRtsPinMux - FSPT
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Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartRtsPinMux;
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/** Offset 0x00A8 - PcdSerialIo2ndUartCtsPinMux - FSPT
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Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartCtsPinMux;
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/** Offset 0x00AC - PcdSerialIo2ndUartMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIo2ndUartMmioBase;
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/** Offset 0x00B0
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**/
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UINT32 TopMemoryCacheSize;
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/** Offset 0x00B4 - FspDebugHandler
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<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
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**/
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UINT32 FspDebugHandler;
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/** Offset 0x00B8 - Serial Io SPI Chip Select Polarity
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Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
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1:SerialIoSpiCsActiveHigh
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**/
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UINT8 PcdSerialIoSpiCsPolarity[2];
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/** Offset 0x00BA - Serial Io SPI Chip Select Enable
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0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
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**/
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UINT8 PcdSerialIoSpiCsEnable[2];
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/** Offset 0x00BC - Serial Io SPI Device Mode
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When mode is set to Pci, controller is initalized in early stage. Available modes:
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0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
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**/
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UINT8 PcdSerialIoSpiMode;
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/** Offset 0x00BD - Serial Io SPI Default Chip Select Output
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Sets Default CS as Output. Available options: 0:CS0, 1:CS1
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**/
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UINT8 PcdSerialIoSpiDefaultCsOutput;
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/** Offset 0x00BE - Serial Io SPI Default Chip Select Mode HW/SW
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Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
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**/
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UINT8 PcdSerialIoSpiCsMode;
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/** Offset 0x00BF - Serial Io SPI Default Chip Select State Low/High
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Sets Default CS State Low or High. Available options: 0:Low, 1:High
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**/
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UINT8 PcdSerialIoSpiCsState;
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/** Offset 0x00C0 - Serial Io SPI Device Number
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Select which Serial Io SPI controller is initalized in early stage.
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**/
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UINT8 PcdSerialIoSpiNumber;
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/** Offset 0x00C1
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**/
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UINT8 Rsvd02[3];
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/** Offset 0x00C4 - Serial Io SPI Device MMIO Base
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Assigns MMIO for Serial Io SPI controller usage in early stage.
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**/
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UINT32 PcdSerialIoSpiMmioBase;
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/** Offset 0x00C8
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**/
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UINT8 ReservedFsptUpd1[16];
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} FSP_T_CONFIG;
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/** Fsp T UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000
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**/
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FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020
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**/
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FSPT_ARCH_UPD FsptArchUpd;
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/** Offset 0x0040
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**/
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FSPT_CORE_UPD FsptCoreUpd;
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/** Offset 0x0060
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**/
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FSP_T_CONFIG FsptConfig;
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/** Offset 0x00D8
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**/
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UINT8 Rsvd03[6];
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/** Offset 0x00DE
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**/
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UINT16 UpdTerminator;
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} FSPT_UPD;
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#pragma pack()
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#endif
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