270 lines
11 KiB
C
270 lines
11 KiB
C
/** @file
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This file contains definitions required for creation of
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Memory S3 Save data, Memory Info data and Memory Platform
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data hobs.
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@copyright
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Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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**/
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#ifndef _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryInfoDataGuid;
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extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define MAX_NODE 1
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#define MAX_CH 2
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#define MAX_DIMM 2
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///
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/// Host reset states from MRC.
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///
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#define WARM_BOOT 2
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#define R_MC_CHNL_RANK_PRESENT 0x7C
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#define B_RANK0_PRS BIT0
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#define B_RANK1_PRS BIT1
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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//
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// Matches MAX_SPD_SAVE define in MRC
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//
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#ifndef MAX_SPD_SAVE
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#define MAX_SPD_SAVE 29
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#endif
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//
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// MRC version description.
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//
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typedef struct {
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UINT8 Major; ///< Major version number
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UINT8 Minor; ///< Minor version number
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UINT8 Rev; ///< Revision number
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UINT8 Build; ///< Build number
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} SiMrcVersion;
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//
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// Matches MrcChannelSts enum in MRC
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//
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#ifndef CHANNEL_NOT_PRESENT
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#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
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#endif
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#ifndef CHANNEL_DISABLED
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#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
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#endif
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#ifndef CHANNEL_PRESENT
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#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
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#endif
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//
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// Matches MrcDimmSts enum in MRC
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//
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#ifndef DIMM_ENABLED
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#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
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#endif
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#ifndef DIMM_DISABLED
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#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
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#endif
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#ifndef DIMM_PRESENT
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#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
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#endif
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#ifndef DIMM_NOT_PRESENT
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#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
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#endif
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//
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// Matches MrcBootMode enum in MRC
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//
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#ifndef bmCold
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#define bmCold 0 // Cold boot
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#endif
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#ifndef bmWarm
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#define bmWarm 1 // Warm boot
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#endif
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#ifndef bmS3
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#define bmS3 2 // S3 resume
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#endif
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#ifndef bmFast
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#define bmFast 3 // Fast boot
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#endif
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_DDR4
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#define MRC_DDR_TYPE_DDR4 0
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#endif
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#ifndef MRC_DDR_TYPE_DDR3
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#define MRC_DDR_TYPE_DDR3 1
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR3
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#define MRC_DDR_TYPE_LPDDR3 2
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#endif
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#ifndef CPU_CFL//CNL
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#ifndef MRC_DDR_TYPE_LPDDR4
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#define MRC_DDR_TYPE_LPDDR4 3
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#endif
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#else//CFL
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 3
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#endif
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#endif//CPU_CFL-endif
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#define MAX_PROFILE_NUM 4 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
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//
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// DIMM timings
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//
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typedef struct {
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UINT32 tCK; ///< Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
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UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
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UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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} MRC_CH_TIMING;
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typedef struct {
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UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
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UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
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UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
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UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
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} MRC_TA_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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typedef struct {
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId;
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
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} DIMM_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
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} CONTROLLER_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
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UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT32 TotalPhysicalMemorySize;
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
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UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
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UINT8 Ratio;
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UINT8 RefClk;
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UINT32 VddVoltage[MAX_PROFILE_NUM];
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CONTROLLER_INFO Controller[MAX_NODE];
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} MEMORY_INFO_DATA_HOB;
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/**
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Memory Platform Data Hob
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2:</b>
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- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT8 Reserved[3];
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UINT32 BootMode;
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT32 PrmrrBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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#ifdef CPU_CFL
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UINT32 GdxcIotBase;
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UINT32 GdxcIotSize;
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UINT32 GdxcMotBase;
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UINT32 GdxcMotSize;
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#endif //CPU_CFL
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType;
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MEMORY_PLATFORM_DATA Data;
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UINT8 *Buffer;
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} MEMORY_PLATFORM_DATA_HOB;
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#pragma pack (pop)
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#endif // _MEM_INFO_HOB_H_
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