114 lines
6.0 KiB
Plaintext
114 lines
6.0 KiB
Plaintext
## @file
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# Platform description for DynamicEx PCDs, defined in FSP Package
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# and shared with Board Package.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2018 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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# the terms of your license agreement with Intel or your vendor. This file may
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# be modified by the user, subject to additional terms of the license agreement.
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#
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# @par Specification
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##
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[PcdsDynamicExDefault]
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processorss
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
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gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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## Specifies the base address of the first microcode Patch in the microcode Region.
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# @Prompt Microcode Region base address.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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## Specifies the AP target C-state for Mwait during POST phase.
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# The default value 0 means C1 state.
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# The value is defined as below.<BR><BR>
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# @Prompt The specified AP target C-state for Mwait.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
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#
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# Enable ACPI S3 support in FSP by default
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1
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## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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# @Prompt The pointer to a CPU S3 data buffer.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00
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## As input, specifies user's desired settings for enabling/disabling processor features.
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## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
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# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# @Prompt The memory size used for processor trace if processor trace is enabled.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0
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## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# @Prompt The processor trace output scheme used when processor trace is enabled.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0
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## Indicates processor feature capabilities, each bit corresponding to a specific feature.
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# @Prompt Processor feature capabilities.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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# Set SEV-ES defaults
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gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
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gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
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## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library
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# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
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# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
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# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
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# @Prompt S3 Boot Script Table Private Data pointer.
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
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## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library
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# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
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# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
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# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
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# @Prompt S3 Boot Script Table Private Smm Data pointer.
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# @ValidList 0x80000001 | 0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 |