291 lines
8.5 KiB
C
291 lines
8.5 KiB
C
/** @file FsptUpd.h
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@copyright
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0020
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0024
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0028
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x002C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0030
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0041 - PcdSerialIoUartNumber
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x0043
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**/
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UINT8 UnusedUpdSpace0;
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/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0048 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0050 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartRtsPinMux;
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/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
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Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartCtsPinMux;
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/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIoUartDebugMmioBase;
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/** Offset 0x006C - PcdLpcUartDebugEnable
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Enable to initialize LPC Uart device in FSP.
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0:Disable, 1:Enable
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**/
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UINT8 PcdLpcUartDebugEnable;
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/** Offset 0x006D - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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BIT2 - Not used.
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**/
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UINT8 PcdDebugInterfaceFlags;
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/** Offset 0x006E - PcdSerialDebugLevel
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Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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/** Offset 0x006F - ISA Serial Base selection
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Select ISA Serial Base address. Default is 0x3F8.
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0:0x3F8, 1:0x2F8
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**/
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UINT8 PcdIsaSerialUartBase;
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/** Offset 0x0070 - PcdSerialIo2ndUartEnable
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Enable Additional SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIo2ndUartEnable;
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/** Offset 0x0071 - PcdSerialIo2ndUartNumber
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Select SerialIo Uart Controller Number
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIo2ndUartNumber;
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/** Offset 0x0072 - PcdSerialIo2ndUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIo2ndUartMode;
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/** Offset 0x0073
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**/
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UINT8 UnusedUpdSpace1;
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/** Offset 0x0074 - PcdSerialIo2ndUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIo2ndUartBaudRate;
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/** Offset 0x0078 - PcdSerialIo2ndUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIo2ndUartParity;
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/** Offset 0x0079 - PcdSerialIo2ndUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIo2ndUartDataBits;
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/** Offset 0x007A - PcdSerialIo2ndUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIo2ndUartStopBits;
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/** Offset 0x007B - PcdSerialIo2ndUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIo2ndUartAutoFlow;
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/** Offset 0x007C - PcdSerialIo2ndUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartRxPinMux;
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/** Offset 0x0080 - PcdSerialIo2ndUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartTxPinMux;
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/** Offset 0x0084 - PcdSerialIo2ndUartRtsPinMux - FSPT
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Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartRtsPinMux;
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/** Offset 0x0088 - PcdSerialIo2ndUartCtsPinMux - FSPT
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Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartCtsPinMux;
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/** Offset 0x008C - PcdSerialIo2ndUartMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIo2ndUartMmioBase;
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/** Offset 0x0090
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**/
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UINT32 TopMemoryCacheSize;
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/** Offset 0x0094 - FspDebugHandler
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<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
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**/
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UINT32 FspDebugHandler;
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/** Offset 0x0098
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**/
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UINT8 UnusedUpdSpace2[4];
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/** Offset 0x009C
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**/
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UINT8 ReservedFsptUpd1[20];
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} FSP_T_CONFIG;
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/** Fsp T UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000
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**/
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FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020
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**/
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FSPT_CORE_UPD FsptCoreUpd;
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/** Offset 0x0040
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**/
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FSP_T_CONFIG FsptConfig;
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/** Offset 0x00B0
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**/
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UINT8 UnusedUpdSpace3[6];
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/** Offset 0x00B6
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**/
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UINT16 UpdTerminator;
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} FSPT_UPD;
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#pragma pack()
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#endif
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