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@@ -64,760 +64,3 @@ index 2c7171e0b0010..85de313ddec29 100644
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select CPU_FREQ_GOV_PERFORMANCE
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help
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From 7695eb71d0872ed9633daf0ca779da3344b87dec Mon Sep 17 00:00:00 2001
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From: Evan Quan <evan.quan@amd.com>
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Date: Mon, 21 Aug 2023 14:15:13 +0800
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Subject: [PATCH] drm/amd/pm: correct SMU13 gfx voltage related OD settings
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The voltage offset setting will be applied to the whole v/f curve line
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instead of per anchor point base.
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Signed-off-by: Evan Quan <evan.quan@amd.com>
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Acked-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/amd/pm/amdgpu_pm.c | 45 +++++++------------
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 31 ++++++-------
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 31 ++++++-------
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3 files changed, 43 insertions(+), 64 deletions(-)
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diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
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index 1da7ece4c627..06aa5c18b40f 100644
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--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
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+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
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@@ -643,18 +643,14 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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* They can be used to calibrate the sclk voltage curve. This is
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* available for Vega20 and NV1X.
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*
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- * - voltage offset for the six anchor points of the v/f curve labeled
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- * OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This
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- * is only availabe for some SMU13 ASICs.
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- *
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* - voltage offset(in mV) applied on target voltage calculation.
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- * This is available for Sienna Cichlid, Navy Flounder and Dimgrey
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- * Cavefish. For these ASICs, the target voltage calculation can be
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- * illustrated by "voltage = voltage calculated from v/f curve +
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- * overdrive vddgfx offset"
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+ * This is available for Sienna Cichlid, Navy Flounder, Dimgrey
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+ * Cavefish and some later SMU13 ASICs. For these ASICs, the target
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+ * voltage calculation can be illustrated by "voltage = voltage
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+ * calculated from v/f curve + overdrive vddgfx offset"
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*
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- * - a list of valid ranges for sclk, mclk, and voltage curve points
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- * labeled OD_RANGE
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+ * - a list of valid ranges for sclk, mclk, voltage curve points
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+ * or voltage offset labeled OD_RANGE
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*
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* < For APUs >
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*
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@@ -686,24 +682,17 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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* E.g., "p 2 0 800" would set the minimum core clock on core
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* 2 to 800Mhz.
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*
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- * For sclk voltage curve,
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- * - For NV1X, enter the new values by writing a string that
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- * contains "vc point clock voltage" to the file. The points
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- * are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update
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- * point1 with clock set as 300Mhz and voltage as 600mV. "vc 2
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- * 1000 1000" will update point3 with clock set as 1000Mhz and
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- * voltage 1000mV.
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- * - For SMU13 ASICs, enter the new values by writing a string that
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- * contains "vc anchor_point_index voltage_offset" to the file.
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- * There are total six anchor points defined on the v/f curve with
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- * index as 0 - 5.
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- * - "vc 0 10" will update the voltage offset for point1 as 10mv.
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- * - "vc 5 -10" will update the voltage offset for point6 as -10mv.
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- *
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- * To update the voltage offset applied for gfxclk/voltage calculation,
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- * enter the new value by writing a string that contains "vo offset".
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- * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
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- * And the offset can be a positive or negative value.
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+ * For sclk voltage curve supported by Vega20 and NV1X, enter the new
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+ * values by writing a string that contains "vc point clock voltage"
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+ * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
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+ * 600" will update point1 with clock set as 300Mhz and voltage as 600mV.
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+ * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
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+ * voltage 1000mV.
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+ *
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+ * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
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+ * Cavefish and some later SMU13 ASICs, enter the new value by writing a
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+ * string that contains "vo offset". E.g., "vo -10" will update the extra
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+ * voltage offset applied to the whole v/f curve line as -10mv.
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*
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* - When you have edited all of the states as needed, write "c" (commit)
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* to the file to commit your changes
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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index 3903a47669e4..bd0d5f027cac 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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@@ -1304,16 +1304,14 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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od_table->OverDriveTable.UclkFmax);
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break;
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- case SMU_OD_VDDC_CURVE:
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+ case SMU_OD_VDDGFX_OFFSET:
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if (!smu_v13_0_0_is_od_feature_supported(smu,
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PP_OD_FEATURE_GFX_VF_CURVE_BIT))
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break;
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- size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
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- for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
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- size += sysfs_emit_at(buf, size, "%d: %dmv\n",
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- i,
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- od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]);
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+ size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
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+ size += sysfs_emit_at(buf, size, "%dmV\n",
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+ od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
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break;
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case SMU_OD_RANGE:
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@@ -1355,7 +1353,7 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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PP_OD_FEATURE_GFX_VF_CURVE,
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&min_value,
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&max_value);
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- size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n",
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+ size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
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min_value, max_value);
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}
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break;
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@@ -1504,29 +1502,26 @@ static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
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}
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break;
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- case PP_OD_EDIT_VDDC_CURVE:
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+ case PP_OD_EDIT_VDDGFX_OFFSET:
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if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
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- dev_warn(adev->dev, "VF curve setting not supported!\n");
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+ dev_warn(adev->dev, "Gfx offset setting not supported!\n");
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return -ENOTSUPP;
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}
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- if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS ||
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- input[0] < 0)
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- return -EINVAL;
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-
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smu_v13_0_0_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFX_VF_CURVE,
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&minimum,
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&maximum);
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- if (input[1] < minimum ||
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- input[1] > maximum) {
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+ if (input[0] < minimum ||
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+ input[0] > maximum) {
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dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
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- input[1], minimum, maximum);
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+ input[0], minimum, maximum);
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return -EINVAL;
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}
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- od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1];
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- od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT;
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+ for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
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+ od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
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+ od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
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break;
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case PP_OD_RESTORE_DEFAULT_TABLE:
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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index 94ef5b4d116d..b9b3bf41eed3 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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@@ -1284,16 +1284,14 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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od_table->OverDriveTable.UclkFmax);
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break;
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- case SMU_OD_VDDC_CURVE:
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+ case SMU_OD_VDDGFX_OFFSET:
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if (!smu_v13_0_7_is_od_feature_supported(smu,
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PP_OD_FEATURE_GFX_VF_CURVE_BIT))
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break;
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- size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
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- for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
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- size += sysfs_emit_at(buf, size, "%d: %dmv\n",
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- i,
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- od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]);
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+ size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
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+ size += sysfs_emit_at(buf, size, "%dmV\n",
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+ od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
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break;
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case SMU_OD_RANGE:
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@@ -1335,7 +1333,7 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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PP_OD_FEATURE_GFX_VF_CURVE,
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&min_value,
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&max_value);
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- size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n",
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+ size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
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min_value, max_value);
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}
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break;
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@@ -1484,29 +1482,26 @@ static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
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}
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break;
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- case PP_OD_EDIT_VDDC_CURVE:
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+ case PP_OD_EDIT_VDDGFX_OFFSET:
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if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
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- dev_warn(adev->dev, "VF curve setting not supported!\n");
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+ dev_warn(adev->dev, "Gfx offset setting not supported!\n");
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return -ENOTSUPP;
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}
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- if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS ||
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- input[0] < 0)
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- return -EINVAL;
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-
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFX_VF_CURVE,
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&minimum,
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&maximum);
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- if (input[1] < minimum ||
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- input[1] > maximum) {
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+ if (input[0] < minimum ||
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+ input[0] > maximum) {
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dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
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- input[1], minimum, maximum);
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+ input[0], minimum, maximum);
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return -EINVAL;
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}
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- od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1];
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- od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT;
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+ for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
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+ od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
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+ od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
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break;
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case PP_OD_RESTORE_DEFAULT_TABLE:
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--
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GitLab
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From 8bad128720ebc69e37f1c66767fb276088ef4fa7 Mon Sep 17 00:00:00 2001
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From: Evan Quan <evan.quan@amd.com>
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Date: Wed, 16 Aug 2023 14:51:19 +0800
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Subject: [PATCH] drm/amd/pm: fulfill the support for SMU13 `pp_dpm_dcefclk`
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interface
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Fulfill the incomplete SMU13 `pp_dpm_dcefclk` implementation.
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Reported-by: Guan Yu <guan.yu@amd.com>
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Signed-off-by: Evan Quan <evan.quan@amd.com>
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Acked-by: Alex Deucher <alexander.deucher@amd.com>
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---
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 27 +++++++++++++++++++
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 27 +++++++++++++++++++
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2 files changed, 54 insertions(+)
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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index bd0d5f027cac..5fdb2b3c042a 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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@@ -176,6 +176,7 @@ static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
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CLK_MAP(VCLK1, PPCLK_VCLK_1),
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CLK_MAP(DCLK, PPCLK_DCLK_0),
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CLK_MAP(DCLK1, PPCLK_DCLK_1),
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+ CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
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};
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static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
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@@ -707,6 +708,22 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
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pcie_table->num_of_link_levels++;
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}
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+ /* dcefclk dpm table setup */
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+ dpm_table = &dpm_context->dpm_tables.dcef_table;
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+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
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+ ret = smu_v13_0_set_single_dpm_table(smu,
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+ SMU_DCEFCLK,
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+ dpm_table);
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+ if (ret)
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+ return ret;
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+ } else {
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+ dpm_table->count = 1;
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+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
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+ dpm_table->dpm_levels[0].enabled = true;
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+ dpm_table->min = dpm_table->dpm_levels[0].value;
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+ dpm_table->max = dpm_table->dpm_levels[0].value;
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+ }
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+
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return 0;
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}
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@@ -794,6 +811,9 @@ static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
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case METRICS_CURR_FCLK:
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*value = metrics->CurrClock[PPCLK_FCLK];
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break;
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+ case METRICS_CURR_DCEFCLK:
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+ *value = metrics->CurrClock[PPCLK_DCFCLK];
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+ break;
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case METRICS_AVERAGE_GFXCLK:
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if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
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*value = metrics->AverageGfxclkFrequencyPostDs;
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@@ -1047,6 +1067,9 @@ static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
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case PPCLK_DCLK_1:
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member_type = METRICS_AVERAGE_DCLK1;
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break;
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+ case PPCLK_DCFCLK:
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+ member_type = METRICS_CURR_DCEFCLK;
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+ break;
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default:
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return -EINVAL;
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}
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@@ -1196,6 +1219,9 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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case SMU_DCLK1:
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single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
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break;
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+ case SMU_DCEFCLK:
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+ single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
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+ break;
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default:
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break;
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}
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@@ -1209,6 +1235,7 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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case SMU_VCLK1:
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case SMU_DCLK:
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case SMU_DCLK1:
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+ case SMU_DCEFCLK:
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ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
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if (ret) {
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dev_err(smu->adev->dev, "Failed to get current clock freq!");
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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index b9b3bf41eed3..12949928e285 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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@@ -147,6 +147,7 @@ static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
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CLK_MAP(VCLK1, PPCLK_VCLK_1),
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CLK_MAP(DCLK, PPCLK_DCLK_0),
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CLK_MAP(DCLK1, PPCLK_DCLK_1),
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+ CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
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};
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static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
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@@ -696,6 +697,22 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
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pcie_table->num_of_link_levels++;
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}
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+ /* dcefclk dpm table setup */
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+ dpm_table = &dpm_context->dpm_tables.dcef_table;
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+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
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+ ret = smu_v13_0_set_single_dpm_table(smu,
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+ SMU_DCEFCLK,
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+ dpm_table);
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+ if (ret)
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+ return ret;
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+ } else {
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+ dpm_table->count = 1;
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+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
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+ dpm_table->dpm_levels[0].enabled = true;
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+ dpm_table->min = dpm_table->dpm_levels[0].value;
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+ dpm_table->max = dpm_table->dpm_levels[0].value;
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+ }
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+
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return 0;
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}
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@@ -777,6 +794,9 @@ static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
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case METRICS_CURR_FCLK:
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*value = metrics->CurrClock[PPCLK_FCLK];
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break;
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+ case METRICS_CURR_DCEFCLK:
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+ *value = metrics->CurrClock[PPCLK_DCFCLK];
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+ break;
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case METRICS_AVERAGE_GFXCLK:
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*value = metrics->AverageGfxclkFrequencyPreDs;
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break;
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@@ -1027,6 +1047,9 @@ static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
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case PPCLK_DCLK_1:
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member_type = METRICS_CURR_DCLK1;
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break;
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+ case PPCLK_DCFCLK:
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+ member_type = METRICS_CURR_DCEFCLK;
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+ break;
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default:
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return -EINVAL;
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}
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@@ -1176,6 +1199,9 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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case SMU_DCLK1:
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single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
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break;
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+ case SMU_DCEFCLK:
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+ single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
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+ break;
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default:
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break;
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}
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@@ -1189,6 +1215,7 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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case SMU_VCLK1:
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case SMU_DCLK:
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case SMU_DCLK1:
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+ case SMU_DCEFCLK:
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ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
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if (ret) {
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dev_err(smu->adev->dev, "Failed to get current clock freq!");
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--
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GitLab
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From 3a2fb905145e76e4bbb32e90e0c6cd532dafb1b0 Mon Sep 17 00:00:00 2001
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From: Evan Quan <evan.quan@amd.com>
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Date: Mon, 14 Aug 2023 10:16:27 +0800
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Subject: [PATCH] Revert "drm/amd/pm: disable the SMU13 OD feature support
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temporarily"
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This reverts commit 3592cc20beeece83db4c50a0f400e2dd15139de9.
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The enablement for the new OD mechanism completed. Also, the support for
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fan control related OD feature has been added via this new mechanism.
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Thus, it is time to bring back the SMU13 OD support.
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Signed-off-by: Evan Quan <evan.quan@amd.com>
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Acked-by: Alex Deucher <alexander.deucher@amd.com>
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---
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 18 +++---------------
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 +++---------
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2 files changed, 6 insertions(+), 24 deletions(-)
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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index c48f81450d24..093962a37688 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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@@ -348,13 +348,10 @@ static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
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table_context->power_play_table;
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struct smu_baco_context *smu_baco = &smu->smu_baco;
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PPTable_t *pptable = smu->smu_table.driver_pptable;
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-#if 0
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- PPTable_t *pptable = smu->smu_table.driver_pptable;
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const OverDriveLimits_t * const overdrive_upperlimits =
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&pptable->SkuTable.OverDriveLimitsBasicMax;
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const OverDriveLimits_t * const overdrive_lowerlimits =
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&pptable->SkuTable.OverDriveLimitsMin;
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-#endif
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if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
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smu->dc_controlled_by_gpio = true;
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@@ -366,27 +363,18 @@ static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
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if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
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smu_baco->maco_support = true;
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- /*
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- * We are in the transition to a new OD mechanism.
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- * Disable the OD feature support for SMU13 temporarily.
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- * TODO: get this reverted when new OD mechanism online
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- */
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|
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-#if 0
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if (!overdrive_lowerlimits->FeatureCtrlMask ||
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|
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!overdrive_upperlimits->FeatureCtrlMask)
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smu->od_enabled = false;
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+ table_context->thermal_controller_type =
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|
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+ powerplay_table->thermal_controller_type;
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+
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|
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/*
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* Instead of having its own buffer space and get overdrive_table copied,
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* smu->od_settings just points to the actual overdrive_table
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*/
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smu->od_settings = &powerplay_table->overdrive_table;
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-#else
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- smu->od_enabled = false;
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-#endif
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-
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- table_context->thermal_controller_type =
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- powerplay_table->thermal_controller_type;
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smu->adev->pm.no_fan =
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!(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
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|
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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index 99bc449799a6..430ad1b05ba3 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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@@ -338,12 +338,10 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
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struct smu_baco_context *smu_baco = &smu->smu_baco;
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PPTable_t *smc_pptable = table_context->driver_pptable;
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|
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BoardTable_t *BoardTable = &smc_pptable->BoardTable;
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|
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-#if 0
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|
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const OverDriveLimits_t * const overdrive_upperlimits =
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|
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&smc_pptable->SkuTable.OverDriveLimitsBasicMax;
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|
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const OverDriveLimits_t * const overdrive_lowerlimits =
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|
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&smc_pptable->SkuTable.OverDriveLimitsMin;
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|
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-#endif
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|
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if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
|
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|
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smu->dc_controlled_by_gpio = true;
|
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|
|
@@ -355,22 +353,18 @@ static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
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|
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if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
|
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|
|
smu_baco->maco_support = true;
|
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|
|
-#if 0
|
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|
|
if (!overdrive_lowerlimits->FeatureCtrlMask ||
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|
|
!overdrive_upperlimits->FeatureCtrlMask)
|
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|
|
smu->od_enabled = false;
|
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|
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|
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|
|
+ table_context->thermal_controller_type =
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|
|
+ powerplay_table->thermal_controller_type;
|
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|
|
+
|
|
|
|
|
/*
|
|
|
|
|
* Instead of having its own buffer space and get overdrive_table copied,
|
|
|
|
|
* smu->od_settings just points to the actual overdrive_table
|
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|
|
|
*/
|
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|
|
smu->od_settings = &powerplay_table->overdrive_table;
|
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|
|
-#else
|
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|
|
- smu->od_enabled = false;
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|
|
-#endif
|
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|
|
-
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|
|
- table_context->thermal_controller_type =
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|
|
- powerplay_table->thermal_controller_type;
|
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|
|
return 0;
|
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|
|
}
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|
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--
|
|
|
|
|
GitLab
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|
|
From 072a8dc3b5260ba08ba2e66036c2c63abd77df52 Mon Sep 17 00:00:00 2001
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|
|
From: Lijo Lazar <lijo.lazar@amd.com>
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|
Date: Thu, 24 Aug 2023 17:25:51 +0530
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|
|
Subject: [PATCH] drm/amd/pm: Fix clock reporting for SMUv13.0.6
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On SMU v13.0.6, effective clocks are reported by FW which won't exactly
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match with DPM level. Report the current clock based on the values
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matching closest to the effective clock. Also, when deep sleep is
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applied to a clock, report it with a special level "S:" as in sample
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clock levels below
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S: 19Mhz *
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0: 615Mhz
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1: 800Mhz
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2: 888Mhz
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3: 1000Mhz
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Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
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Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
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Reviewed-by: Evan Quan <evan.quan@amd.com>
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---
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.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 159 +++++++-----------
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1 file changed, 62 insertions(+), 97 deletions(-)
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diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
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index c2308783053c..29e1cada7667 100644
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--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
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+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
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@@ -91,6 +91,8 @@
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
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#define LINK_SPEED_MAX 4
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+#define SMU_13_0_6_DSCLK_THRESHOLD 100
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+
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static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
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MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
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MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
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@@ -783,13 +785,61 @@ static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
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return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
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}
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+static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf,
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+ struct smu_13_0_dpm_table *single_dpm_table,
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+ uint32_t curr_clk, const char *clk_name)
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+{
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+ struct pp_clock_levels_with_latency clocks;
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+ int i, ret, size = 0, level = -1;
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+ uint32_t clk1, clk2;
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+
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+ ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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+ if (ret) {
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+ dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
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+ clk_name);
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+ return ret;
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+ }
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+
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+ if (!clocks.num_levels)
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+ return -EINVAL;
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+
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+ if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
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+ size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
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+ for (i = 0; i < clocks.num_levels; i++)
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+ size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
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+ clocks.data[i].clocks_in_khz /
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+ 1000);
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+
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+ } else {
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+ if ((clocks.num_levels == 1) ||
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+ (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
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+ level = 0;
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+ for (i = 0; i < clocks.num_levels; i++) {
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+ clk1 = clocks.data[i].clocks_in_khz / 1000;
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+
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+ if (i < (clocks.num_levels - 1))
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+ clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
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+
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+ if (curr_clk >= clk1 && curr_clk < clk2) {
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+ level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
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+ i :
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+ i + 1;
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+ }
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+
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+ size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
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+ clk1, (level == i) ? "*" : "");
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+ }
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+ }
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+
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+ return size;
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+}
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+
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static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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enum smu_clk_type type, char *buf)
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{
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- int i, now, size = 0;
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+ int now, size = 0;
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int ret = 0;
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struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
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- struct pp_clock_levels_with_latency clocks;
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struct smu_13_0_dpm_table *single_dpm_table;
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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struct smu_13_0_dpm_context *dpm_context = NULL;
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@@ -852,26 +902,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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}
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single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
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- ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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- if (ret) {
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- dev_err(smu->adev->dev,
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- "Attempt to get memory clk levels Failed!");
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- return ret;
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- }
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- for (i = 0; i < clocks.num_levels; i++)
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- size += sysfs_emit_at(
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- buf, size, "%d: %uMhz %s\n", i,
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- clocks.data[i].clocks_in_khz / 1000,
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- (clocks.num_levels == 1) ?
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- "*" :
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- (smu_v13_0_6_freqs_in_same_level(
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- clocks.data[i].clocks_in_khz /
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- 1000,
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- now) ?
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- "*" :
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- ""));
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- break;
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+ return smu_v13_0_6_print_clks(smu, buf, single_dpm_table, now,
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+ "mclk");
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case SMU_SOCCLK:
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ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
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@@ -883,26 +916,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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}
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single_dpm_table = &(dpm_context->dpm_tables.soc_table);
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- ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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- if (ret) {
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- dev_err(smu->adev->dev,
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- "Attempt to get socclk levels Failed!");
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- return ret;
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- }
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- for (i = 0; i < clocks.num_levels; i++)
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- size += sysfs_emit_at(
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- buf, size, "%d: %uMhz %s\n", i,
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- clocks.data[i].clocks_in_khz / 1000,
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- (clocks.num_levels == 1) ?
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- "*" :
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- (smu_v13_0_6_freqs_in_same_level(
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- clocks.data[i].clocks_in_khz /
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- 1000,
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- now) ?
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- "*" :
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- ""));
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- break;
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+ return smu_v13_0_6_print_clks(smu, buf, single_dpm_table, now,
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+ "socclk");
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case SMU_FCLK:
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ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
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@@ -914,26 +930,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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}
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single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
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- ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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- if (ret) {
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- dev_err(smu->adev->dev,
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- "Attempt to get fclk levels Failed!");
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- return ret;
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- }
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- for (i = 0; i < single_dpm_table->count; i++)
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- size += sysfs_emit_at(
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- buf, size, "%d: %uMhz %s\n", i,
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- single_dpm_table->dpm_levels[i].value,
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- (clocks.num_levels == 1) ?
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- "*" :
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- (smu_v13_0_6_freqs_in_same_level(
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- clocks.data[i].clocks_in_khz /
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- 1000,
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- now) ?
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- "*" :
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- ""));
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- break;
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+ return smu_v13_0_6_print_clks(smu, buf, single_dpm_table, now,
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+ "fclk");
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case SMU_VCLK:
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ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
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@@ -945,26 +944,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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}
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single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
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- ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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- if (ret) {
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- dev_err(smu->adev->dev,
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- "Attempt to get vclk levels Failed!");
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- return ret;
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- }
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- for (i = 0; i < single_dpm_table->count; i++)
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- size += sysfs_emit_at(
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- buf, size, "%d: %uMhz %s\n", i,
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- single_dpm_table->dpm_levels[i].value,
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- (clocks.num_levels == 1) ?
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- "*" :
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- (smu_v13_0_6_freqs_in_same_level(
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- clocks.data[i].clocks_in_khz /
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- 1000,
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- now) ?
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- "*" :
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- ""));
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- break;
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+ return smu_v13_0_6_print_clks(smu, buf, single_dpm_table, now,
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+ "vclk");
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case SMU_DCLK:
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ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
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@@ -976,26 +958,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
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}
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single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
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- ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
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- if (ret) {
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- dev_err(smu->adev->dev,
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- "Attempt to get dclk levels Failed!");
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- return ret;
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- }
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- for (i = 0; i < single_dpm_table->count; i++)
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- size += sysfs_emit_at(
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- buf, size, "%d: %uMhz %s\n", i,
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- single_dpm_table->dpm_levels[i].value,
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- (clocks.num_levels == 1) ?
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- "*" :
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- (smu_v13_0_6_freqs_in_same_level(
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- clocks.data[i].clocks_in_khz /
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- 1000,
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- now) ?
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- "*" :
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- ""));
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- break;
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+ return smu_v13_0_6_print_clks(smu, buf, single_dpm_table, now,
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+ "dclk");
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default:
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break;
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--
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GitLab
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