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soc/intel/tgl: Add PEG devices to IRQ constraints

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Fixes IRQ errors on oryp8 that cause conflicts with the PCH HDA device.

Change-Id: If0020d9bb6585f7b0fb2dabd3d8b2a3efdd86de2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-05-25 12:18:35 -06:00
committed by Jeremy Soller
parent 80fb39363b
commit 0278090e68
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/tigerlake/fsp_params.c
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@ -93,6 +93,14 @@ static void parse_devicetree(FSP_S_CONFIG *params)
* regardless of whether or not they are used by the mainboard. * regardless of whether or not they are used by the mainboard.
*/ */
static const struct slot_irq_constraints irq_constraints[] = { static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = SA_DEV_SLOT_PEG,
.fns = {
FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B),
FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C),
},
},
{ {
.slot = SA_DEV_SLOT_IGD, .slot = SA_DEV_SLOT_IGD,
.fns = { .fns = {