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skylake: honor pcie root port settings already in chip.h

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For some unkonwn reason the pcie root port settings weren't
being honored in the device tree. Fix that omission.

BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
     settings were being honored.

Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285027
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10987
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Aaron Durbin
2015-07-13 14:03:41 -05:00
committed by Patrick Georgi
parent 356cabbe35
commit 02b3243dd3
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/skylake/romstage/romstage.c
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@@ -90,6 +90,13 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
for (i = 0; i < PchSerialIoIndexMax; i++)
params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
memcpy(params->PcieRpEnable, config->PcieRpEnable,
sizeof(params->PcieRpEnable));
memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
sizeof(params->PcieRpClkReqSupport));
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
params->MmioSize = 0x800; /* 2GB in MB */
params->TsegSize = CONFIG_SMM_TSEG_SIZE;
params->IedSize = config->IedSize;