Add check_member macro to allow clean and easy struct offset checking

This patch adds a new static assertion macro that can be used to check
the offsets in structures that overlay register sets at compile time. It
uses the _Static_assert() declaration from the new ISO C11 standard,
which is supported (even without -std=c11) by GCC after version 4.6.
(There is supposedly also support in clang, although I haven't tried
it... let's deal with compiler issues when/if they turn up.)

I've added it to all structures for our current ARM SoCs for now, and I
think every new register overlay we add going forward should use them
(at least for the last member, but feel free to add more if you think
it's useful).

Change-Id: If32510e7049739ad05618d363a854dc372d64386
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179412
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6905
Tested-by: build bot (Jenkins)

src/soc/nvidia/tegra/dc.h

@@ -89,6 +89,7 @@ struct dc_cmd_reg {
 	u32 disp_win_header;		/* _CMD_DISPLAY_WINDOW_HEADER_0 */
 	u32 reg_act_ctrl;		/* _CMD_REG_ACT_CONTROL_0 */
 };
+check_member(dc_cmd_reg, reg_act_ctrl, 0x43 * 4);
 
 enum {
 	PIN_REG_COUNT		= 4,
@@ -137,6 +138,7 @@ struct dc_com_reg {
 	u32 gpio_debounce_cnt;		/* _COM_GPIO_DEBOUNCE_COUNTER_0 */
 	u32 crc_checksum_latched;	/* _COM_CRC_CHECKSUM_LATCHED_0 */
 };
+check_member(dc_com_reg, crc_checksum_latched, (0x329 - 0x300) * 4);
 
 enum dc_disp_h_pulse_pos {
 	H_PULSE0_POSITION_A,
@@ -272,6 +274,7 @@ struct dc_disp_reg {
 	u32 dac_crt_ctrl;		/* _DISP_DAC_CRT_CTRL_0 */
 	u32 disp_misc_ctrl;		/* _DISP_DISP_MISC_CONTROL_0 */
 };
+check_member(dc_disp_reg, disp_misc_ctrl, (0x4c1 - 0x400) * 4);
 
 enum dc_winc_filter_p {
 	WINC_FILTER_COUNT	= 0x10,
@@ -305,6 +308,7 @@ struct dc_winc_reg {
 	/* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
 	u32 v_filter_p[WINC_FILTER_COUNT];
 };
+check_member(dc_winc_reg, v_filter_p, (0x619 - 0x500) * 4);
 
 /* WIN A/B/C Register 0x700 ~ 0x714*/
 struct dc_win_reg {
@@ -331,6 +335,7 @@ struct dc_win_reg {
 	u32 blend_3win_xy;		/* _WIN_BLEND_3WIN_XY_0 */
 	u32 hp_fetch_ctrl;		/* _WIN_HP_FETCH_CONTROL_0 */
 };
+check_member(dc_win_reg, hp_fetch_ctrl, (0x714 - 0x700) * 4);
 
 /* WINBUF A/B/C Register 0x800 ~ 0x80a */
 struct dc_winbuf_reg {
@@ -347,6 +352,7 @@ struct dc_winbuf_reg {
 	u32 addr_v_offset_ns;		/* _WINBUF_ADDR_V_OFFSET_NS_0 */
 	u32 uflow_status;		/* _WINBUF_UFLOW_STATUS_0 */
 };
+check_member(dc_winbuf_reg, uflow_status, (0x80a - 0x800) * 4);
 
 /* Display Controller (DC_) regs */
 struct display_controller {
@@ -367,6 +373,7 @@ struct display_controller {
 
 	struct dc_winbuf_reg winbuf;	/* WINBUF A/B/C 0x800 ~ 0x80a */
 };
+check_member(display_controller, winbuf, 0x800 * 4);
 
 #define BIT(pos)	(1U << pos)
 

src/soc/nvidia/tegra/i2c.h

@@ -149,5 +149,6 @@ struct tegra_i2c_regs {
 	uint32_t bus_clear_status;
 	uint32_t spare;
 };
+check_member(tegra_i2c_regs, bus_clear_status, 0x88);
 
 #endif	/* __SOC_NVIDIA_TEGRA_I2C_H__ */

src/soc/nvidia/tegra/usb.h

@@ -44,6 +44,7 @@ struct utmip_ctlr {
 	u32 misc_sts;
 	u32 pmc_wakeup;
 };
+check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800);
 
 struct usb_ctlr {
 	u32 id;
@@ -108,6 +109,7 @@ struct usb_ctlr {
 	u32 _rsv14[207];
 	struct utmip_ctlr utmip;	/* 0x800 */
 };
+check_member(usb_ctlr, utmip, 0x800);
 
 enum usb_phy_type {		/* For use in lpm_ctrl[31:29] */
 	USB_PHY_UTMIP = 0,

src/soc/nvidia/tegra124/clk_rst.h

@@ -295,6 +295,7 @@ struct  __attribute__ ((__packed__)) clk_rst_ctlr {
 	u32 clk_src_emc_latency;	/* _CLK_SOURCE_EMC_LATENCY  0x640 */
 	u32 clk_src_soc_therm;		/* _CLK_SOURCE_SOC_THERM    0x644 */
 };
+check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
 
 #define TEGRA_DEV_L			0
 #define TEGRA_DEV_H			1

src/soc/nvidia/tegra124/dma.h

@@ -70,6 +70,7 @@ struct apb_dma {
 	u32 chan_wr_reg3;	/* 0x50 */
 	u32 channel_swid1;	/* 0x54 */
 } __attribute__((packed));
+check_member(apb_dma, channel_swid1, 0x54);
 
 /*
  * Naming in the doc included a superfluous _CHANNEL_n_ for
@@ -167,6 +168,7 @@ struct apb_dma_channel_regs {
 	u32 wcount;		/* 0x20 */
 	u32 word_transfer;	/* 0x24 */
 } __attribute__((packed));
+check_member(apb_dma_channel_regs, word_transfer, 0x24);
 
 struct apb_dma_channel {
 	const int num;

src/soc/nvidia/tegra124/flow.h

@@ -36,6 +36,7 @@ struct flow_ctlr {
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
 };
+check_member(flow_ctlr, ram_repair, 0x40);
 
 enum {
 	FLOW_MODE_SHIFT = 29,

src/soc/nvidia/tegra124/pmc.h

@@ -156,6 +156,7 @@ struct tegra_pmc_regs {
 	u32 secure_scratch8[24 - 8];
 	u32 scratch56[120 - 56];
 };
+check_member(tegra_pmc_regs, scratch56, 0x340);
 
 enum {
 	PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f,

src/soc/nvidia/tegra124/spi.h

@@ -39,6 +39,7 @@ struct tegra_spi_regs {
 	u32 rx_fifo;		/* 0x188: SPI_FIFO2 */
 	u32 spare_ctl;		/* 0x18c: SPI_SPARE_CTRL */
 } __attribute__((packed));
+check_member(tegra_spi_regs, spare_ctl, 0x18c);
 
 enum spi_xfer_mode {
 	XFER_MODE_NONE = 0,

src/soc/nvidia/tegra124/sysctr.h

@@ -50,5 +50,6 @@ struct sysctr_regs {
 	uint32_t counterid10;
 	uint32_t counterid11;
 };
+check_member(sysctr_regs, counterid11, 0xffc);
 
 #endif	/* __SOC_NVIDIA_TEGRA124_SYSCTR_H__ */