sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/emulation/qemu: Configure TSEG size

Browse Source 
Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage.
The remaining Qemu code can already handle the bigger TSEG region.

TEST: Increased TSEG to 8MiB.

Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph
2024-06-14 17:07:29 +02:00
committed by Felix Held
parent f40f5b6dd5
commit 0395b4b5f2
2 changed files with 22 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/qemu-x86/Kconfig
View File

@@ -31,6 +31,11 @@ config CPU_QEMU_X86_TSEG_SMM
endchoice
config SMM_TSEG_SIZE
hex
depends on SMM_TSEG
default 0x100000
config MAX_CPUS
int
default 32 if SMM_TSEG

17
src/mainboard/emulation/qemu-q35/romstage.c
View File

@@ -7,6 +7,8 @@
#include "q35.h"
#define TSEG_SZ_MASK (3 << 1)
void mainboard_romstage_entry(void)
{
i82801ix_early_init();
@@ -14,5 +16,20 @@ void mainboard_romstage_entry(void)
if (!CONFIG(BOOTBLOCK_CONSOLE))
mainboard_machine_check();
/* Configure requested TSEG size */
switch (CONFIG_SMM_TSEG_SIZE) {
case 1 * MiB:
pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 0 << 1);
break;
case 2 * MiB:
pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 1 << 1);
break;
case 8 * MiB:
pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 2 << 1);
break;
default:
printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE);
}
cbmem_recovery(0);
}