Wield battle axe at ARM port
This patch unfortunately incorporates a number of changes, all of which are making future ARM ports easier. - drop cruft that came in with u-boot - move serial console from mainboard Kconfig to Exynos Kconfig - factor out non-board specific wakeup code - move generic bootblock code from mainboard to Exynos - actually call arch_cpu_init() - remove dead code - fix up copyright messages - remove snow_ prefix from a lot of code to reduce the noise when creating a new mainboard based on that code. Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3640 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Stefan Reinauer
committed by
Stefan Reinauer
Stefan Reinauer
parent
6adef0847e
commit
043eb0e35f
@@ -61,23 +61,6 @@
|
||||
|
||||
|
||||
#include <arch/io.h>
|
||||
/* CPU detection macros */
|
||||
extern unsigned int s5p_cpu_id;
|
||||
|
||||
inline void s5p_set_cpu_id(void);
|
||||
|
||||
#define IS_SAMSUNG_TYPE(type, id) \
|
||||
static inline int cpu_is_##type(void) \
|
||||
{ \
|
||||
return s5p_cpu_id == id ? 1 : 0; \
|
||||
}
|
||||
|
||||
IS_SAMSUNG_TYPE(s5pc100, 0xc100)
|
||||
IS_SAMSUNG_TYPE(s5pc110, 0xc110)
|
||||
|
||||
int s5p_get_cpu_rev(void);
|
||||
//void s5p_set_cpu_id(void);
|
||||
int s5p_get_cpu_id(void);
|
||||
|
||||
#define DEVICE_NOT_AVAILABLE 0
|
||||
|
||||
@@ -132,9 +115,6 @@ enum boot_mode exynos_get_boot_device(void);
|
||||
*/
|
||||
int board_wakeup_permitted(void);
|
||||
|
||||
#define cpu_is_exynos4() (s5p_get_cpu_id() == 0xc210)
|
||||
#define cpu_is_exynos5() (s5p_get_cpu_id() == 0xc520)
|
||||
|
||||
/**
|
||||
* Init subsystems according to the reset status
|
||||
*
|
||||
@@ -142,4 +122,7 @@ int board_wakeup_permitted(void);
|
||||
*/
|
||||
int lowlevel_init_subsystems(void);
|
||||
|
||||
int arch_cpu_init(void);
|
||||
|
||||
|
||||
#endif /* _EXYNOS_COMMON_CPU_H */
|
||||
|
||||
@@ -20,13 +20,9 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <common.h>
|
||||
#if 0
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/dmc.h>
|
||||
#endif
|
||||
#include <arch/io.h>
|
||||
|
||||
#include <cpu/samsung/exynos5-common/clk.h>
|
||||
@@ -39,31 +35,10 @@
|
||||
/* FIXME(dhendrix): consolidate samsung ID code/#defines to a common location */
|
||||
#include <cpu/samsung/exynos5250/setup.h> /* cpu_info_init() prototype */
|
||||
|
||||
/*
|
||||
* The following CPU infos are initialized in lowlevel_init(). They should be
|
||||
* put in the .data section. Otherwise, a compile will put them in the .bss
|
||||
* section since they don't have initial values. The relocation code which
|
||||
* runs after lowlevel_init() will reset them to zero.
|
||||
*/
|
||||
unsigned int s5p_cpu_id __attribute__((section(".data")));
|
||||
unsigned int s5p_cpu_rev __attribute__((section(".data")));
|
||||
static unsigned int s5p_cpu_id;
|
||||
static unsigned int s5p_cpu_rev;
|
||||
|
||||
void cpu_info_init(void)
|
||||
{
|
||||
s5p_set_cpu_id();
|
||||
}
|
||||
|
||||
int s5p_get_cpu_id(void)
|
||||
{
|
||||
return s5p_cpu_id;
|
||||
}
|
||||
|
||||
int s5p_get_cpu_rev(void)
|
||||
{
|
||||
return s5p_cpu_rev;
|
||||
}
|
||||
|
||||
void s5p_set_cpu_id(void)
|
||||
static void s5p_set_cpu_id(void)
|
||||
{
|
||||
s5p_cpu_id = readl((void *)EXYNOS_PRO_ID);
|
||||
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
|
||||
@@ -80,49 +55,12 @@ void s5p_set_cpu_id(void)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char buf[32];
|
||||
|
||||
printf("CPU: S5P%X @ %sMHz\n",
|
||||
s5p_cpu_id, strmhz(buf, get_arm_clk()));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
void board_show_dram(ulong size)
|
||||
{
|
||||
enum ddr_mode mem_type;
|
||||
unsigned frequency_mhz;
|
||||
unsigned arm_freq;
|
||||
enum mem_manuf mem_manuf;
|
||||
char buf[32];
|
||||
int ret;
|
||||
|
||||
/* Get settings from the fdt */
|
||||
ret = clock_get_mem_selection(&mem_type, &frequency_mhz,
|
||||
&arm_freq, &mem_manuf);
|
||||
if (ret)
|
||||
panic("Invalid DRAM information");
|
||||
|
||||
puts("DRAM: ");
|
||||
print_size(size, " ");
|
||||
printf("%s %s @ %sMHz",
|
||||
clock_get_mem_manuf_name(mem_manuf),
|
||||
clock_get_mem_type_name(mem_type),
|
||||
strmhz(buf, frequency_mhz));
|
||||
putc('\n');
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_CPU_INIT
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
cpu_info_init();
|
||||
s5p_set_cpu_id();
|
||||
|
||||
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
|
||||
s5p_cpu_id, get_arm_clk() / (1024*1024));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -22,175 +22,24 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
|
||||
|
||||
#ifndef __EXYNOS5_CONFIG_H
|
||||
#define __EXYNOS5_CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* S5P Family */
|
||||
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
|
||||
#define BUILD_PART_FS_STUFF 1 /* Disk Partition Support */
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT /* Used to check cpu type */
|
||||
|
||||
#include <cpu/samsung/exynos5250/cpu.h> /* get chip and board defs */
|
||||
|
||||
/* Align LCD to 1MB boundary */
|
||||
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_CMD_SHA256
|
||||
//#define CONFIG_EXYNOS_ACE_SHA
|
||||
/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
|
||||
|
||||
//#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
//#define CONFIG_SYS_TEXT_BASE 0x43e00000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Power Down Modes */
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
#define S5P_CHECK_DIDLE 0xBAD00000
|
||||
#define S5P_CHECK_LPA 0xABAD0000
|
||||
|
||||
/* Offset for inform registers */
|
||||
#define INFORM0_OFFSET 0x800
|
||||
#define INFORM1_OFFSET 0x804
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
//#define CONFIG_BAUDRATE 115200
|
||||
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* PWM */
|
||||
#define CONFIG_PWM
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
|
||||
/* Number of GPIOS to use for board revision detection */
|
||||
#define CONFIG_BOARD_REV_GPIO_COUNT 2
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* valid baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/* Stack sizes */
|
||||
#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
/* Enable SPI H/W Controller Driver support */
|
||||
#define CONFIG_EXYNOS_SPI
|
||||
|
||||
/* FIXME(dhendrix): We should be concerned with SPI flash parts here... */
|
||||
#if 0
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
/* Enable Gigadevice SPI flash support for Snow board */
|
||||
#define CONFIG_SPI_FLASH_GIGADEVICE
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
/* Set speed for SPI flash */
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_SECURE_BL1_ONLY
|
||||
|
||||
/* Secure FW size configuration */
|
||||
#ifdef CONFIG_SECURE_BL1_ONLY
|
||||
#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
|
||||
#else
|
||||
#define CONFIG_SEC_FW_SIZE 0
|
||||
#endif
|
||||
|
||||
/* Configuration of BL1, BL2, ENV Blocks on mmc */
|
||||
#define CONFIG_RES_BLOCK_SIZE (512)
|
||||
#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
|
||||
#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
|
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
|
||||
|
||||
#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
|
||||
#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
|
||||
|
||||
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE + \
|
||||
CONFIG_BL2_SIZE)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SPI_BUS 1
|
||||
#else /* CONFIG_ENV_IS_IN_MMC */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
|
||||
#endif
|
||||
|
||||
/* U-boot copy size from boot Media to DRAM.*/
|
||||
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
|
||||
|
||||
/* Set the emmc bus width to 8 */
|
||||
#define CONFIG_MSHCI_BUS_WIDTH 8
|
||||
#define CONFIG_MSHCI_PERIPH_ID PERIPH_ID_SDMMC0
|
||||
|
||||
#if BUILD_PART_FS_STUFF
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#endif
|
||||
|
||||
/* Enable devicetree support */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
|
||||
/* We spend about 100us getting from reset to SPL */
|
||||
#define CONFIG_SPL_TIME_US 100000
|
||||
|
||||
/* Stringify a token */
|
||||
#ifndef STRINGIFY
|
||||
#define _STRINGIFY(x) #x
|
||||
#define STRINGIFY(x) _STRINGIFY(x)
|
||||
#endif
|
||||
|
||||
#endif /* __EXYNOS5_CONFIG_H */
|
||||
|
||||
@@ -97,3 +97,41 @@ config SYS_TEXT_BASE
|
||||
config COREBOOT_TABLES_SIZE
|
||||
hex
|
||||
default 0x4000000
|
||||
|
||||
choice CONSOLE_SERIAL_UART_CHOICES
|
||||
prompt "Serial Console UART"
|
||||
default CONSOLE_SERIAL_UART3
|
||||
depends on CONSOLE_SERIAL_UART
|
||||
|
||||
config CONSOLE_SERIAL_UART0
|
||||
bool "UART0"
|
||||
help
|
||||
Serial console on UART0
|
||||
|
||||
config CONSOLE_SERIAL_UART1
|
||||
bool "UART1"
|
||||
help
|
||||
Serial console on UART1
|
||||
|
||||
config CONSOLE_SERIAL_UART2
|
||||
bool "UART2"
|
||||
help
|
||||
Serial console on UART2
|
||||
|
||||
config CONSOLE_SERIAL_UART3
|
||||
bool "UART3"
|
||||
help
|
||||
Serial console on UART3
|
||||
|
||||
endchoice
|
||||
|
||||
config CONSOLE_SERIAL_UART_ADDRESS
|
||||
hex
|
||||
depends on CONSOLE_SERIAL_UART
|
||||
default 0x12c00000 if CONSOLE_SERIAL_UART0
|
||||
default 0x12c10000 if CONSOLE_SERIAL_UART1
|
||||
default 0x12c20000 if CONSOLE_SERIAL_UART2
|
||||
default 0x12c30000 if CONSOLE_SERIAL_UART3
|
||||
help
|
||||
Map the UART names to the respective MMIO address.
|
||||
|
||||
|
||||
@@ -10,6 +10,7 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c
|
||||
bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c
|
||||
bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c
|
||||
bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
|
||||
bootblock-y += wakeup.c
|
||||
|
||||
romstage-y += clock.c
|
||||
romstage-y += clock_init.c
|
||||
@@ -21,6 +22,7 @@ romstage-y += mct.c
|
||||
romstage-y += monotonic_timer.c
|
||||
romstage-$(CONFIG_EARLY_CONSOLE) += soc.c
|
||||
romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
|
||||
romstage-y += wakeup.c
|
||||
|
||||
#ramstage-y += tzpc_init.c
|
||||
ramstage-y += clock.c
|
||||
|
||||
@@ -17,7 +17,27 @@
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include "clk.h"
|
||||
#include "wakeup.h"
|
||||
|
||||
void bootblock_cpu_init(void);
|
||||
void bootblock_cpu_init(void)
|
||||
{
|
||||
/* kick off the multi-core timer.
|
||||
* We want to do this as early as we can.
|
||||
*/
|
||||
mct_start();
|
||||
|
||||
if (get_wakeup_state() == WAKEUP_DIRECT) {
|
||||
wakeup();
|
||||
/* Never returns. */
|
||||
}
|
||||
|
||||
/* For most ARM systems, we have to initialize firmware media source
|
||||
* (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
|
||||
* already handled by iROM so there's no need to setup again.
|
||||
*/
|
||||
|
||||
console_init();
|
||||
}
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <arch/cache.h>
|
||||
#include <cpu/samsung/exynos5250/fimd.h>
|
||||
#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
|
||||
#include <cpu/samsung/exynos5-common/cpu.h>
|
||||
#include "chip.h"
|
||||
#include "cpu.h"
|
||||
|
||||
@@ -97,6 +98,8 @@ static void cpu_init(device_t dev)
|
||||
{
|
||||
exynos_displayport_init(dev);
|
||||
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
|
||||
|
||||
arch_cpu_init();
|
||||
}
|
||||
|
||||
static void cpu_noop(device_t dev)
|
||||
|
||||
52
src/cpu/samsung/exynos5250/wakeup.c
Normal file
52
src/cpu/samsung/exynos5250/wakeup.c
Normal file
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/samsung/exynos5250/power.h>
|
||||
#include <cpu/samsung/exynos5-common/exynos5-common.h>
|
||||
|
||||
#include "wakeup.h"
|
||||
|
||||
void wakeup(void)
|
||||
{
|
||||
if (wakeup_need_reset())
|
||||
power_reset();
|
||||
|
||||
power_init(); /* Ensure ps_hold_setup() for early wakeup. */
|
||||
power_exit_wakeup();
|
||||
/* Should never return. */
|
||||
die("Failed to wake up.\n");
|
||||
}
|
||||
|
||||
int get_wakeup_state(void)
|
||||
{
|
||||
uint32_t status = power_read_reset_status();
|
||||
|
||||
/* DIDLE/LPA can be resumed without clock reset (ex, bootblock),
|
||||
* and SLEEP requires resetting clock (should be done in ROM stage).
|
||||
*/
|
||||
|
||||
if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA)
|
||||
return WAKEUP_DIRECT;
|
||||
|
||||
if (status == S5P_CHECK_SLEEP)
|
||||
return WAKEUP_NEED_CLOCK_RESET;
|
||||
|
||||
return IS_NOT_WAKEUP;
|
||||
}
|
||||
37
src/cpu/samsung/exynos5250/wakeup.h
Normal file
37
src/cpu/samsung/exynos5250/wakeup.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef WAKEUP_H
|
||||
#define WAKEUP_H
|
||||
|
||||
enum {
|
||||
// A normal boot (not suspend/resume)
|
||||
IS_NOT_WAKEUP,
|
||||
// A wake up event that can be resumed any time
|
||||
WAKEUP_DIRECT,
|
||||
// A wake up event that must be resumed only after
|
||||
// clock and memory controllers are re-initialized
|
||||
WAKEUP_NEED_CLOCK_RESET,
|
||||
};
|
||||
|
||||
int wakeup_need_reset(void);
|
||||
int get_wakeup_state(void);
|
||||
void wakeup(void);
|
||||
|
||||
#endif /* WAKEUP_H */
|
||||
Reference in New Issue
Block a user