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mb/google/brox/var/lotso: Update DTT settings for thermal control

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update DTT settings for thermal control,according to b:348285763#comment6.

BUG=b:348285763
TEST=emerge-brox coreboot

Change-Id: I67e16a2596884d501273a5787119406dff7a20f9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83304
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kun Liu 2024-07-02 17:47:46 +08:00 committed by Subrata Banik
parent 85cb9f7648
commit 048bffc365
1 changed files with 46 additions and 21 deletions
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67
src/mainboard/google/brox/variants/lotso/overridetree.cb
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@ -80,49 +80,74 @@ chip soc/intel/alderlake
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DRAM_SOC""
register "options.tsr[1].desc" = ""Fan-Inlet""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""5V""
# TODO: below values are initial reference values only
## Active Policy
register "policies.active" = "{
[0] = {
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(54, 64),
TEMP_PCT(52, 52),
TEMP_PCT(50, 44),
TEMP_PCT(48, 38),
TEMP_PCT(45, 34),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(85, 90),
TEMP_PCT(80, 80),
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(55, 50),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(90, 90),
TEMP_PCT(85, 80),
TEMP_PCT(75, 70),
TEMP_PCT(70, 60),
TEMP_PCT(70, 50),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(80, 90),
TEMP_PCT(75, 80),
TEMP_PCT(70, 70),
TEMP_PCT(65, 50),
TEMP_PCT(60, 40),
}
}
}"
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 97, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 80, 5000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 15000,
.min_power = 12000,
.max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 55000,
.max_power = 55000,
.min_power = 25000,
.max_power = 25000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
@ -139,15 +164,15 @@ chip soc/intel/alderlake
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[0] = { 90, 4734, 220, 1640, },
[1] = { 80, 4443, 180, 1310, },
[2] = { 70, 4108, 145, 1030, },
[3] = { 60, 3752, 115, 765, },
[4] = { 50, 3352, 90, 545, },
[5] = { 40, 2897, 55, 365, },
[6] = { 30, 2363, 30, 220, },
[7] = { 20, 1752, 15, 120, },
[8] = { 10, 918, 10, 60, },
[9] = { 0, 0, 0, 50, }
}"