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soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD

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Replace the two obsolete LPID implementations with the new PEPD device.

The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)

There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.

Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
2020-10-15 18:09:28 +02:00
committed by Nico Huber
parent e593747f06
commit 05c732b9e4
12 changed files with 10 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/deltaur/dsdt.asl
View File

@ -35,9 +35,6 @@ DefinitionBlock(
/* VPD support */
#include <vendorcode/google/chromeos/acpi/vpd.asl>
/* Low power idle table */
#include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{

3
src/mainboard/google/drallion/dsdt.asl
View File

@ -39,9 +39,6 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{

3
src/mainboard/google/hatch/dsdt.asl
View File

@ -36,9 +36,6 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{

3
src/mainboard/google/sarien/dsdt.asl
View File

@ -39,9 +39,6 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/common/acpi/lpit.asl>
#if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)

4
src/mainboard/google/volteer/dsdt.asl
View File

@ -38,10 +38,6 @@ DefinitionBlock(
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Include Low power idle table for a short term workaround to enable
S0ix. Once cr50 pulse width is fixed, this can be removed. */
#include <soc/intel/common/acpi/lpit.asl>
// Chrome OS Embedded Controller
Scope (\_SB.PCI0.LPCB)
{

4
src/soc/intel/alderlake/acpi/southbridge.asl
View File

@ -44,8 +44,8 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* PMC Core*/
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>

4
src/soc/intel/cannonlake/acpi/southbridge.asl
View File

@ -46,5 +46,5 @@
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
/* PMC Core */
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>

103
src/soc/intel/common/acpi/lpit.asl
View File

@ -1,103 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0
#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1
#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2
#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3
#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4
#define LPID_DSM_ARG2_S0IX_ENTRY 5
#define LPID_DSM_ARG2_S0IX_EXIT 6
External(\_SB.MS0X, MethodObj)
External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
External(\_SB.PCI0.EGPM, MethodObj)
External(\_SB.PCI0.RGPM, MethodObj)
Scope(\_SB)
{
Device(LPID)
{
Name(_ADR, 0x00000000)
Name(_CID, EISAID("PNP0D80"))
Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
Method(_DSM, 4)
{
If(Arg0 == ^UUID) {
/*
* Enum functions
*/
If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) {
Return(Buffer(One) {0x60})
}
/*
* Function 1 - Get Device Constraints
*/
If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) {
Return(Package(5) {0, Ones, Ones, Ones, Ones})
}
/*
* Function 2 - Get Crash Dump Device
*/
If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) {
Return(Buffer(One) {0x0})
}
/*
* Function 3 - Display Off Notification
*/
If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) {
}
/*
* Function 4 - Display On Notification
*/
If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) {
}
/*
* Function 5 - Low Power S0 Entry Notification
*/
If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) {
/* Inform the EC */
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
\_SB.PCI0.LPCB.EC0.S0IX(1)
}
/* provide board level S0ix hook */
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(1)
}
/*
* Save the current PM bits then
* enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
}
}
/*
* Function 6 - Low Power S0 Exit Notification
*/
If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) {
/* Inform the EC */
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
\_SB.PCI0.LPCB.EC0.S0IX(0)
}
/* provide board level S0ix hook */
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(0)
}
/* Restore GPIO all Community PM */
If (CondRefOf (\_SB.PCI0.RGPM))
{
\_SB.PCI0.RGPM ()
}
}
}
Return(Buffer(One) {0x00})
} // Method(_DSM)
} // Device (LPID)
} // End Scope(\_SB)

8
src/soc/intel/common/block/acpi/acpi/pmc.asl
View File

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Device (PEPD)
{
Name (_HID, "INT33A1" /* Intel Power Engine */)
Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */)
Name (_UID, One)
}

4
src/soc/intel/elkhartlake/acpi/southbridge.asl
View File

@ -41,8 +41,8 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* PMC Core*/
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* EMMC/SD card */
#include "scs.asl"

4
src/soc/intel/jasperlake/acpi/southbridge.asl
View File

@ -47,8 +47,8 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* PMC Core*/
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* EMMC/SD card */
#include "scs.asl"

4
src/soc/intel/tigerlake/acpi/southbridge.asl
View File

@ -44,8 +44,8 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* PMC Core*/
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>