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ec/google/chromec: Expand EC share memory for DTTS

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DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
EricKY Cheng 2022-10-03 16:24:04 +08:00 committed by Raul Rangel
parent 7b73e85283
commit 065c5870e4
1 changed files with 1 additions and 0 deletions
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src/ec/google/chromeec/acpi/ec.asl
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@ -56,6 +56,7 @@ Device (EC0)
CHGL, 8, // Charger Current Limit
TBMD, 1, // Tablet mode
DDPN, 3, // Device DPTF Profile Number
STTB, 1, // Switch thermal table by body detection status
// DFUD must be 0 for the other 31 values to be valid
Offset (0x0a),
DFUD, 1, // Device Features Undefined