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mb/system76/rpl: gaze18-3050: Add USB and PCIe RP configs

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Change-Id: Ic9863d3aa8129e7081f36bc302cfa8ca68140eae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-21 08:15:15 -07:00
parent 6529e3d712
commit 0689097632
1 changed files with 61 additions and 2 deletions
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63
src/mainboard/system76/rpl/variants/gaze18-3050/overridetree.cb
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@@ -2,10 +2,69 @@ chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x5630 inherit
device ref pcie5_0 off
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.1 Gen2)
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A (USB 3.1 Gen2)
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (USB 3.1 Gen2)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Finger
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A (USB 3.1 Gen2)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
end
device ref pcie4_0 off
device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 3 (GPU)
register "pch_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie4_0 on
# PCIE PEG0 x4, Clock 0 (SSD0)
register "pch_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp5 on
# PCH RP#5 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp9 on
# PCH RP#9 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp10 on
# PCH RP#10 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp11 on
# PCH RP#11 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end