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This patch unifies the use of config options in v2 to all start with CONFIG_

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It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

90
documentation/LinuxBIOS-AMD64.tex
View File

@ -286,7 +286,7 @@ the build target configuration file
All local configuration variables have to be declared before they can be All local configuration variables have to be declared before they can be
used. Example: used. Example:
\begin{verbatim} \begin{verbatim}
uses ROM_IMAGE_SIZE uses CONFIG_ROM_IMAGE_SIZE
\end{verbatim} \end{verbatim}
\textbf{NOTE:} Only configuration variables known to the configuration \textbf{NOTE:} Only configuration variables known to the configuration
@ -303,20 +303,20 @@ configuration files.
Example: Example:
\begin{verbatim} \begin{verbatim}
default ROM_IMAGE_SIZE=0x10000 default CONFIG_ROM_IMAGE_SIZE=0x10000
\end{verbatim} \end{verbatim}
It is also possible to assign the value of one configuration variable to It is also possible to assign the value of one configuration variable to
another one, i.e.: another one, i.e.:
\begin{verbatim} \begin{verbatim}
default FALLBACK_SIZE=ROM_SIZE default CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
\end{verbatim} \end{verbatim}
Also, simple expressions are allowed: Also, simple expressions are allowed:
\begin{verbatim} \begin{verbatim}
default FALLBACK_SIZE=(ROM_SIZE - NORMAL_SIZE) default CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE - NORMAL_SIZE)
\end{verbatim} \end{verbatim}
If an option contains a string, this string has to be protected with If an option contains a string, this string has to be protected with
@ -365,8 +365,8 @@ path to a static elf binary (i.e Linux kernel or etherboot)
\begin{verbatim} \begin{verbatim}
romimage "normal" romimage "normal"
option USE_FALLBACK_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000 option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Normal" option COREBOOT_EXTRA_VERSION=".0Normal"
mainboard amd/solo mainboard amd/solo
payload /suse/stepan/tg3ide_ payload /suse/stepan/tg3ide_
@ -382,7 +382,7 @@ together to the final coreboot image. It also specifies the order of
the images and the final image size: the images and the final image size:
\begin{verbatim} \begin{verbatim}
buildrom ./solo.rom ROM_SIZE "normal" "fallback" buildrom ./solo.rom CONFIG_ROM_SIZE "normal" "fallback"
\end{verbatim} \end{verbatim}
\end{itemize} \end{itemize}
@ -408,12 +408,12 @@ machine.
Use new \textit{chip\_configure} method for configuring (nonpci) Use new \textit{chip\_configure} method for configuring (nonpci)
devices. Set to \texttt{1} for all AMD64 mainboards. devices. Set to \texttt{1} for all AMD64 mainboards.
\item \begin{verbatim}MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} \item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim}
Errors or log messages up to this level can be printed. Default is Errors or log messages up to this level can be printed. Default is
\texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}. \texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}.
\item \begin{verbatim}DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} \item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim}
Console will log at this level unless changed. Default is \texttt{7}, Console will log at this level unless changed. Default is \texttt{7},
minimum is \texttt{0}, maximum is \texttt{10}. minimum is \texttt{0}, maximum is \texttt{10}.
@ -424,16 +424,16 @@ Log messages to 8250 uart based serial console. Default is \texttt{0}
(don't log to serial console). This value should be set to \texttt{1} (don't log to serial console). This value should be set to \texttt{1}
for all AMD64 builds. for all AMD64 builds.
\item \begin{verbatim}ROM_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_ROM_SIZE\end{verbatim}
Size of final ROM image. This option has no default value. Size of final ROM image. This option has no default value.
\item \begin{verbatim}FALLBACK_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_FALLBACK_SIZE\end{verbatim}
Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:} Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:}
This does not include the fallback payload. This does not include the fallback payload.
\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if
your mainboard has CMOS memory and you want to use it to store your mainboard has CMOS memory and you want to use it to store
@ -444,7 +444,7 @@ coreboot parameters (Loglevel, serial line speed, ...)
Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which
will boot from an IDE disk) will boot from an IDE disk)
\item \begin{verbatim}HAVE_FALLBACK_BOOT\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_FALLBACK_BOOT\end{verbatim}
Set to \texttt{1} if fallback booting is required. Defaults to Set to \texttt{1} if fallback booting is required. Defaults to
\texttt{0}. \texttt{0}.
@ -456,11 +456,11 @@ The following options should be used within a romimage section:
\begin{itemize} \begin{itemize}
\item \begin{verbatim}USE_FALLBACK_IMAGE\end{verbatim} \item \begin{verbatim}CONFIG_USE_FALLBACK_IMAGE\end{verbatim}
Set to \texttt{1} to build a fallback image. Defaults to \texttt{0} Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
\item \begin{verbatim}ROM_IMAGE_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim}
Default image size. Defaults to \texttt{65535} bytes. Default image size. Defaults to \texttt{65535} bytes.
@ -544,14 +544,14 @@ do:
\begin{verbatim} \begin{verbatim}
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
$(MAINBOARD)/auto.c -o $@" $(CONFIG_MAINBOARD)/auto.c -o $@"
end end
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
$(MAINBOARD)/auto.c -o $@" $(CONFIG_MAINBOARD)/auto.c -o $@"
end end
\end{verbatim} \end{verbatim}
@ -747,26 +747,26 @@ They should be set using the \texttt{default} keyword:
\begin{itemize} \begin{itemize}
\item \begin{verbatim}HAVE_HARD_RESET\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_HARD_RESET\end{verbatim}
If set to \texttt{1}, this option defines that there is a hard reset If set to \texttt{1}, this option defines that there is a hard reset
function for this mainboard. This option is not defined per default. function for this mainboard. This option is not defined per default.
\item \begin{verbatim}HAVE_PIRQ_TABLE\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_PIRQ_TABLE\end{verbatim}
If set to \texttt{1}, this option defines that there is an IRQ Table for If set to \texttt{1}, this option defines that there is an IRQ Table for
this mainboard. This option is not defined per default. this mainboard. This option is not defined per default.
\item \begin{verbatim}IRQ_SLOT_COUNT\end{verbatim} \item \begin{verbatim}CONFIG_IRQ_SLOT_COUNT\end{verbatim}
Number of IRQ slots. This option is not defined per default. Number of IRQ slots. This option is not defined per default.
\item \begin{verbatim}HAVE_MP_TABLE\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_MP_TABLE\end{verbatim}
Define this option to build an MP table (v1.4). The default is not to Define this option to build an MP table (v1.4). The default is not to
build an MP table. build an MP table.
\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim} \item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
Define this option to export a CMOS option table. The default is not to Define this option to export a CMOS option table. The default is not to
export a CMOS option table. export a CMOS option table.
@ -787,23 +787,23 @@ system. Defaults to \texttt{1}.
Set this option to \texttt{1} to enable IOAPIC support. This is Set this option to \texttt{1} to enable IOAPIC support. This is
mandatory if you want to boot a 64bit Linux kernel on an AMD64 system. mandatory if you want to boot a 64bit Linux kernel on an AMD64 system.
\item \begin{verbatim}STACK_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_STACK_SIZE\end{verbatim}
coreboot stack size. The size of the function call stack defaults to coreboot stack size. The size of the function call stack defaults to
\texttt{0x2000} (8k). \texttt{0x2000} (8k).
\item \begin{verbatim}HEAP_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_HEAP_SIZE\end{verbatim}
coreboot heap size. The heap is used when coreboot allocates memory coreboot heap size. The heap is used when coreboot allocates memory
with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards
generally set it to \texttt{0x4000} (16k) generally set it to \texttt{0x4000} (16k)
\item \begin{verbatim}XIP_ROM_BASE\end{verbatim} \item \begin{verbatim}CONFIG_XIP_ROM_BASE\end{verbatim}
Start address of area to cache during coreboot execution directly from Start address of area to cache during coreboot execution directly from
ROM. ROM.
\item \begin{verbatim}XIP_ROM_SIZE\end{verbatim} \item \begin{verbatim}CONFIG_XIP_ROM_SIZE\end{verbatim}
Size of area to cache during coreboot execution directly from ROM Size of area to cache during coreboot execution directly from ROM
@ -1075,8 +1075,8 @@ Mainboards that provide an IRQ table should have the following two
variables set in their \texttt{Config.lb} file: variables set in their \texttt{Config.lb} file:
\begin{verbatim} \begin{verbatim}
default HAVE_PIRQ_TABLE=1 default CONFIG_HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=7 default CONFIG_IRQ_SLOT_COUNT=7
\end{verbatim} \end{verbatim}
This will make coreboot look for the file \\ This will make coreboot look for the file \\
@ -1106,7 +1106,7 @@ mainboard specific configuration file
\begin{verbatim} \begin{verbatim}
default CONFIG_SMP=1 default CONFIG_SMP=1
default CONFIG_MAX_CPUS=1 # 2,4,.. default CONFIG_MAX_CPUS=1 # 2,4,..
default HAVE_MP_TABLE=1 default CONFIG_HAVE_MP_TABLE=1
\end{verbatim} \end{verbatim}
coreboot will then look for a function for setting up the MP table in coreboot will then look for a function for setting up the MP table in
@ -1136,9 +1136,9 @@ framework that can generate the following tables:
To enable ACPI in your coreboot build, add the following lines to your To enable ACPI in your coreboot build, add the following lines to your
configuration files: configuration files:
\begin{verbatim} \begin{verbatim}
uses HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_TABLES
[..] [..]
option HAVE_ACPI_TABLES=1 option CONFIG_HAVE_ACPI_TABLES=1
\end{verbatim} \end{verbatim}
To keep Linux doing it's pci ressource allocation based on IRQ tables and MP To keep Linux doing it's pci ressource allocation based on IRQ tables and MP
@ -1234,12 +1234,12 @@ When changing speed and width of hypertransport chain connections
coreboot has to either assert an LDTSTOP or a reset to make the changes coreboot has to either assert an LDTSTOP or a reset to make the changes
become active. Additionally Linux can do a firmware reset, if coreboot become active. Additionally Linux can do a firmware reset, if coreboot
provides the needed infrastructure. To use this capability, define the provides the needed infrastructure. To use this capability, define the
option \texttt{HAVE\_HARD\_RESET} and add an object file specifying the option \texttt{HAVE\_HARD\CONFIG_RESET} and add an object file specifying the
reset code in your mainboard specific configuration file reset code in your mainboard specific configuration file
\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}: \texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}:
\begin{verbatim} \begin{verbatim}
default HAVE_HARD_RESET=1 default CONFIG_HAVE_HARD_RESET=1
object reset.o object reset.o
\end{verbatim} \end{verbatim}
@ -1529,7 +1529,7 @@ was added for many AMD CPUs, which both simplified and complicated things. Simpl
There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them. There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them.
\begin{itemize} \begin{itemize}
\item \begin{verbatim}USE_DCACHE_RAM\end{verbatim} \item \begin{verbatim}CONFIG_USE_DCACHE_RAM\end{verbatim}
Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0} Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0}
@ -1552,7 +1552,7 @@ A coreboot rom file consists of one or more \textit{images}. All images consist
ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only
one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c. one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c.
\subsubsection{How it is built} \subsubsection{How it is built}
Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CRT0\_INCLUDES variable. crt0.s is then assembled. Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG_CRT0\_INCLUDES variable. crt0.s is then assembled.
File for the ram part are compiled in a conventional manner. File for the ram part are compiled in a conventional manner.
@ -1575,8 +1575,8 @@ As we mentioned, the ROM file consists of multiple images. In the basic file, th
\begin{itemize} \begin{itemize}
\item PAYLOAD\_SIZE. Each image may have a different payload size. \item PAYLOAD\_SIZE. Each image may have a different payload size.
\item \_ROMBASE Each image must have a different base in rom. \item \CONFIG_ROMBASE Each image must have a different base in rom.
\item \_RESET Unclear what this is used for. \item \CONFIG_RESET Unclear what this is used for.
\item \_EXCEPTION\_VECTORS where an optional IDT might go. \item \_EXCEPTION\_VECTORS where an optional IDT might go.
\item USE\_OPTION\_TABLE if set, an option table section will be linked in. \item USE\_OPTION\_TABLE if set, an option table section will be linked in.
\item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this. \item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this.
@ -1608,7 +1608,7 @@ If fallback has been built in, some setup needs to be done. On some machines, it
); );
fallback_image: fallback_image:
#if HAVE_FAILOVER_BOOT==1 #if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image" __asm__ volatile ("jmp __fallback_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@ -1619,7 +1619,7 @@ If fallback has been built in, some setup needs to be done. On some machines, it
How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other. How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other.
Finally, we can see this in the Config.lb for most mainboards: Finally, we can see this in the Config.lb for most mainboards:
\begin{verbatim} \begin{verbatim}
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds ldscript /cpu/x86/16bit/reset16.lds
else else
@ -1771,10 +1771,10 @@ Confusingly enough, almost all the uses of these two variables are either nested
The fallback and normal builds are the same. The target config has a new clause that looks like this: The fallback and normal builds are the same. The target config has a new clause that looks like this:
\begin{verbatim} \begin{verbatim}
romimage "failover" romimage "failover"
option USE_FAILOVER_IMAGE=1 option CONFIG_USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover" option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover"
end end
\end{verbatim} \end{verbatim}

40
documentation/RFC/config.tex
View File

@ -173,7 +173,7 @@ A sample file:
target x target x
# over-ride the default rom size in the mainboard file # over-ride the default rom size in the mainboard file
option ROM_SIZE=1024*1024 option CONFIG_ROM_SIZE=1024*1024
mainboard amd/solo mainboard amd/solo
end end
@ -188,8 +188,8 @@ Sample mainboard file
arch i386 end arch i386 end
cpu k8 end cpu k8 end
# #
option DEBUG=1 option CONFIG_DEBUG=1
default USE_FALLBACK_IMAGE=1 default CONFIG_USE_FALLBACK_IMAGE=1
option A=(1+2) option A=(1+2)
option B=0xa option B=0xa
# #
@ -204,7 +204,7 @@ ldscript cpu/i386/entry32.lds
### ###
### Build our reset vector (This is where linuxBIOS is entered) ### Build our reset vector (This is where linuxBIOS is entered)
### ###
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds ldscript cpu/i386/reset16.lds
else else
@ -214,15 +214,15 @@ end
. .
. .
. .
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
# #
### ###
### Romcc output ### Romcc output
### ###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" #makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit ./failover.inc #mainboardinit ./failover.inc
makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
mainboardinit ./auto.inc mainboardinit ./auto.inc
# #
@ -250,8 +250,8 @@ cpu k8 end
##object mainboard.o ##object mainboard.o
driver mainboard.o driver mainboard.o
object static_devices.o object static_devices.o
if HAVE_MP_TABLE object mptable.o end if CONFIG_HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
### Location of the DIMM EEPROMS on the SMBUS ### Location of the DIMM EEPROMS on the SMBUS
### This is fixed into a narrow range by the DIMM package standard. ### This is fixed into a narrow range by the DIMM package standard.
### ###
@ -261,8 +261,8 @@ option SMBUS_MEM_DEVICE_INC=1
# #
### The linuxBIOS bootloader. ### The linuxBIOS bootloader.
### ###
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
# #
\end{verbatim} \end{verbatim}
@ -272,17 +272,17 @@ handle. Makefile.settings looks like this, for example:
\begin{verbatim} \begin{verbatim}
TOP:=/home/rminnich/src/yapps2/freebios2 TOP:=/home/rminnich/src/yapps2/freebios2
TARGET_DIR:=x TARGET_DIR:=x
export MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
export ARCH:=i386 export CONFIG_ARCH:=i386
export _RAMBASE:=0x4000 export CONFIG_RAMBASE:=0x4000
export ROM_IMAGE_SIZE:=65535 export CONFIG_ROM_IMAGE_SIZE:=65535
export PAYLOAD_SIZE:=131073 export CONFIG_PAYLOAD_SIZE:=131073
export CONFIG_MAX_CPUS:=1 export CONFIG_MAX_CPUS:=1
export HEAP_SIZE:=8192 export CONFIG_HEAP_SIZE:=8192
export STACK_SIZE:=8192 export CONFIG_STACK_SIZE:=8192
export MEMORY_HOLE:=0 export CONFIG_MEMORY_HOLE:=0
export COREBOOT_VERSION:=1.1.0 export COREBOOT_VERSION:=1.1.0
export CC:=$(CROSS_COMPILE)gcc export CC:=$(CONFIG_CROSS_COMPILE)gcc
\end{verbatim} \end{verbatim}

28
src/arch/i386/Config.lb
View File

@ -2,14 +2,14 @@ uses CONFIG_CBFS
uses CONFIG_SMP uses CONFIG_SMP
uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_USE_INIT uses CONFIG_USE_INIT
uses HAVE_FAILOVER_BOOT uses CONFIG_HAVE_FAILOVER_BOOT
uses USE_FAILOVER_IMAGE uses CONFIG_USE_FAILOVER_IMAGE
uses USE_FALLBACK_IMAGE uses CONFIG_USE_FALLBACK_IMAGE
init init/crt0.S.lb init init/crt0.S.lb
if CONFIG_CBFS if CONFIG_CBFS
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
else else
initobject /src/lib/cbfs.o initobject /src/lib/cbfs.o
initobject /src/console/vsprintf.o initobject /src/console/vsprintf.o
@ -17,8 +17,8 @@ if CONFIG_CBFS
end end
end end
if HAVE_FAILOVER_BOOT if CONFIG_HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
ldscript init/ldscript_failover.lb ldscript init/ldscript_failover.lb
else else
if CONFIG_CBFS if CONFIG_CBFS
@ -29,13 +29,13 @@ if HAVE_FAILOVER_BOOT
end end
else else
if CONFIG_CBFS if CONFIG_CBFS
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
ldscript init/ldscript_fallback_cbfs.lb ldscript init/ldscript_fallback_cbfs.lb
else else
ldscript init/ldscript_cbfs.lb ldscript init/ldscript_cbfs.lb
end end
else else
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
ldscript init/ldscript_fallback.lb ldscript init/ldscript_fallback.lb
else else
ldscript init/ldscript.lb ldscript init/ldscript.lb
@ -54,7 +54,7 @@ end
makerule nrv2b makerule nrv2b
depends "$(TOP)/util/nrv2b/nrv2b.c" depends "$(TOP)/util/nrv2b/nrv2b.c"
action "$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@" action "$(CONFIG_HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
end end
makerule payload makerule payload
@ -91,7 +91,7 @@ if CONFIG_PRECOMPRESSED_PAYLOAD
makedefine PAYLOAD-1:=payload makedefine PAYLOAD-1:=payload
end end
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
makedefine COREBOOT_APC:= makedefine COREBOOT_APC:=
makedefine COREBOOT_RAM_ROM:= makedefine COREBOOT_RAM_ROM:=
@ -102,13 +102,13 @@ if USE_FAILOVER_IMAGE
else else
makerule coreboot.rom makerule coreboot.rom
depends "coreboot.strip buildrom $(PAYLOAD-1)" depends "coreboot.strip buildrom $(PAYLOAD-1)"
action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi" action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
end end
end end
makerule crt0.S makerule crt0.S
depends "$(CRT0)" depends "$(CONFIG_CRT0)"
action "cp $< $@" action "cp $< $@"
end end
@ -118,13 +118,13 @@ if CONFIG_USE_INIT
makerule init.o makerule init.o
depends "$(INIT-OBJECTS)" depends "$(INIT-OBJECTS)"
action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)" action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" action "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end end
makerule coreboot makerule coreboot
depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" action "$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end end
end end

12
src/arch/i386/boot/Config.lb
View File

@ -1,7 +1,7 @@
uses HAVE_PIRQ_TABLE uses CONFIG_HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_MULTIBOOT uses CONFIG_MULTIBOOT
uses HAVE_ACPI_RESUME uses CONFIG_HAVE_ACPI_RESUME
object boot.o object boot.o
object coreboot_table.o object coreboot_table.o
@ -9,13 +9,13 @@ if CONFIG_MULTIBOOT
object multiboot.o object multiboot.o
end end
object tables.o object tables.o
if HAVE_PIRQ_TABLE if CONFIG_HAVE_PIRQ_TABLE
object pirq_routing.o object pirq_routing.o
end end
if HAVE_ACPI_TABLES if CONFIG_HAVE_ACPI_TABLES
object acpi.o object acpi.o
object acpigen.o object acpigen.o
if HAVE_ACPI_RESUME if CONFIG_HAVE_ACPI_RESUME
object wakeup.S object wakeup.S
end end
end end

10
src/arch/i386/boot/acpi.c
View File

@ -390,18 +390,18 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt)
rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
} }
#if HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
void suspend_resume(void) void suspend_resume(void)
{ {
void *wake_vec; void *wake_vec;
#if 0 #if 0
#if MEM_TRAIN_SEQ != 0 #if CONFIG_MEM_TRAIN_SEQ != 0
#error "So far it works on AMD and MEM_TRAIN_SEQ == 0" #error "So far it works on AMD and CONFIG_MEM_TRAIN_SEQ == 0"
#endif #endif
#if _RAMBASE < 0x1F00000 #if CONFIG_RAMBASE < 0x1F00000
#error "For ACPI RESUME you need to have _RAMBASE at least 31MB" #error "For ACPI RESUME you need to have CONFIG_RAMBASE at least 31MB"
#error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
#error "And coreboot memory reserved in mainboard.c" #error "And coreboot memory reserved in mainboard.c"
#endif #endif

22
src/arch/i386/boot/coreboot_table.c
View File

@ -76,15 +76,15 @@ struct lb_memory *lb_memory(struct lb_header *header)
struct lb_serial *lb_serial(struct lb_header *header) struct lb_serial *lb_serial(struct lb_header *header)
{ {
#if defined(TTYS0_BASE) #if defined(CONFIG_TTYS0_BASE)
struct lb_record *rec; struct lb_record *rec;
struct lb_serial *serial; struct lb_serial *serial;
rec = lb_new_record(header); rec = lb_new_record(header);
serial = (struct lb_serial *)rec; serial = (struct lb_serial *)rec;
serial->tag = LB_TAG_SERIAL; serial->tag = LB_TAG_SERIAL;
serial->size = sizeof(*serial); serial->size = sizeof(*serial);
serial->ioport = TTYS0_BASE; serial->ioport = CONFIG_TTYS0_BASE;
serial->baud = TTYS0_BAUD; serial->baud = CONFIG_TTYS0_BAUD;
return serial; return serial;
#else #else
return header; return header;
@ -157,9 +157,9 @@ struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
cmos_checksum->size = (sizeof(*cmos_checksum)); cmos_checksum->size = (sizeof(*cmos_checksum));
cmos_checksum->range_start = LB_CKS_RANGE_START * 8; cmos_checksum->range_start = CONFIG_LB_CKS_RANGE_START * 8;
cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; cmos_checksum->range_end = ( CONFIG_LB_CKS_RANGE_END * 8 ) + 7;
cmos_checksum->location = LB_CKS_LOC * 8; cmos_checksum->location = CONFIG_LB_CKS_LOC * 8;
cmos_checksum->type = CHECKSUM_PCBIOS; cmos_checksum->type = CHECKSUM_PCBIOS;
return cmos_checksum; return cmos_checksum;
@ -413,7 +413,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
return mem; return mem;
} }
#if HAVE_HIGH_TABLES == 1 #if CONFIG_HAVE_HIGH_TABLES == 1
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
@ -424,7 +424,7 @@ unsigned long write_coreboot_table(
struct lb_header *head; struct lb_header *head;
struct lb_memory *mem; struct lb_memory *mem;
#if HAVE_HIGH_TABLES == 1 #if CONFIG_HAVE_HIGH_TABLES == 1
printk_debug("Writing high table forward entry at 0x%08lx\n", printk_debug("Writing high table forward entry at 0x%08lx\n",
low_table_end); low_table_end);
head = lb_table_init(low_table_end); head = lb_table_init(low_table_end);
@ -460,7 +460,7 @@ unsigned long write_coreboot_table(
rom_table_end &= ~0xffff; rom_table_end &= ~0xffff;
printk_debug("0x%08lx \n", rom_table_end); printk_debug("0x%08lx \n", rom_table_end);
#if (HAVE_OPTION_TABLE == 1) #if (CONFIG_HAVE_OPTION_TABLE == 1)
{ {
struct lb_record *rec_dest, *rec_src; struct lb_record *rec_dest, *rec_src;
/* Write the option config table... */ /* Write the option config table... */
@ -482,13 +482,13 @@ unsigned long write_coreboot_table(
lb_add_memory_range(mem, LB_MEM_TABLE, lb_add_memory_range(mem, LB_MEM_TABLE,
rom_table_start, rom_table_end-rom_table_start); rom_table_start, rom_table_end-rom_table_start);
#if HAVE_HIGH_TABLES == 1 #if CONFIG_HAVE_HIGH_TABLES == 1
printk_debug("Adding high table area\n"); printk_debug("Adding high table area\n");
lb_add_memory_range(mem, LB_MEM_TABLE, lb_add_memory_range(mem, LB_MEM_TABLE,
high_tables_base, high_tables_size); high_tables_base, high_tables_size);
#endif #endif
#if (HAVE_MAINBOARD_RESOURCES == 1) #if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
add_mainboard_resources(mem); add_mainboard_resources(mem);
#endif #endif

8
src/arch/i386/boot/pirq_routing.c
View File

@ -3,7 +3,7 @@
#include <string.h> #include <string.h>
#include <device/pci.h> #include <device/pci.h>
#if (DEBUG==1 && HAVE_PIRQ_TABLE==1) #if (CONFIG_DEBUG==1 && CONFIG_HAVE_PIRQ_TABLE==1)
static void check_pirq_routing_table(struct irq_routing_table *rt) static void check_pirq_routing_table(struct irq_routing_table *rt)
{ {
uint8_t *addr = (uint8_t *)rt; uint8_t *addr = (uint8_t *)rt;
@ -12,7 +12,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
printk_info("Checking Interrupt Routing Table consistency...\n"); printk_info("Checking Interrupt Routing Table consistency...\n");
#if defined(IRQ_SLOT_COUNT) #if defined(CONFIG_IRQ_SLOT_COUNT)
if (sizeof(struct irq_routing_table) != rt->size) { if (sizeof(struct irq_routing_table) != rt->size) {
printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
sizeof(struct irq_routing_table), sizeof(struct irq_routing_table),
@ -83,7 +83,7 @@ static int verify_copy_pirq_routing_table(unsigned long addr)
#define verify_copy_pirq_routing_table(addr) #define verify_copy_pirq_routing_table(addr)
#endif #endif
#if HAVE_PIRQ_TABLE==1 #if CONFIG_HAVE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long addr) unsigned long copy_pirq_routing_table(unsigned long addr)
{ {
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
@ -100,7 +100,7 @@ unsigned long copy_pirq_routing_table(unsigned long addr)
} }
#endif #endif
#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) #if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1)
void pirq_routing_irqs(unsigned long addr) void pirq_routing_irqs(unsigned long addr)
{ {
int i, j, k, num_entries; int i, j, k, num_entries;

6
src/arch/i386/boot/tables.c
View File

@ -104,7 +104,7 @@ struct lb_memory *write_tables(void)
post_code(0x9a); post_code(0x9a);
/* Write ACPI tables to F segment and high tables area */ /* Write ACPI tables to F segment and high tables area */
#if HAVE_ACPI_TABLES == 1 #if CONFIG_HAVE_ACPI_TABLES == 1
if (high_tables_base) { if (high_tables_base) {
unsigned long acpi_start = high_table_end; unsigned long acpi_start = high_table_end;
rom_table_end = ALIGN(rom_table_end, 16); rom_table_end = ALIGN(rom_table_end, 16);
@ -129,7 +129,7 @@ struct lb_memory *write_tables(void)
#endif #endif
post_code(0x9b); post_code(0x9b);
#if HAVE_MP_TABLE == 1 #if CONFIG_HAVE_MP_TABLE == 1
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
rom_table_end = write_smp_table(rom_table_end); rom_table_end = write_smp_table(rom_table_end);
rom_table_end = ALIGN(rom_table_end, 1024); rom_table_end = ALIGN(rom_table_end, 1024);
@ -139,7 +139,7 @@ struct lb_memory *write_tables(void)
high_table_end = write_smp_table(high_table_end); high_table_end = write_smp_table(high_table_end);
high_table_end = ALIGN(high_table_end, 1024); high_table_end = ALIGN(high_table_end, 1024);
} }
#endif /* HAVE_MP_TABLE */ #endif /* CONFIG_HAVE_MP_TABLE */
post_code(0x9c); post_code(0x9c);

12
src/arch/i386/include/arch/acpi.h
View File

@ -13,11 +13,11 @@
#ifndef __ASM_ACPI_H #ifndef __ASM_ACPI_H
#define __ASM_ACPI_H #define __ASM_ACPI_H
#if HAVE_ACPI_TABLES==1 #if CONFIG_HAVE_ACPI_TABLES==1
#include <stdint.h> #include <stdint.h>
#if HAVE_ACPI_RESUME #if CONFIG_HAVE_ACPI_RESUME
/* 0 = S0, 1 = S1 ...*/ /* 0 = S0, 1 = S1 ...*/
extern u8 acpi_slp_type; extern u8 acpi_slp_type;
#endif #endif
@ -88,13 +88,13 @@ typedef struct acpi_table_header /* ACPI common table header */
/* RSDT */ /* RSDT */
typedef struct acpi_rsdt { typedef struct acpi_rsdt {
struct acpi_table_header header; struct acpi_table_header header;
u32 entry[7+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/ u32 entry[7+CONFIG_ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
} __attribute__ ((packed)) acpi_rsdt_t; } __attribute__ ((packed)) acpi_rsdt_t;
/* XSDT */ /* XSDT */
typedef struct acpi_xsdt { typedef struct acpi_xsdt {
struct acpi_table_header header; struct acpi_table_header header;
u64 entry[6+ACPI_SSDTX_NUM]; u64 entry[6+CONFIG_ACPI_SSDTX_NUM];
} __attribute__ ((packed)) acpi_xsdt_t; } __attribute__ ((packed)) acpi_xsdt_t;
/* HPET TIMERS */ /* HPET TIMERS */
@ -367,7 +367,7 @@ void acpi_create_facs(acpi_facs_t *facs);
void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_rsdt(acpi_rsdt_t *rsdt);
void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt);
#if HAVE_ACPI_RESUME #if CONFIG_HAVE_ACPI_RESUME
void suspend_resume(void); void suspend_resume(void);
void *acpi_find_wakeup_vector(void); void *acpi_find_wakeup_vector(void);
void *acpi_get_wakeup_rsdp(void); void *acpi_get_wakeup_rsdp(void);
@ -390,7 +390,7 @@ do { \
#define IO_APIC_ADDR 0xfec00000UL #define IO_APIC_ADDR 0xfec00000UL
#else // HAVE_ACPI_TABLES #else // CONFIG_HAVE_ACPI_TABLES
#define write_acpi_tables(start) (start) #define write_acpi_tables(start) (start)

4
src/arch/i386/include/arch/cpu.h
View File

@ -128,8 +128,8 @@ static inline struct cpu_info *cpu_info(void)
__asm__("andl %%esp,%0; " __asm__("andl %%esp,%0; "
"orl %2, %0 " "orl %2, %0 "
:"=r" (ci) :"=r" (ci)
: "0" (~(STACK_SIZE - 1)), : "0" (~(CONFIG_STACK_SIZE - 1)),
"r" (STACK_SIZE - sizeof(struct cpu_info)) "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
); );
return ci; return ci;
} }

2
src/arch/i386/include/arch/pci_ops.h
View File

@ -4,7 +4,7 @@
extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_cf8_conf2; extern const struct pci_bus_operations pci_cf8_conf2;
#if MMCONF_SUPPORT==1 #if CONFIG_MMCONF_SUPPORT==1
extern const struct pci_bus_operations pci_ops_mmconf; extern const struct pci_bus_operations pci_ops_mmconf;
#endif #endif

2
src/arch/i386/include/arch/pciconf.h
View File

@ -5,7 +5,7 @@
#define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_INDEX 0xcf8
#define PCI_CONF_REG_DATA 0xcfc #define PCI_CONF_REG_DATA 0xcfc
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
#else #else
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )

8
src/arch/i386/include/arch/pirq_routing.h
View File

@ -16,8 +16,8 @@ struct irq_info {
uint8_t rfu; uint8_t rfu;
} __attribute__((packed)); } __attribute__((packed));
#if defined(IRQ_SLOT_COUNT) #if defined(CONFIG_IRQ_SLOT_COUNT)
#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT #define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
#elif (__GNUC__ < 3) #elif (__GNUC__ < 3)
#define IRQ_SLOTS_COUNT 1 #define IRQ_SLOTS_COUNT 1
#else #else
@ -39,10 +39,10 @@ struct irq_routing_table {
extern const struct irq_routing_table intel_irq_routing_table; extern const struct irq_routing_table intel_irq_routing_table;
#if HAVE_PIRQ_TABLE==1 #if CONFIG_HAVE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long start); unsigned long copy_pirq_routing_table(unsigned long start);
unsigned long write_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start);
#if PIRQ_ROUTE==1 #if CONFIG_PIRQ_ROUTE==1
void pirq_routing_irqs(unsigned long start); void pirq_routing_irqs(unsigned long start);
void pirq_assign_irqs(const unsigned char pIntAtoD[4]); void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
#else #else

52
src/arch/i386/include/arch/romcc_io.h
View File

@ -34,7 +34,7 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
*((volatile uint32_t *)(addr)) = value; *((volatile uint32_t *)(addr)) = value;
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
#include <arch/mmio_conf.h> #include <arch/mmio_conf.h>
@ -92,7 +92,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
@ -101,17 +101,17 @@ static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_
return inb(0xCFC + (addr & 3)); return inb(0xCFC + (addr & 3));
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
return read8x(addr); return read8x(addr);
} }
#endif #endif
static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config8(dev, where); return pci_mmio_read_config8(dev, where);
#else #else
return pci_io_read_config8(dev, where); return pci_io_read_config8(dev, where);
@ -121,7 +121,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -130,18 +130,18 @@ static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic
return inw(0xCFC + (addr & 2)); return inw(0xCFC + (addr & 2));
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
return read16x(addr); return read16x(addr);
} }
#endif #endif
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config16(dev, where); return pci_mmio_read_config16(dev, where);
#else #else
return pci_io_read_config16(dev, where); return pci_io_read_config16(dev, where);
@ -152,7 +152,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -161,18 +161,18 @@ static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic
return inl(0xCFC); return inl(0xCFC);
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
return read32x(addr); return read32x(addr);
} }
#endif #endif
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config32(dev, where); return pci_mmio_read_config32(dev, where);
#else #else
return pci_io_read_config32(dev, where); return pci_io_read_config32(dev, where);
@ -182,7 +182,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -191,18 +191,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config8(device_t
outb(value, 0xCFC + (addr & 3)); outb(value, 0xCFC + (addr & 3));
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
write8x(addr, value); write8x(addr, value);
} }
#endif #endif
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config8(dev, where, value); pci_mmio_write_config8(dev, where, value);
#else #else
pci_io_write_config8(dev, where, value); pci_io_write_config8(dev, where, value);
@ -213,7 +213,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -222,18 +222,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config16(device_t
outw(value, 0xCFC + (addr & 2)); outw(value, 0xCFC + (addr & 2));
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
write16x(addr, value); write16x(addr, value);
} }
#endif #endif
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config16(dev, where, value); pci_mmio_write_config16(dev, where, value);
#else #else
pci_io_write_config16(dev, where, value); pci_io_write_config16(dev, where, value);
@ -244,7 +244,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
{ {
unsigned addr; unsigned addr;
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where; addr = (dev>>4) | where;
#else #else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -253,18 +253,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config32(device_t
outl(value, 0xCFC); outl(value, 0xCFC);
} }
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
{ {
unsigned addr; unsigned addr;
addr = MMCONF_BASE_ADDRESS | dev | where; addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
write32x(addr, value); write32x(addr, value);
} }
#endif #endif
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
{ {
#if MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config32(dev, where, value); pci_mmio_write_config32(dev, where, value);
#else #else
pci_io_write_config32(dev, where, value); pci_io_write_config32(dev, where, value);
@ -286,7 +286,7 @@ static device_t pci_io_locate_device(unsigned pci_id, device_t dev)
static device_t pci_locate_device(unsigned pci_id, device_t dev) static device_t pci_locate_device(unsigned pci_id, device_t dev)
{ {
for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id; unsigned int id;
id = pci_read_config32(dev, 0); id = pci_read_config32(dev, 0);
if (id == pci_id) { if (id == pci_id) {

10
src/arch/i386/init/car.S
View File

@ -72,8 +72,8 @@ __protected_stage0:
* the other is very similar to the AMD CAR, except remove amd specific msr * the other is very similar to the AMD CAR, except remove amd specific msr
*/ */
#define CacheSize DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase DCACHE_RAM_BASE #define CacheBase CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
@ -241,14 +241,14 @@ clear_fixed_var_mtrr_out:
*/ */
movl $0x202, %ecx movl $0x202, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $0x203, %ecx movl $0x203, %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax

28
src/arch/i386/init/crt0.S.lb
View File

@ -37,14 +37,14 @@
#include "crt0_includes.h" #include "crt0_includes.h"
#if USE_DCACHE_RAM == 0 #if CONFIG_USE_DCACHE_RAM == 0
#ifndef CONSOLE_DEBUG_TX_STRING #ifndef CONSOLE_DEBUG_TX_STRING
/* uses: esp, ebx, ax, dx */ /* uses: esp, ebx, ax, dx */
# define __CRT_CONSOLE_TX_STRING(string) \ # define __CRT_CONSOLE_TX_STRING(string) \
mov string, %ebx ; \ mov string, %ebx ; \
CALLSP(crt_console_tx_string) CALLSP(crt_console_tx_string)
# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
# else # else
# define CONSOLE_DEBUG_TX_STRING(string) # define CONSOLE_DEBUG_TX_STRING(string)
@ -102,26 +102,26 @@ crt_console_tx_string:
RETSP RETSP
9: 9:
/* Base Address */ /* Base Address */
#ifndef TTYS0_BASE #ifndef CONFIG_TTYS0_BASE
#define TTYS0_BASE 0x3f8 #define CONFIG_TTYS0_BASE 0x3f8
#endif #endif
/* Data */ /* Data */
#define TTYS0_RBR (TTYS0_BASE+0x00) #define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
/* Control */ /* Control */
#define TTYS0_TBR TTYS0_RBR #define TTYS0_TBR TTYS0_RBR
#define TTYS0_IER (TTYS0_BASE+0x01) #define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
#define TTYS0_IIR (TTYS0_BASE+0x02) #define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
#define TTYS0_FCR TTYS0_IIR #define TTYS0_FCR TTYS0_IIR
#define TTYS0_LCR (TTYS0_BASE+0x03) #define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
#define TTYS0_MCR (TTYS0_BASE+0x04) #define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
#define TTYS0_DLL TTYS0_RBR #define TTYS0_DLL TTYS0_RBR
#define TTYS0_DLM TTYS0_IER #define TTYS0_DLM TTYS0_IER
/* Status */ /* Status */
#define TTYS0_LSR (TTYS0_BASE+0x05) #define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
#define TTYS0_MSR (TTYS0_BASE+0x06) #define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
#define TTYS0_SCR (TTYS0_BASE+0x07) #define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
mov %al, %ah mov %al, %ah
10: mov $TTYS0_LSR, %dx 10: mov $TTYS0_LSR, %dx
@ -143,7 +143,7 @@ str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n"
str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
#endif #endif
#if CONFIG_CBFS #if CONFIG_CBFS
# if USE_FALLBACK_IMAGE == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1
str_coreboot_ram_name: .string "fallback/coreboot_ram" str_coreboot_ram_name: .string "fallback/coreboot_ram"
# else # else
str_coreboot_ram_name: .string "normal/coreboot_ram" str_coreboot_ram_name: .string "normal/coreboot_ram"
@ -154,4 +154,4 @@ str_pre_main: .string "Jumping to coreboot.\r\n"
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
#endif /* USE_DCACHE_RAM */ #endif /* CONFIG_USE_DCACHE_RAM */

8
src/arch/i386/init/ldscript.lb
View File

@ -1,12 +1,12 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
* : stack * : stack
* _ROMBASE * CONFIG_ROMBASE
* : coreboot text * : coreboot text
* : readonly text * : readonly text
*/ */
@ -35,7 +35,7 @@ TARGET(binary)
INPUT(coreboot_ram.rom) INPUT(coreboot_ram.rom)
SECTIONS SECTIONS
{ {
. = _ROMBASE; . = CONFIG_ROMBASE;
.ram . : { .ram . : {
_ram = . ; _ram = . ;
@ -56,7 +56,7 @@ SECTIONS
_lrom = LOADADDR(.rom); _lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom); _elrom = LOADADDR(.rom) + SIZEOF(.rom);
_iseg = _RAMBASE; _iseg = CONFIG_RAMBASE;
_eiseg = _iseg + SIZEOF(.ram); _eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram; _liseg = _ram;
_eliseg = _eram; _eliseg = _eram;

2
src/arch/i386/init/ldscript_apc.lb
View File

@ -6,7 +6,7 @@ SECTIONS
coreboot_apc.rom(*) coreboot_apc.rom(*)
_eapcrom = .; _eapcrom = .;
} }
_iseg_apc = DCACHE_RAM_BASE; _iseg_apc = CONFIG_DCACHE_RAM_BASE;
_eiseg_apc = _iseg_apc + SIZEOF(.apcrom); _eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
_liseg_apc = _apcrom; _liseg_apc = _apcrom;
_eliseg_apc = _eapcrom; _eliseg_apc = _eapcrom;

6
src/arch/i386/init/ldscript_cbfs.lb
View File

@ -1,12 +1,12 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
* : stack * : stack
* _ROMBASE * CONFIG_ROMBASE
* : coreboot text * : coreboot text
* : readonly text * : readonly text
*/ */
@ -34,7 +34,7 @@ ENTRY(_start)
TARGET(binary) TARGET(binary)
SECTIONS SECTIONS
{ {
. = _ROMBASE; . = CONFIG_ROMBASE;
/* This section might be better named .setup */ /* This section might be better named .setup */
.rom . : { .rom . : {

6
src/arch/i386/init/ldscript_failover.lb
View File

@ -1,12 +1,12 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
* : stack * : stack
* _ROMBASE * CONFIG_ROMBASE
* : coreboot text * : coreboot text
* : readonly text * : readonly text
*/ */
@ -34,7 +34,7 @@ ENTRY(_start)
TARGET(binary) TARGET(binary)
SECTIONS SECTIONS
{ {
. = _ROMBASE; . = CONFIG_ROMBASE;
/* This section might be better named .setup */ /* This section might be better named .setup */
.rom . : { .rom . : {

10
src/arch/i386/init/ldscript_fallback.lb
View File

@ -1,12 +1,12 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
* : stack * : stack
* _ROMBASE * CONFIG_ROMBASE
* : coreboot text * : coreboot text
* : readonly text * : readonly text
*/ */
@ -35,7 +35,7 @@ TARGET(binary)
INPUT(coreboot_ram.rom) INPUT(coreboot_ram.rom)
SECTIONS SECTIONS
{ {
. = _ROMBASE; . = CONFIG_ROMBASE;
.ram . : { .ram . : {
_ram = . ; _ram = . ;
@ -45,7 +45,7 @@ SECTIONS
/* cut _start into last 64k*/ /* cut _start into last 64k*/
_x = .; _x = .;
. = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x;
/* This section might be better named .setup */ /* This section might be better named .setup */
.rom . : { .rom . : {
@ -61,7 +61,7 @@ SECTIONS
_lrom = LOADADDR(.rom); _lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom); _elrom = LOADADDR(.rom) + SIZEOF(.rom);
_iseg = _RAMBASE; _iseg = CONFIG_RAMBASE;
_eiseg = _iseg + SIZEOF(.ram); _eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram; _liseg = _ram;
_eliseg = _eram; _eliseg = _eram;

8
src/arch/i386/init/ldscript_fallback_cbfs.lb
View File

@ -1,12 +1,12 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
* : stack * : stack
* _ROMBASE * CONFIG_ROMBASE
* : coreboot text * : coreboot text
* : readonly text * : readonly text
*/ */
@ -34,11 +34,11 @@ ENTRY(_start)
TARGET(binary) TARGET(binary)
SECTIONS SECTIONS
{ {
. = _ROMBASE; . = CONFIG_ROMBASE;
/* cut _start into last 64k*/ /* cut _start into last 64k*/
_x = .; _x = .;
. = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x;
/* This section might be better named .setup */ /* This section might be better named .setup */
.rom . : { .rom . : {

4
src/arch/i386/lib/Config.lb
View File

@ -1,6 +1,6 @@
uses CONFIG_USE_INIT uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_USE_PRINTK_IN_CAR
uses USE_FAILOVER_IMAGE uses CONFIG_USE_FAILOVER_IMAGE
uses CONFIG_CBFS uses CONFIG_CBFS
object c_start.S object c_start.S
@ -13,7 +13,7 @@ object exception.c
initobject printk_init.o initobject printk_init.o
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
else else
if CONFIG_CBFS if CONFIG_CBFS
initobject cbfs_and_run.o initobject cbfs_and_run.o

18
src/arch/i386/lib/console_printk.c
View File

@ -11,39 +11,39 @@ extern int do_printk(int msg_level, const char *fmt, ...);
#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) #define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg) #define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg)
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
#undef printk_emerg #undef printk_emerg
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
#undef printk_alert #undef printk_alert
#define printk_alert(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_alert(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
#undef printk_crit #undef printk_crit
#define printk_crit(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_crit(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
#undef printk_err #undef printk_err
#define printk_err(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_err(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
#undef printk_warning #undef printk_warning
#define printk_warning(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_warning(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
#undef printk_notice #undef printk_notice
#define printk_notice(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_notice(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
#undef printk_info #undef printk_info
#define printk_info(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_info(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
#undef printk_debug #undef printk_debug
#define printk_debug(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_debug(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
#undef printk_spew #undef printk_spew
#define printk_spew(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #define printk_spew(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg)
#endif #endif

2
src/arch/i386/lib/failover_failover.lds
View File

@ -1,2 +1,2 @@
__fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8; __fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
__normal_image = ((CONFIG_ROM_PAYLOAD_START - FALLBACK_SIZE) & 0xfffffff0) - 8; __normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;

6
src/arch/i386/lib/id.inc
View File

@ -3,12 +3,12 @@
.globl __id_start .globl __id_start
__id_start: __id_start:
vendor: vendor:
.asciz MAINBOARD_VENDOR .asciz CONFIG_MAINBOARD_VENDOR
part: part:
.asciz MAINBOARD_PART_NUMBER .asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end + 0x10 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x10 - vendor /* Reverse offset to the vendor id */
.long __id_end + 0x10 - part /* Reverse offset to the part number */ .long __id_end + 0x10 - part /* Reverse offset to the part number */
.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ .long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */
.globl __id_end .globl __id_end
__id_end: __id_end:

2
src/arch/i386/lib/id.lds
View File

@ -1,5 +1,5 @@
SECTIONS { SECTIONS {
. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start); . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
.id (.): { .id (.): {
*(.id) *(.id)
} }

2
src/arch/i386/lib/pci_ops_conf1.c
View File

@ -8,7 +8,7 @@
* Functions for accessing PCI configuration space with type 1 accesses * Functions for accessing PCI configuration space with type 1 accesses
*/ */
#if PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
#else #else
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )

4
src/arch/i386/lib/pci_ops_mmconf.c
View File

@ -1,4 +1,4 @@
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
#include <console/console.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
@ -13,7 +13,7 @@
*/ */
#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \
MMCONF_BASE_ADDRESS | \ CONFIG_MMCONF_BASE_ADDRESS | \
(((SEGBUS) & 0xFFF) << 20) | \ (((SEGBUS) & 0xFFF) << 20) | \
(((DEVFN) & 0xFF) << 12) | \ (((DEVFN) & 0xFF) << 12) | \
((WHERE) & 0xFFF)) ((WHERE) & 0xFFF))

6
src/arch/i386/lib/printk_init.c
View File

@ -14,7 +14,7 @@
/* Keep together for sysctl support */ /* Keep together for sysctl support */
/* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/ /* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/
#if 0 #if 0
int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
#else #else
#define console_loglevel ASM_CONSOLE_LOGLEVEL #define console_loglevel ASM_CONSOLE_LOGLEVEL
#endif #endif
@ -25,8 +25,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char);
void console_tx_byte(unsigned char byte) void console_tx_byte(unsigned char byte)
{ {
if (byte == '\n') if (byte == '\n')
uart8250_tx_byte(TTYS0_BASE, '\r'); uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
uart8250_tx_byte(TTYS0_BASE, byte); uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
} }
int do_printk(int msg_level, const char *fmt, ...) int do_printk(int msg_level, const char *fmt, ...)

4
src/arch/i386/smp/Config.lb
View File

@ -1,6 +1,6 @@
uses HAVE_MP_TABLE uses CONFIG_HAVE_MP_TABLE
if HAVE_MP_TABLE if CONFIG_HAVE_MP_TABLE
object mpspec.o object mpspec.o
end end
#object ioapic.o CONFIG_IOAPIC #object ioapic.o CONFIG_IOAPIC

2
src/arch/ppc/boot/coreboot_table.c
View File

@ -340,7 +340,7 @@ unsigned long write_coreboot_table(
head = lb_table_init(low_table_end); head = lb_table_init(low_table_end);
low_table_end = (unsigned long)head; low_table_end = (unsigned long)head;
if (HAVE_OPTION_TABLE == 1) { if (CONFIG_HAVE_OPTION_TABLE == 1) {
struct lb_record *rec_dest, *rec_src; struct lb_record *rec_dest, *rec_src;
/* Write the option config table... */ /* Write the option config table... */
rec_dest = lb_new_record(head); rec_dest = lb_new_record(head);

16
src/arch/ppc/include/arch/cpu.h
View File

@ -13,24 +13,24 @@ struct cpu_driver {
struct cpu_device_id *id_table; struct cpu_device_id *id_table;
}; };
#ifndef STACK_SIZE #ifndef CONFIG_STACK_SIZE
#error STACK_SIZE not defined #error CONFIG_STACK_SIZE not defined
#endif #endif
/* The basic logic comes from the Linux kernel. /* The basic logic comes from the Linux kernel.
* The invariant is that (1 << 31 - STACK_BITS) == STACK_SIZE * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE
* I wish there was simpler way to support multiple stack sizes. * I wish there was simpler way to support multiple stack sizes.
* Oh well. * Oh well.
*/ */
#if STACK_SIZE == 4096 #if CONFIG_STACK_SIZE == 4096
#define STACK_BITS "19" #define STACK_BITS "19"
#elif STACK_SIZE == 8192 #elif CONFIG_STACK_SIZE == 8192
#define STACK_BITS "18" #define STACK_BITS "18"
#elif STACK_SIZE == 16384 #elif CONFIG_STACK_SIZE == 16384
#define STACK_BITS "17" #define STACK_BITS "17"
#elif STACK_SIZE == 32768 #elif CONFIG_STACK_SIZE == 32768
#define STACK_BITS "16" #define STACK_BITS "16"
#elif STACK_SIZE == 65536 #elif CONFIG_STACK_SIZE == 65536
#define STACK_BITS "15" #define STACK_BITS "15"
#else #else
#error Unimplemented stack size #error Unimplemented stack size

24
src/arch/ppc/include/arch/io.h
View File

@ -11,8 +11,8 @@
#define SLOW_DOWN_IO #define SLOW_DOWN_IO
#ifndef _IO_BASE #ifndef CONFIG_IO_BASE
#define _IO_BASE 0 #define CONFIG_IO_BASE 0
#endif #endif
#define readb(addr) in_8((volatile uint8_t *)(addr)) #define readb(addr) in_8((volatile uint8_t *)(addr))
@ -36,15 +36,15 @@
* are arrays of bytes, and byte-swapping is not appropriate in * are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus * that case. - paulus
*/ */
#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) #define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) #define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) #define inb(port) in_8((uint8_t *)((port)+CONFIG_IO_BASE))
#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) #define outb(val, port) out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val))
#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) #define inw(port) in_le16((uint16_t *)((port)+CONFIG_IO_BASE))
#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) #define outw(val, port) out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val))
#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) #define inl(port) in_le32((uint32_t *)((port)+CONFIG_IO_BASE))
#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) #define outl(val, port) out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val))
#define inb_p(port) inb((port)) #define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port)) #define outb_p(val, port) outb((val), (port))
@ -56,8 +56,8 @@
/* /*
* The *_ns versions below do byte-swapping. * The *_ns versions below do byte-swapping.
*/ */
#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+_IO_BASE), (buf), (ns)) #define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+_IO_BASE), (buf), (ns)) #define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
#define IO_SPACE_LIMIT ~0 #define IO_SPACE_LIMIT ~0

8
src/arch/ppc/include/arch/pirq_routing.h
View File

@ -16,8 +16,8 @@ struct irq_info {
u8 rfu; u8 rfu;
} __attribute__((packed)); } __attribute__((packed));
#if defined(IRQ_SLOT_COUNT) #if defined(CONFIG_IRQ_SLOT_COUNT)
#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT #define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
#elif (__GNUC__ < 3) #elif (__GNUC__ < 3)
#define IRQ_SLOTS_COUNT 1 #define IRQ_SLOTS_COUNT 1
#else #else
@ -39,13 +39,13 @@ struct irq_routing_table {
extern const struct irq_routing_table intel_irq_routing_table; extern const struct irq_routing_table intel_irq_routing_table;
#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) #if defined(CONFIG_DEBUG) && defined(CONFIG_HAVE_PIRQ_TABLE)
void check_pirq_routing_table(void); void check_pirq_routing_table(void);
#else #else
#define check_pirq_routing_table() do {} while(0) #define check_pirq_routing_table() do {} while(0)
#endif #endif
#if defined(HAVE_PIRQ_TABLE) #if defined(CONFIG_HAVE_PIRQ_TABLE)
unsigned long copy_pirq_routing_table(unsigned long start); unsigned long copy_pirq_routing_table(unsigned long start);
#else #else
#define copy_pirq_routing_table(start) (start) #define copy_pirq_routing_table(start) (start)

20
src/arch/ppc/init/crt0.S.lb
View File

@ -30,8 +30,8 @@ system_reset:
*/ */
%%PROCESSOR_INIT%% %%PROCESSOR_INIT%%
#if USE_DCACHE_RAM == 1 #if CONFIG_USE_DCACHE_RAM == 1
#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1) #define DCACHE_RAM_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
/* /*
* Initialize data cache blocks * Initialize data cache blocks
* (assumes cache block size of 32 bytes) * (assumes cache block size of 32 bytes)
@ -39,9 +39,9 @@ system_reset:
* NOTE: This may need to be moved to FAMILY_INIT if * NOTE: This may need to be moved to FAMILY_INIT if
* dcbz is not supported on all CPU's * dcbz is not supported on all CPU's
*/ */
lis r1, DCACHE_RAM_BASE@h lis r1, CONFIG_DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32) li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3 mtctr r3
0: dcbz r0, r1 0: dcbz r0, r1
addi r1, r1, 32 addi r1, r1, 32
@ -53,8 +53,8 @@ system_reset:
* it 16-byte aligned to cover both cases. Also we have to ensure that * it 16-byte aligned to cover both cases. Also we have to ensure that
* the first word is located within the cache. * the first word is located within the cache.
*/ */
lis r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h lis r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
ori r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l ori r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
lis r0, 0 lis r0, 0
stwu r0, -4(r1) stwu r0, -4(r1)
stwu r0, -4(r1) stwu r0, -4(r1)
@ -65,8 +65,8 @@ system_reset:
/* /*
* Clear stack * Clear stack
*/ */
lis r4, DCACHE_RAM_BASE@h lis r4, CONFIG_DCACHE_RAM_BASE@h
ori r4, r4, DCACHE_RAM_BASE@l ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
lis r7, DCACHE_RAM_END@h lis r7, DCACHE_RAM_END@h
ori r7, r7, DCACHE_RAM_END@l ori r7, r7, DCACHE_RAM_END@l
lis r5, 0 lis r5, 0
@ -110,7 +110,7 @@ system_reset:
* Complete rest of initialization in C (ppc_main) * Complete rest of initialization in C (ppc_main)
*/ */
rfi rfi
#endif /* USE_DCACHE_RAM */ #endif /* CONFIG_USE_DCACHE_RAM */
/* /*
* Stop here if something goes wrong * Stop here if something goes wrong

18
src/arch/ppc/init/ldscript.lb
View File

@ -1,14 +1,14 @@
/* /*
* Memory map: * Memory map:
* *
* _ROMBASE : start of ROM * CONFIG_ROMBASE : start of ROM
* _RESET : reset vector (may be at top of ROM) * CONFIG_RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table * _EXCEPTIONS_VECTORS : exception table
* *
* _ROMSTART : coreboot text * CONFIG_ROMSTART : coreboot text
* : payload text * : payload text
* *
* _RAMBASE : address to copy payload * CONFIG_RAMBASE : address to copy payload
*/ */
/* /*
@ -32,13 +32,13 @@ SECTIONS
/* /*
* Absolute location of base of ROM * Absolute location of base of ROM
*/ */
. = _ROMBASE; . = CONFIG_ROMBASE;
/* /*
* Absolute location of reset vector. This may actually be at the * Absolute location of reset vector. This may actually be at the
* the top of ROM. * the top of ROM.
*/ */
. = _RESET; . = CONFIG_RESET;
.reset . : { .reset . : {
*(.rom.reset); *(.rom.reset);
. = ALIGN(16); . = ALIGN(16);
@ -47,7 +47,7 @@ SECTIONS
/* /*
* Absolute location of exception vector table. * Absolute location of exception vector table.
*/ */
. = _EXCEPTION_VECTORS; . = CONFIG_EXCEPTION_VECTORS;
.exception_vectors . : { .exception_vectors . : {
*(.rom.exception_vectors); *(.rom.exception_vectors);
. = ALIGN(16); . = ALIGN(16);
@ -56,7 +56,7 @@ SECTIONS
/* /*
* Absolute location of coreboot initialization code in ROM. * Absolute location of coreboot initialization code in ROM.
*/ */
. = _ROMSTART; . = CONFIG_ROMSTART;
.rom . : { .rom . : {
_rom = .; _rom = .;
*(.rom.text); *(.rom.text);
@ -94,7 +94,7 @@ SECTIONS
/* /*
* Absolute location of where coreboot will be relocated in RAM. * Absolute location of where coreboot will be relocated in RAM.
*/ */
_iseg = _RAMBASE; _iseg = CONFIG_RAMBASE;
_eiseg = _iseg + SIZEOF(.ram); _eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram; _liseg = _ram;
_eliseg = _eram; _eliseg = _eram;

24
src/arch/ppc/lib/pci_dev.c
View File

@ -9,8 +9,8 @@ uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where)
{ {
uint8_t res; uint8_t res;
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
res = in_8((unsigned char *)PCIC0_CFGDATA + (where & 3)); res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3));
return res; return res;
} }
@ -18,8 +18,8 @@ uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where)
{ {
uint16_t res; uint16_t res;
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
res = in_le16((unsigned short *)PCIC0_CFGDATA + (where & 2)); res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2));
return res; return res;
} }
@ -27,28 +27,28 @@ uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where)
{ {
uint32_t res; uint32_t res;
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
res = in_le32((unsigned *)PCIC0_CFGDATA); res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA);
return res; return res;
} }
int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data) int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data)
{ {
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
out_8((unsigned char *)PCIC0_CFGDATA + (where & 3), data); out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data);
return 0; return 0;
} }
int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data) int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data)
{ {
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
out_le16((unsigned short *)PCIC0_CFGDATA + (where & 2), data); out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data);
return 0; return 0;
} }
int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data) int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data)
{ {
out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
out_le32((unsigned *)PCIC0_CFGDATA, data); out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data);
return 0; return 0;
} }

6
src/arch/ppc/lib/printk_init.c
View File

@ -12,7 +12,7 @@
/* Keep together for sysctl support */ /* Keep together for sysctl support */
int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
extern int vtxprintf(void (*)(unsigned char), const char *, va_list); extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
extern void uart8250_tx_byte(unsigned, unsigned char); extern void uart8250_tx_byte(unsigned, unsigned char);
@ -20,8 +20,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char);
void console_tx_byte(unsigned char byte) void console_tx_byte(unsigned char byte)
{ {
if (byte == '\n') if (byte == '\n')
uart8250_tx_byte(TTYS0_BASE, '\r'); uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
uart8250_tx_byte(TTYS0_BASE, byte); uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
} }
int do_printk(int msg_level, const char *fmt, ...) int do_printk(int msg_level, const char *fmt, ...)

22
src/boot/filo.c
View File

@ -14,11 +14,11 @@
#define ENTER '\r' #define ENTER '\r'
#define ESCAPE '\x1b' #define ESCAPE '\x1b'
#ifndef AUTOBOOT_CMDLINE #ifndef CONFIG_AUTOBOOT_CMDLINE
#define autoboot(mem) #define autoboot(mem)
#endif #endif
#if !AUTOBOOT_DELAY #if !CONFIG_AUTOBOOT_DELAY
#define autoboot_delay() 0 /* success */ #define autoboot_delay() 0 /* success */
#endif #endif
@ -115,8 +115,8 @@ static void boot(struct lb_memory *mem, const char *line)
free(boot_file); free(boot_file);
} }
#ifdef AUTOBOOT_CMDLINE #ifdef CONFIG_AUTOBOOT_CMDLINE
#if AUTOBOOT_DELAY #if CONFIG_AUTOBOOT_DELAY
static inline int autoboot_delay(void) static inline int autoboot_delay(void)
{ {
unsigned int timeout; unsigned int timeout;
@ -126,7 +126,7 @@ static inline int autoboot_delay(void)
key = 0; key = 0;
printk_info("Press <Enter> for default boot, or <Esc> for boot prompt... "); printk_info("Press <Enter> for default boot, or <Esc> for boot prompt... ");
for (sec = AUTOBOOT_DELAY; sec>0 && key==0; sec--) { for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) {
printk_info("%d", sec); printk_info("%d", sec);
timeout = 10; timeout = 10;
while (timeout-- > 0) { while (timeout-- > 0) {
@ -151,7 +151,7 @@ static inline int autoboot_delay(void)
return 0; /* default accepted */ return 0; /* default accepted */
} }
} }
#endif /* AUTOBOOT_DELAY */ #endif /* CONFIG_AUTOBOOT_DELAY */
static void autoboot(struct lb_memory *mem) static void autoboot(struct lb_memory *mem)
{ {
@ -160,11 +160,11 @@ static void autoboot(struct lb_memory *mem)
return; return;
if (autoboot_delay()==0) { if (autoboot_delay()==0) {
printk_info("boot: %s\n", AUTOBOOT_CMDLINE); printk_info("boot: %s\n", CONFIG_AUTOBOOT_CMDLINE);
boot(mem, AUTOBOOT_CMDLINE); boot(mem, CONFIG_AUTOBOOT_CMDLINE);
} }
} }
#endif /* AUTOBOOT_CMDLINE */ #endif /* CONFIG_AUTOBOOT_CMDLINE */
/* The main routine */ /* The main routine */
int filo(struct lb_memory *mem) int filo(struct lb_memory *mem)
@ -179,8 +179,8 @@ int filo(struct lb_memory *mem)
/* The above didn't work, ask user */ /* The above didn't work, ask user */
while (havechar()) while (havechar())
getchar(); getchar();
#ifdef AUTOBOOT_CMDLINE #ifdef CONFIG_AUTOBOOT_CMDLINE
strncpy(line, AUTOBOOT_CMDLINE, sizeof(line)-1); strncpy(line, CONFIG_AUTOBOOT_CMDLINE, sizeof(line)-1);
line[sizeof(line)-1] = '\0'; line[sizeof(line)-1] = '\0';
#else #else
line[0] = '\0'; line[0] = '\0';

6
src/boot/hardwaremain.c
View File

@ -37,7 +37,7 @@ it with the version available from LANL.
#include <boot/tables.h> #include <boot/tables.h>
#include <boot/elf.h> #include <boot/elf.h>
#include <cbfs.h> #include <cbfs.h>
#if HAVE_ACPI_RESUME #if CONFIG_HAVE_ACPI_RESUME
#include <arch/acpi.h> #include <arch/acpi.h>
#endif #endif
@ -88,7 +88,7 @@ void hardwaremain(int boot_complete)
dev_initialize(); dev_initialize();
post_code(0x89); post_code(0x89);
#if HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
suspend_resume(); suspend_resume();
post_code(0x8a); post_code(0x8a);
#endif #endif
@ -98,7 +98,7 @@ void hardwaremain(int boot_complete)
*/ */
lb_mem = write_tables(); lb_mem = write_tables();
#if CONFIG_CBFS == 1 #if CONFIG_CBFS == 1
# if USE_FALLBACK_IMAGE == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_load_payload(lb_mem, "fallback/payload"); cbfs_load_payload(lb_mem, "fallback/payload");
# else # else
cbfs_load_payload(lb_mem, "normal/payload"); cbfs_load_payload(lb_mem, "normal/payload");

48
src/config/Config.lb
View File

@ -1,18 +1,18 @@
## This is Architecture independant part of the makefile ## This is Architecture independant part of the makefile
uses HAVE_OPTION_TABLE uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_AP_CODE_IN_CAR uses CONFIG_AP_CODE_IN_CAR
uses ASSEMBLER_DEBUG uses CONFIG_ASSEMBLER_DEBUG
makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
makedefine GCC ?= $(CC) makedefine GCC ?= $(CC)
makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
if ASSEMBLER_DEBUG if CONFIG_ASSEMBLER_DEBUG
makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
end end
@ -35,25 +35,25 @@ end
makerule coreboot.strip makerule coreboot.strip
depends "coreboot" depends "coreboot"
action "$(OBJCOPY) -O binary coreboot coreboot.strip" action "$(CONFIG_OBJCOPY) -O binary coreboot coreboot.strip"
end end
makerule coreboot.a makerule coreboot.a
depends "$(OBJECTS)" depends "$(OBJECTS)"
action "rm -f coreboot.a" action "rm -f coreboot.a"
action "$(CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)" action "$(CONFIG_CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)"
end end
makerule coreboot_ram.o makerule coreboot_ram.o
depends "src/arch/$(ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)"
end end
makerule coreboot_ram makerule coreboot_ram
depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map" action "$(CONFIG_CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
end end
## ##
@ -64,7 +64,7 @@ makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
makerule coreboot_ram.bin makerule coreboot_ram.bin
depends "coreboot_ram" depends "coreboot_ram"
action "$(OBJCOPY) -O binary $< $@" action "$(CONFIG_OBJCOPY) -O binary $< $@"
end end
makerule coreboot_ram.nrv2b makerule coreboot_ram.nrv2b
@ -85,18 +85,18 @@ if CONFIG_AP_CODE_IN_CAR
makerule coreboot_apc.a makerule coreboot_apc.a
depends "apc_auto.o" depends "apc_auto.o"
action "rm -f coreboot_apc.a" action "rm -f coreboot_apc.a"
action "$(CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o" action "$(CONFIG_CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o"
end end
makerule coreboot_apc.o makerule coreboot_apc.o
depends "src/arch/$(ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)" depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
end end
makerule coreboot_apc makerule coreboot_apc
depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions" depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map" action "$(CONFIG_CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
end end
## ##
@ -107,7 +107,7 @@ if CONFIG_AP_CODE_IN_CAR
makerule coreboot_apc.bin makerule coreboot_apc.bin
depends "coreboot_apc" depends "coreboot_apc"
action "$(OBJCOPY) -O binary $< $@" action "$(CONFIG_OBJCOPY) -O binary $< $@"
end end
makerule coreboot_apc.nrv2b makerule coreboot_apc.nrv2b
@ -129,14 +129,14 @@ makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
makerule coreboot makerule coreboot
depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" action "$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
action "$(CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm" action "$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"
end end
# the buildrom tool # the buildrom tool
makerule buildrom makerule buildrom
depends "$(TOP)/util/buildrom/buildrom.c" depends "$(TOP)/util/buildrom/buildrom.c"
action "$(HOSTCC) -o $@ $<" action "$(CONFIG_HOSTCC) -o $@ $<"
end end
# Force crt0.s (which has build time version code in it to rebuild every time) # Force crt0.s (which has build time version code in it to rebuild every time)
@ -149,7 +149,7 @@ end
# generate an assembly listing via -a switch. # generate an assembly listing via -a switch.
makerule crt0.o makerule crt0.o
depends "crt0.s" depends "crt0.s"
action "$(CC) -Wa,-acdlns -c $(CPU_OPT) -o $@ $< >crt0.disasm" action "$(CC) -Wa,-acdlns -c $(CONFIG_CPU_OPT) -o $@ $< >crt0.disasm"
end end
makerule etags makerule etags
@ -178,21 +178,21 @@ end
# be in a correct and valid state if it exists because the move is atomic. # be in a correct and valid state if it exists because the move is atomic.
makerule ../romcc makerule ../romcc
depends "$(TOP)/util/romcc/romcc.c" depends "$(TOP)/util/romcc/romcc.c"
action "$(HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile" action "$(CONFIG_HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile"
action "mv romcc.tmpfile $@" action "mv romcc.tmpfile $@"
end end
makerule build_opt_tbl makerule build_opt_tbl
depends "$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile" depends "$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile"
action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@"
end end
makerule option_table.h option_table.c makerule option_table.h option_table.c
depends "build_opt_tbl $(MAINBOARD)/cmos.layout" depends "build_opt_tbl $(CONFIG_MAINBOARD)/cmos.layout"
action "./build_opt_tbl --config $(MAINBOARD)/cmos.layout --header option_table.h --option option_table.c" action "./build_opt_tbl --config $(CONFIG_MAINBOARD)/cmos.layout --header option_table.h --option option_table.c"
end end
if HAVE_OPTION_TABLE if CONFIG_HAVE_OPTION_TABLE
object ./option_table.o object ./option_table.o
end end

254
src/config/Options.lb
View File

@ -61,12 +61,12 @@ define CONFIG_ARCH_X86
export always export always
comment "X86 is the default" comment "X86 is the default"
end end
define ARCH define CONFIG_ARCH
default "i386" default "i386"
export always export always
comment "Default architecture is i386, options are alpha and ppc" comment "Default architecture is i386, options are alpha and ppc"
end end
define HAVE_MOVNTI define CONFIG_HAVE_MOVNTI
default 0 default 0
export always export always
comment "This cpu supports the MOVNTI directive" comment "This cpu supports the MOVNTI directive"
@ -76,28 +76,28 @@ end
# Build options # Build options
############################################### ###############################################
define CROSS_COMPILE define CONFIG_CROSS_COMPILE
default "" default ""
export always export always
comment "Cross compiler prefix" comment "Cross compiler prefix"
end end
define CC define CC
default "$(CROSS_COMPILE)gcc" default "$(CONFIG_CROSS_COMPILE)gcc"
export always export always
comment "Target C Compiler" comment "Target C Compiler"
end end
define HOSTCC define CONFIG_HOSTCC
default "gcc" default "gcc"
export always export always
comment "Host C Compiler" comment "Host C Compiler"
end end
define CPU_OPT define CONFIG_CPU_OPT
default none default none
export used export used
comment "Additional per-cpu CFLAGS" comment "Additional per-cpu CFLAGS"
end end
define OBJCOPY define CONFIG_OBJCOPY
default "$(CROSS_COMPILE)objcopy --gap-fill 0xff" default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
export always export always
comment "Objcopy command" comment "Objcopy command"
end end
@ -186,143 +186,143 @@ end
# ROM image options # ROM image options
############################################### ###############################################
define HAVE_FALLBACK_BOOT define CONFIG_HAVE_FALLBACK_BOOT
format "%d" format "%d"
default 0 default 0
export always export always
comment "Set if fallback booting required" comment "Set if fallback booting required"
end end
define HAVE_FAILOVER_BOOT define CONFIG_HAVE_FAILOVER_BOOT
format "%d" format "%d"
default 0 default 0
export always export always
comment "Set if failover booting required" comment "Set if failover booting required"
end end
define USE_FALLBACK_IMAGE define CONFIG_USE_FALLBACK_IMAGE
format "%d" format "%d"
default 0 default 0
export used export used
comment "Set to build a fallback image" comment "Set to build a fallback image"
end end
define USE_FAILOVER_IMAGE define CONFIG_USE_FAILOVER_IMAGE
format "%d" format "%d"
default 0 default 0
export used export used
comment "Set to build a failover image" comment "Set to build a failover image"
end end
define FALLBACK_SIZE define CONFIG_FALLBACK_SIZE
default 65536 default 65536
format "0x%x" format "0x%x"
export used export used
comment "Default fallback image size" comment "Default fallback image size"
end end
define FAILOVER_SIZE define CONFIG_FAILOVER_SIZE
default 0 default 0
format "0x%x" format "0x%x"
export used export used
comment "Default failover image size" comment "Default failover image size"
end end
define ROM_SIZE define CONFIG_ROM_SIZE
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Size of your ROM" comment "Size of your ROM"
end end
define ROM_IMAGE_SIZE define CONFIG_ROM_IMAGE_SIZE
default 65535 default 65535
format "0x%x" format "0x%x"
export always export always
comment "Default image size" comment "Default image size"
end end
define ROM_SECTION_SIZE define CONFIG_ROM_SECTION_SIZE
default {FALLBACK_SIZE} default {CONFIG_FALLBACK_SIZE}
format "0x%x" format "0x%x"
export used export used
comment "Default rom section size" comment "Default rom section size"
end end
define ROM_SECTION_OFFSET define CONFIG_ROM_SECTION_OFFSET
default {ROM_SIZE - FALLBACK_SIZE} default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
format "0x%x" format "0x%x"
export used export used
comment "Default rom section offset" comment "Default rom section offset"
end end
define PAYLOAD_SIZE define CONFIG_PAYLOAD_SIZE
default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE} default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE}
format "0x%x" format "0x%x"
export always export always
comment "Default payload size" comment "Default payload size"
end end
define _ROMBASE define CONFIG_ROMBASE
default {PAYLOAD_SIZE} default {CONFIG_PAYLOAD_SIZE}
format "0x%x" format "0x%x"
export always export always
comment "Base address of coreboot in ROM" comment "Base address of coreboot in ROM"
end end
define _ROMSTART define CONFIG_ROMSTART
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Start address of coreboot in ROM" comment "Start address of coreboot in ROM"
end end
define _RESET define CONFIG_RESET
default {_ROMBASE} default {CONFIG_ROMBASE}
format "0x%x" format "0x%x"
export always export always
comment "Hardware reset vector address" comment "Hardware reset vector address"
end end
define _EXCEPTION_VECTORS define CONFIG_EXCEPTION_VECTORS
default {_ROMBASE+0x100} default {CONFIG_ROMBASE+0x100}
format "0x%x" format "0x%x"
export always export always
comment "Address of exception vector table" comment "Address of exception vector table"
end end
define STACK_SIZE define CONFIG_STACK_SIZE
default 0x2000 default 0x2000
format "0x%x" format "0x%x"
export always export always
comment "Default stack size" comment "Default stack size"
end end
define HEAP_SIZE define CONFIG_HEAP_SIZE
default 0x2000 default 0x2000
format "0x%x" format "0x%x"
export always export always
comment "Default heap size" comment "Default heap size"
end end
define _RAMBASE define CONFIG_RAMBASE
default none default none
format "0x%x" format "0x%x"
export always export always
comment "Base address of coreboot in RAM" comment "Base address of coreboot in RAM"
end end
define _RAMSTART define CONFIG_RAMSTART
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Start address of coreboot in RAM" comment "Start address of coreboot in RAM"
end end
define USE_DCACHE_RAM define CONFIG_USE_DCACHE_RAM
default 0 default 0
export always export always
comment "Use data cache as temporary RAM if possible" comment "Use data cache as temporary RAM if possible"
end end
define CAR_FAM10 define CONFIG_CAR_FAM10
default 0 default 0
export always export always
comment "AMD family 10 CAR requires additional setup" comment "AMD family 10 CAR requires additional setup"
end end
define DCACHE_RAM_BASE define CONFIG_DCACHE_RAM_BASE
default 0xc0000 default 0xc0000
format "0x%x" format "0x%x"
export always export always
comment "Base address of data cache when using it for temporary RAM" comment "Base address of data cache when using it for temporary RAM"
end end
define DCACHE_RAM_SIZE define CONFIG_DCACHE_RAM_SIZE
default 0x1000 default 0x1000
format "0x%x" format "0x%x"
export always export always
comment "Size of data cache when using it for temporary RAM" comment "Size of data cache when using it for temporary RAM"
end end
define DCACHE_RAM_GLOBAL_VAR_SIZE define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
default 0 default 0
format "0x%x" format "0x%x"
export always export always
@ -333,23 +333,23 @@ define CONFIG_AP_CODE_IN_CAR
export always export always
comment "will copy coreboot_apc to AP cache ane execute in AP" comment "will copy coreboot_apc to AP cache ane execute in AP"
end end
define MEM_TRAIN_SEQ define CONFIG_MEM_TRAIN_SEQ
default 0 default 0
export always export always
comment "0: three for in bsp, 1: on every core0, 2: one for on bsp" comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
end end
define WAIT_BEFORE_CPUS_INIT define CONFIG_WAIT_BEFORE_CPUS_INIT
default 0 default 0
export always export always
comment "execute cpus_ready_for_init if it is set to 1" comment "execute cpus_ready_for_init if it is set to 1"
end end
define XIP_ROM_BASE define CONFIG_XIP_ROM_BASE
default 0 default 0
format "0x%x" format "0x%x"
export used export used
comment "Start address of area to cache during coreboot execution directly from ROM" comment "Start address of area to cache during coreboot execution directly from ROM"
end end
define XIP_ROM_SIZE define CONFIG_XIP_ROM_SIZE
default 0 default 0
format "0x%x" format "0x%x"
export used export used
@ -372,14 +372,14 @@ define CONFIG_LB_MEM_TOPK
export always export always
comment "Kilobytes of memory to initialized before executing code from RAM" comment "Kilobytes of memory to initialized before executing code from RAM"
end end
define HAVE_OPTION_TABLE define CONFIG_HAVE_OPTION_TABLE
default 0 default 0
export always export always
comment "Export CMOS option table" comment "Export CMOS option table"
end end
define USE_OPTION_TABLE define CONFIG_USE_OPTION_TABLE
format "%d" format "%d"
default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE} default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
export always export always
comment "Use option table" comment "Use option table"
end end
@ -387,19 +387,19 @@ end
############################################### ###############################################
# CMOS variable options # CMOS variable options
############################################### ###############################################
define LB_CKS_RANGE_START define CONFIG_LB_CKS_RANGE_START
default 49 default 49
format "%d" format "%d"
export always export always
comment "First CMOS byte to use for coreboot options" comment "First CMOS byte to use for coreboot options"
end end
define LB_CKS_RANGE_END define CONFIG_LB_CKS_RANGE_END
default 125 default 125
format "%d" format "%d"
export always export always
comment "Last CMOS byte to use for coreboot options" comment "Last CMOS byte to use for coreboot options"
end end
define LB_CKS_LOC define CONFIG_LB_CKS_LOC
default 126 default 126
format "%d" format "%d"
export always export always
@ -411,8 +411,8 @@ end
# Build targets # Build targets
############################################### ###############################################
define CRT0 define CONFIG_CRT0
default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb" default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
export always export always
comment "Main initialization target" comment "Main initialization target"
end end
@ -421,7 +421,7 @@ end
# Debugging/Logging options # Debugging/Logging options
############################################### ###############################################
define DEBUG define CONFIG_DEBUG
default 0 default 0
export always export always
comment "Enable x86emu debugging code" comment "Enable x86emu debugging code"
@ -466,12 +466,12 @@ define CONFIG_USBDEBUG_DIRECT
export always export always
comment "Log messages to ehci debug port console" comment "Log messages to ehci debug port console"
end end
define DEFAULT_CONSOLE_LOGLEVEL define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
default 7 default 7
export always export always
comment "Console will log at this level unless changed" comment "Console will log at this level unless changed"
end end
define MAXIMUM_CONSOLE_LOGLEVEL define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
default 8 default 8
export always export always
comment "Error messages up to this level can be printed" comment "Error messages up to this level can be printed"
@ -481,29 +481,29 @@ define CONFIG_SERIAL_POST
export always export always
comment "Enable SERIAL POST codes" comment "Enable SERIAL POST codes"
end end
define NO_POST define CONFIG_NO_POST
default none default none
export used export used
comment "Disable POST codes" comment "Disable POST codes"
end end
define TTYS0_BASE define CONFIG_TTYS0_BASE
default 0x3f8 default 0x3f8
format "0x%x" format "0x%x"
export always export always
comment "Base address for 8250 uart for the serial console" comment "Base address for 8250 uart for the serial console"
end end
define TTYS0_BAUD define CONFIG_TTYS0_BAUD
default 115200 default 115200
export always export always
comment "Default baud rate for serial console" comment "Default baud rate for serial console"
end end
define TTYS0_DIV define CONFIG_TTYS0_DIV
default none default none
format "%d" format "%d"
export used export used
comment "Allow UART divisor to be set explicitly" comment "Allow UART divisor to be set explicitly"
end end
define TTYS0_LCS define CONFIG_TTYS0_LCS
default 0x3 default 0x3
format "0x%x" format "0x%x"
export always export always
@ -515,7 +515,7 @@ define CONFIG_USE_PRINTK_IN_CAR
export always export always
comment "use printk instead of print in CAR stage code" comment "use printk instead of print in CAR stage code"
end end
define ASSEMBLER_DEBUG define CONFIG_ASSEMBLER_DEBUG
default 0 default 0
export always export always
comment "Create disassembly files for debugging" comment "Create disassembly files for debugging"
@ -525,35 +525,35 @@ end
# Mainboard options # Mainboard options
############################################### ###############################################
define MAINBOARD define CONFIG_MAINBOARD
default "Mainboard_not_set" default "Mainboard_not_set"
export always export always
comment "Mainboard name" comment "Mainboard name"
end end
define MAINBOARD_PART_NUMBER define CONFIG_MAINBOARD_PART_NUMBER
default "Part_number_not_set" default "Part_number_not_set"
export always export always
format "\"%s\"" format "\"%s\""
comment "Part number of mainboard" comment "Part number of mainboard"
end end
define MAINBOARD_VENDOR define CONFIG_MAINBOARD_VENDOR
default "Vendor_not_set" default "Vendor_not_set"
export always export always
format "\"%s\"" format "\"%s\""
comment "Vendor of mainboard" comment "Vendor of mainboard"
end end
define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
default 0 default 0
export always export always
comment "PCI Vendor ID of mainboard manufacturer" comment "PCI Vendor ID of mainboard manufacturer"
end end
define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
default 0 default 0
format "0x%x" format "0x%x"
export always export always
comment "PCI susbsystem device id assigned my mainboard manufacturer" comment "PCI susbsystem device id assigned my mainboard manufacturer"
end end
define MAINBOARD_POWER_ON_AFTER_POWER_FAIL define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
default none default none
export used export used
comment "Default power on after power fail setting" comment "Default power on after power fail setting"
@ -597,27 +597,27 @@ define CONFIG_AP_IN_SIPI_WAIT
export always export always
comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)" comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
end end
define HAVE_MP_TABLE define CONFIG_HAVE_MP_TABLE
default none default none
export used export used
comment "Define to build an MP table" comment "Define to build an MP table"
end end
define SERIAL_CPU_INIT define CONFIG_SERIAL_CPU_INIT
default 1 default 1
export always export always
comment "Serialize CPU init" comment "Serialize CPU init"
end end
define APIC_ID_OFFSET define CONFIG_APIC_ID_OFFSET
default 0 default 0
export always export always
comment "We need to share this value between cache_as_ram_auto.c and northbridge.c" comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
end end
define ENABLE_APIC_EXT_ID define CONFIG_ENABLE_APIC_EXT_ID
default 0 default 0
export always export always
comment "Enable APIC ext id mode 8 bit" comment "Enable APIC ext id mode 8 bit"
end end
define LIFT_BSP_APIC_ID define CONFIG_LIFT_BSP_APIC_ID
default 0 default 0
export always export always
comment "decide if we lift bsp apic id while ap apic id" comment "decide if we lift bsp apic id while ap apic id"
@ -642,7 +642,7 @@ define CONFIG_ROM_PAYLOAD
comment "Boot image is located in ROM" comment "Boot image is located in ROM"
end end
define CONFIG_ROM_PAYLOAD_START define CONFIG_ROM_PAYLOAD_START
default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1} default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1}
format "0x%x" format "0x%x"
export always export always
comment "ROM stream start location" comment "ROM stream start location"
@ -692,19 +692,19 @@ define CONFIG_CBFS
export always export always
comment "The new CBFS file system" comment "The new CBFS file system"
end end
define AUTOBOOT_DELAY define CONFIG_AUTOBOOT_DELAY
default 2 default 2
export always export always
comment "Delay (in seconds) before autobooting" comment "Delay (in seconds) before autobooting"
end end
define AUTOBOOT_CMDLINE define CONFIG_AUTOBOOT_CMDLINE
default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200" default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
export always export always
format "\"%s\"" format "\"%s\""
comment "Default command line when autobooting" comment "Default command line when autobooting"
end end
define USE_WATCHDOG_ON_BOOT define CONFIG_USE_WATCHDOG_ON_BOOT
default 0 default 0
export always export always
comment "Use the watchdog on booting" comment "Use the watchdog on booting"
@ -744,17 +744,17 @@ end
# IRQ options # IRQ options
############################################### ###############################################
define HAVE_PIRQ_TABLE define CONFIG_HAVE_PIRQ_TABLE
default none default none
export used export used
comment "Define if we have a PIRQ table" comment "Define if we have a PIRQ table"
end end
define PIRQ_ROUTE define CONFIG_PIRQ_ROUTE
default 0 default 0
export always export always
comment "Define if we have a PIRQ table and want routing IRQs" comment "Define if we have a PIRQ table and want routing IRQs"
end end
define IRQ_SLOT_COUNT define CONFIG_IRQ_SLOT_COUNT
default none default none
export used export used
comment "Number of IRQ slots" comment "Number of IRQ slots"
@ -779,17 +779,17 @@ define CONFIG_IDE
export always export always
comment "Define to include IDE support" comment "Define to include IDE support"
end end
define IDE_BOOT_DRIVE define CONFIG_IDE_BOOT_DRIVE
default 0 default 0
export always export always
comment "Disk number of boot drive" comment "Disk number of boot drive"
end end
define IDE_SWAB define CONFIG_IDE_SWAB
default none default none
export used export used
comment "Swap bytes when reading from IDE device" comment "Swap bytes when reading from IDE device"
end end
define IDE_OFFSET define CONFIG_IDE_OFFSET
default 0 default 0
export always export always
comment "Sector at which to start searching for boot image" comment "Sector at which to start searching for boot image"
@ -799,49 +799,49 @@ end
# Options for memory mapped I/O # Options for memory mapped I/O
############################################### ###############################################
define PCI_IO_CFG_EXT define CONFIG_PCI_IO_CFG_EXT
default 0 default 0
export always export always
comment "allow 4K register space via io CFG port" comment "allow 4K register space via io CFG port"
end end
define PCIC0_CFGADDR define CONFIG_PCIC0_CFGADDR
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Address of PCI Configuration Address Register" comment "Address of PCI Configuration Address Register"
end end
define PCIC0_CFGDATA define CONFIG_PCIC0_CFGDATA
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Address of PCI Configuration Data Register" comment "Address of PCI Configuration Data Register"
end end
define ISA_IO_BASE define CONFIG_ISA_IO_BASE
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Base address of PCI/ISA I/O address range" comment "Base address of PCI/ISA I/O address range"
end end
define ISA_MEM_BASE define CONFIG_ISA_MEM_BASE
default none default none
format "0x%x" format "0x%x"
export used export used
comment "Base address of PCI/ISA memory address range" comment "Base address of PCI/ISA memory address range"
end end
define PNP_CFGADDR define CONFIG_PNP_CFGADDR
default none default none
format "0x%x" format "0x%x"
export used export used
comment "PNP Configuration Address Register offset" comment "PNP Configuration Address Register offset"
end end
define PNP_CFGDATA define CONFIG_PNP_CFGDATA
default none default none
format "0x%x" format "0x%x"
export used export used
comment "PNP Configuration Data Register offset" comment "PNP Configuration Data Register offset"
end end
define _IO_BASE define CONFIG_IO_BASE
default none default none
format "0x%x" format "0x%x"
export used export used
@ -852,7 +852,7 @@ end
# Options for embedded systems # Options for embedded systems
############################################### ###############################################
define EMBEDDED_RAM_SIZE define CONFIG_EMBEDDED_RAM_SIZE
default none default none
export used export used
comment "Embedded boards generally have fixed RAM size" comment "Embedded boards generally have fixed RAM size"
@ -868,27 +868,27 @@ define CONFIG_GDB_STUB
comment "Compile in gdb stub support?" comment "Compile in gdb stub support?"
end end
define HAVE_INIT_TIMER define CONFIG_HAVE_INIT_TIMER
default 0 default 0
export always export always
comment "Have a init_timer function" comment "Have a init_timer function"
end end
define HAVE_HARD_RESET define CONFIG_HAVE_HARD_RESET
default none default none
export used export used
comment "Have hard reset" comment "Have hard reset"
end end
define HAVE_SMI_HANDLER define CONFIG_HAVE_SMI_HANDLER
default 0 default 0
export always export always
comment "Set, if the board needs an SMI handler" comment "Set, if the board needs an SMI handler"
end end
define MEMORY_HOLE define CONFIG_MEMORY_HOLE
default none default none
export used export used
comment "Set to deal with memory hole" comment "Set to deal with memory hole"
end end
define MAX_REBOOT_CNT define CONFIG_MAX_REBOOT_CNT
default 3 default 3
export always export always
comment "Set maximum reboots" comment "Set maximum reboots"
@ -898,7 +898,7 @@ end
# Misc device options # Misc device options
############################################### ###############################################
define HAVE_FANCTL define CONFIG_HAVE_FANCTL
default 0 default 0
export used export used
comment "Include board specific FAN control initialization" comment "Include board specific FAN control initialization"
@ -908,7 +908,7 @@ define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
export used export used
comment "Use timer2 to callibrate the x86 time stamp counter" comment "Use timer2 to callibrate the x86 time stamp counter"
end end
define INTEL_PPRO_MTRR define CONFIG_INTEL_PPRO_MTRR
default none default none
export used export used
comment "" comment ""
@ -923,93 +923,93 @@ define CONFIG_UDELAY_IO
export used export used
comment "Implement udelay with x86 io registers" comment "Implement udelay with x86 io registers"
end end
define FAKE_SPDROM define CONFIG_FAKE_SPDROM
default 0 default 0
export always export always
comment "Use this to fake spd rom values" comment "Use this to fake spd rom values"
end end
define HAVE_ACPI_TABLES define CONFIG_HAVE_ACPI_TABLES
default 0 default 0
export always export always
comment "Define to build ACPI tables" comment "Define to build ACPI tables"
end end
define HAVE_ACPI_RESUME define CONFIG_HAVE_ACPI_RESUME
default 0 default 0
export always export always
comment "Define to build ACPI with resume support" comment "Define to build ACPI with resume support"
end end
define ACPI_SSDTX_NUM define CONFIG_ACPI_SSDTX_NUM
default 0 default 0
export always export always
comment "extra ssdt num for PCI Device" comment "extra ssdt num for PCI Device"
end end
define AGP_APERTURE_SIZE define CONFIG_AGP_APERTURE_SIZE
default none default none
export used export used
format "0x%x" format "0x%x"
comment "AGP graphics virtual memory aperture size" comment "AGP graphics virtual memory aperture size"
end end
define HT_CHAIN_UNITID_BASE define CONFIG_HT_CHAIN_UNITID_BASE
default 1 default 1
export always export always
comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
end end
define HT_CHAIN_END_UNITID_BASE define CONFIG_HT_CHAIN_END_UNITID_BASE
default 0x20 default 0x20
export always export always
comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0" comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
end end
define SB_HT_CHAIN_UNITID_OFFSET_ONLY define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
default 1 default 1
export always export always
comment "this will decided if only offset SB hypertransport chain" comment "this will decided if only offset SB hypertransport chain"
end end
define SB_HT_CHAIN_ON_BUS0 define CONFIG_SB_HT_CHAIN_ON_BUS0
default 0 default 0
export always export always
comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
end end
define PCI_BUS_SEGN_BITS define CONFIG_PCI_BUS_SEGN_BITS
default 0 default 0
export always export always
comment "It could be 0, 1, 2, 3 and 4 only" comment "It could be 0, 1, 2, 3 and 4 only"
end end
define MMCONF_SUPPORT define CONFIG_MMCONF_SUPPORT
default 0 default 0
export always export always
comment "enable mmconfig for pci conf" comment "enable mmconfig for pci conf"
end end
define MMCONF_SUPPORT_DEFAULT define CONFIG_MMCONF_SUPPORT_DEFAULT
default 0 default 0
export always export always
comment "enable mmconfig for pci conf" comment "enable mmconfig for pci conf"
end end
define MMCONF_BASE_ADDRESS define CONFIG_MMCONF_BASE_ADDRESS
default none default none
format "0x%x" format "0x%x"
export used export used
comment "enable mmconfig base address" comment "enable mmconfig base address"
end end
define HW_MEM_HOLE_SIZEK define CONFIG_HW_MEM_HOLE_SIZEK
default 0 default 0
export always export always
comment "Opteron E0 later memory hole size in K, 0 mean disable" comment "Opteron E0 later memory hole size in K, 0 mean disable"
end end
define HW_MEM_HOLE_SIZE_AUTO_INC define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
default 0 default 0
export always export always
comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek" comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
@ -1021,62 +1021,62 @@ define CONFIG_VAR_MTRR_HOLE
comment "using hole in MTRR instead of increasing method" comment "using hole in MTRR instead of increasing method"
end end
define K8_HT_FREQ_1G_SUPPORT define CONFIG_K8_HT_FREQ_1G_SUPPORT
default 0 default 0
export always export always
comment "Optern E0 later could support 1G HT, but still depends MB design" comment "Optern E0 later could support 1G HT, but still depends MB design"
end end
define K8_REV_F_SUPPORT define CONFIG_K8_REV_F_SUPPORT
default 0 default 0
export always export always
comment "Opteron Rev F (DDR2) support" comment "Opteron Rev F (DDR2) support"
end end
define CBB define CONFIG_CBB
default 0 default 0
export always export always
comment "Opteron cpu bus num base" comment "Opteron cpu bus num base"
end end
define CDB define CONFIG_CDB
default 0x18 default 0x18
export always export always
comment "Opteron cpu device num base" comment "Opteron cpu device num base"
end end
define HT3_SUPPORT define CONFIG_HT3_SUPPORT
default 0 default 0
export always export always
comment "Hypertransport 3 support, include ac HT and unganged sublink feature" comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
end end
define EXT_RT_TBL_SUPPORT define CONFIG_EXT_RT_TBL_SUPPORT
default 0 default 0
export always export always
comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8" comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
end end
define EXT_CONF_SUPPORT define CONFIG_EXT_CONF_SUPPORT
default 0 default 0
export always export always
comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4" comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
end end
define DIMM_SUPPORT define CONFIG_DIMM_SUPPORT
default 0x0108 default 0x0108
format "0x%x" format "0x%x"
export always export always
comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg" comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
end end
define CPU_SOCKET_TYPE define CONFIG_CPU_SOCKET_TYPE
default 0x10 default 0x10
export always export always
comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
end end
define CPU_ADDR_BITS define CONFIG_CPU_ADDR_BITS
default 36 default 36
export always export always
comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48" comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
@ -1137,14 +1137,14 @@ define CONFIG_AMDMCT
comment "use AMD MCT to init RAM instead of native code" comment "use AMD MCT to init RAM instead of native code"
end end
define AMD_UCODE_PATCH_FILE define CONFIG_AMD_UCODE_PATCH_FILE
default none default none
export used export used
format "\"%s\"" format "\"%s\""
comment "name of the microcode patch file" comment "name of the microcode patch file"
end end
define K8_MEM_BANK_B_ONLY define CONFIG_K8_MEM_BANK_B_ONLY
default 0 default 0
export always export always
comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert." comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
@ -1162,19 +1162,19 @@ define CONFIG_GFXUMA
comment "GFX UMA" comment "GFX UMA"
end end
define HAVE_MAINBOARD_RESOURCES define CONFIG_HAVE_MAINBOARD_RESOURCES
default 0 default 0
export always export always
comment "Enable if the mainboard/chipset requires extra entries in the memory map" comment "Enable if the mainboard/chipset requires extra entries in the memory map"
end end
define HAVE_LOW_TABLES define CONFIG_HAVE_LOW_TABLES
default 1 default 1
export always export always
comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte" comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
end end
define HAVE_HIGH_TABLES define CONFIG_HAVE_HIGH_TABLES
default 0 default 0
export always export always
comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory" comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"

6
src/config/coreboot_apc.ld
View File

@ -1,7 +1,7 @@
/* /*
* Memory map: * Memory map:
* *
* DCACHE_RAM_BASE * CONFIG_DCACHE_RAM_BASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
@ -28,7 +28,7 @@ ENTRY(_start)
SECTIONS SECTIONS
{ {
. = DCACHE_RAM_BASE; . = CONFIG_DCACHE_RAM_BASE;
/* /*
* First we place the code and read only data (typically const declared). * First we place the code and read only data (typically const declared).
* This get placed in rom. * This get placed in rom.
@ -90,7 +90,7 @@ SECTIONS
_ram_seg = _text; _ram_seg = _text;
_eram_seg = _eheap; _eram_seg = _eheap;
_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
/DISCARD/ : { /DISCARD/ : {
*(.comment) *(.comment)

14
src/config/coreboot_ram.ld
View File

@ -1,7 +1,7 @@
/* /*
* Memory map: * Memory map:
* *
* _RAMBASE * CONFIG_RAMBASE
* : data segment * : data segment
* : bss segment * : bss segment
* : heap * : heap
@ -27,7 +27,7 @@ ENTRY(_start)
SECTIONS SECTIONS
{ {
. = _RAMBASE; . = CONFIG_RAMBASE;
/* /*
* First we place the code and read only data (typically const declared). * First we place the code and read only data (typically const declared).
* This get placed in rom. * This get placed in rom.
@ -99,18 +99,18 @@ SECTIONS
} }
_ebss = .; _ebss = .;
_end = .; _end = .;
. = ALIGN(STACK_SIZE); . = ALIGN(CONFIG_STACK_SIZE);
_stack = .; _stack = .;
.stack . : { .stack . : {
/* Reserve a stack for each possible cpu */ /* Reserve a stack for each possible cpu */
/* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/ /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/
. = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? STACK_SIZE : (CONFIG_MAX_CPUS*STACK_SIZE); . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
} }
_estack = .; _estack = .;
_heap = .; _heap = .;
.heap . : { .heap . : {
/* Reserve HEAP_SIZE bytes for the heap */ /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = HEAP_SIZE ; . = CONFIG_HEAP_SIZE ;
. = ALIGN(4); . = ALIGN(4);
} }
_eheap = .; _eheap = .;
@ -122,7 +122,7 @@ SECTIONS
_bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK");
_bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M"); _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set CONFIG_RAMBASE more than 1M");
/DISCARD/ : { /DISCARD/ : {
*(.comment) *(.comment)

40
src/config/failovercalculation.lb
View File

@ -2,20 +2,20 @@
## Compute the location and size of where this firmware image ## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip. ## (coreboot plus bootloader) will live in the boot rom chip.
## ##
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE default CONFIG_ROM_SECTION_SIZE = CONFIG_FAILOVER_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FAILOVER_SIZE )
else else
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
else else
if CONFIG_CBFS if CONFIG_CBFS
default ROM_SECTION_SIZE = FALLBACK_SIZE default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
else else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0 default CONFIG_ROM_SECTION_OFFSET = 0
end end
end end
end end
@ -24,29 +24,29 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
## ##
## Compute where this copy of coreboot will start in the boot rom ## Compute where this copy of coreboot will start in the boot rom
## ##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
## ##
## Compute a range of ROM that can cached to speed up coreboot, ## Compute a range of ROM that can cached to speed up coreboot,
## execution speed. ## execution speed.
## ##
## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb ## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
## ##
if USE_FAILOVER_IMAGE if CONFIG_USE_FAILOVER_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
else else
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE)
else else
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
end end
end end

26
src/config/nofailovercalculation.lb
View File

@ -2,16 +2,16 @@
## Compute the location and size of where this firmware image ## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip. ## (coreboot plus bootloader) will live in the boot rom chip.
## ##
if USE_FALLBACK_IMAGE if CONFIG_USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
else else
if CONFIG_CBFS if CONFIG_CBFS
default ROM_SECTION_SIZE = FALLBACK_SIZE default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE ) default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
else else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0 default CONFIG_ROM_SECTION_OFFSET = 0
end end
end end
@ -19,19 +19,19 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
## ##
## Compute where this copy of coreboot will start in the boot rom ## Compute where this copy of coreboot will start in the boot rom
## ##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
## ##
## Compute a range of ROM that can cached to speed up coreboot, ## Compute a range of ROM that can cached to speed up coreboot,
## execution speed. ## execution speed.
## ##
## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb ## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
## ##
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )

4
src/console/console.c
View File

@ -15,7 +15,7 @@ void console_init(void)
{ {
struct console_driver *driver; struct console_driver *driver;
if(get_option(&console_loglevel, "debug_level")) if(get_option(&console_loglevel, "debug_level"))
console_loglevel=DEFAULT_CONSOLE_LOGLEVEL; console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
for(driver = console_drivers; driver < econsole_drivers; driver++) { for(driver = console_drivers; driver < econsole_drivers; driver++) {
if (!driver->init) if (!driver->init)
@ -83,7 +83,7 @@ int console_tst_byte(void)
*/ */
void post_code(uint8_t value) void post_code(uint8_t value)
{ {
#if !defined(NO_POST) || NO_POST==0 #if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
#if CONFIG_SERIAL_POST==1 #if CONFIG_SERIAL_POST==1
printk_emerg("POST: 0x%02x\n", value); printk_emerg("POST: 0x%02x\n", value);
#endif #endif

4
src/console/printk.c
View File

@ -17,10 +17,10 @@
/* Keep together for sysctl support */ /* Keep together for sysctl support */
int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL; int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL;
int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
void display(char*); void display(char*);
extern int vtxprintf(void (*)(unsigned char), const char *, va_list); extern int vtxprintf(void (*)(unsigned char), const char *, va_list);

30
src/console/uart8250_console.c
View File

@ -3,54 +3,54 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
/* Base Address */ /* Base Address */
#ifndef TTYS0_BASE #ifndef CONFIG_TTYS0_BASE
#define TTYS0_BASE 0x3f8 #define CONFIG_TTYS0_BASE 0x3f8
#endif #endif
#ifndef TTYS0_BAUD #ifndef CONFIG_TTYS0_BAUD
#define TTYS0_BAUD 115200 #define CONFIG_TTYS0_BAUD 115200
#endif #endif
#ifndef TTYS0_DIV #ifndef CONFIG_TTYS0_DIV
#if ((115200%TTYS0_BAUD) != 0) #if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate #error Bad ttys0 baud rate
#endif #endif
#define TTYS0_DIV (115200/TTYS0_BAUD) #define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif #endif
/* Line Control Settings */ /* Line Control Settings */
#ifndef TTYS0_LCS #ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */ /* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3 #define CONFIG_TTYS0_LCS 0x3
#endif #endif
#define UART_LCS TTYS0_LCS #define UART_LCS CONFIG_TTYS0_LCS
static void ttyS0_init(void) static void ttyS0_init(void)
{ {
static const unsigned char div[8]={1,2,3,6,12,24,48,96}; static const unsigned char div[8]={1,2,3,6,12,24,48,96};
int b_index=0; int b_index=0;
unsigned int divisor=TTYS0_DIV; unsigned int divisor=CONFIG_TTYS0_DIV;
if(get_option(&b_index,"baud_rate")==0) { if(get_option(&b_index,"baud_rate")==0) {
divisor=div[b_index]; divisor=div[b_index];
} }
uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS); uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS);
} }
static void ttyS0_tx_byte(unsigned char data) static void ttyS0_tx_byte(unsigned char data)
{ {
uart8250_tx_byte(TTYS0_BASE, data); uart8250_tx_byte(CONFIG_TTYS0_BASE, data);
} }
static unsigned char ttyS0_rx_byte(void) static unsigned char ttyS0_rx_byte(void)
{ {
return uart8250_rx_byte(TTYS0_BASE); return uart8250_rx_byte(CONFIG_TTYS0_BASE);
} }
static int ttyS0_tst_byte(void) static int ttyS0_tst_byte(void)
{ {
return uart8250_can_rx_byte(TTYS0_BASE); return uart8250_can_rx_byte(CONFIG_TTYS0_BASE);
} }
static const struct console_driver uart8250_console __console = { static const struct console_driver uart8250_console __console = {

30
src/cpu/amd/car/cache_as_ram.inc
View File

@ -18,13 +18,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize) #define CacheBase (0xd0000 - CacheSize)
/* leave some space for global variable to pass to RAM stage */ /* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
/* for CAR_FAM10 */ /* for CONFIG_CAR_FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */ #define CacheSizeAPStack 0x400 /* 1K */
#define MSR_FAM10 0xC001102A #define MSR_FAM10 0xC001102A
@ -72,7 +72,7 @@ cache_as_ram_setup:
cvtsd2si %xmm3, %ebx cvtsd2si %xmm3, %ebx
/* hope we can skip the double set for normal part */ /* hope we can skip the double set for normal part */
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* check if cpu_init_detected */ /* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
@ -248,10 +248,10 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx xorl %edx, %edx
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr wrmsr
#endif /* USE_FAILOVER_IMAGE == 1*/ #endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30),%eax orl $(1 << 30),%eax
@ -259,25 +259,25 @@ clear_fixed_var_mtrr_out:
#endif #endif
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place /* enable write base caching so we can do execute in place
* on the flash rom. * on the flash rom.
*/ */
movl $0x202, %ecx movl $0x202, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $0x203, %ecx movl $0x203, %ecx
movl $0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */ movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
jmp_if_k8(wbcache_post_fam10_setup) jmp_if_k8(wbcache_post_fam10_setup)
movl $0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */ movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
wbcache_post_fam10_setup: wbcache_post_fam10_setup:
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
@ -313,7 +313,7 @@ fam10_end_part1:
movb $0xA2, %al movb $0xA2, %al
outb %al, $0x80 outb %al, $0x80
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Read the range with lodsl*/ /* Read the range with lodsl*/
cld cld
movl $CacheBase, %esi movl $CacheBase, %esi
@ -325,7 +325,7 @@ fam10_end_part1:
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
#endif /*USE_FAILOVER_IMAGE == 1*/ #endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */ /* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl $(CacheBase + CacheSize - GlobalVarSize), %eax

6
src/cpu/amd/car/clear_init_ram.c
View File

@ -7,11 +7,11 @@ static void __attribute__((noinline)) clear_init_ram(void)
// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
// so noline clear_init_ram // so noline clear_init_ram
#if HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else #else
clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE));
#endif #endif
} }

4
src/cpu/amd/car/copy_and_run.c
View File

@ -8,7 +8,7 @@ void cbfs_and_run_core(char*, unsigned ebp);
static void copy_and_run(void) static void copy_and_run(void)
{ {
# if USE_FALLBACK_IMAGE == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_ram", 0); cbfs_and_run_core("fallback/coreboot_ram", 0);
# else # else
cbfs_and_run_core("normal/coreboot_ram", 0); cbfs_and_run_core("normal/coreboot_ram", 0);
@ -19,7 +19,7 @@ static void copy_and_run(void)
static void copy_and_run_ap_code_in_car(unsigned ret_addr) static void copy_and_run_ap_code_in_car(unsigned ret_addr)
{ {
# if USE_FALLBACK_IMAGE == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_apc", ret_addr); cbfs_and_run_core("fallback/coreboot_apc", ret_addr);
# else # else
cbfs_and_run_core("normal/coreboot_apc", ret_addr); cbfs_and_run_core("normal/coreboot_apc", ret_addr);

2
src/cpu/amd/car/disable_cache_as_ram.c
View File

@ -16,7 +16,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
"xorl %edx, %edx\n\t" "xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t" "xorl %eax, %eax\n\t"
"wrmsr\n\t" "wrmsr\n\t"
#if DCACHE_RAM_SIZE > 0x8000 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t" "wrmsr\n\t"
#endif #endif

18
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -64,7 +64,7 @@ static void post_cache_as_ram(void)
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
/* from here don't store more data in CAR */ /* from here don't store more data in CAR */
@ -76,14 +76,14 @@ static void post_cache_as_ram(void)
); );
#endif #endif
memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
__asm__ volatile ( __asm__ volatile (
/* set new esp */ /* before _RAMBASE */ /* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t" "subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t" "subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
#if 0 #if 0
__asm__ volatile ( __asm__ volatile (
@ -102,18 +102,18 @@ static void post_cache_as_ram(void)
disable_cache_as_ram_bsp(); disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: "); print_debug("Clearing initial memory region: ");
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
print_debug("Done\r\n"); print_debug("Done\r\n");
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
#ifndef MEM_TRAIN_SEQ #ifndef CONFIG_MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0 #define CONFIG_MEM_TRAIN_SEQ 0
#endif #endif
set_sysinfo_in_ram(1); // So other core0 could start to train mem set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained // wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c

2
src/cpu/amd/dualcore/amd_sibling.c
View File

@ -110,7 +110,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) { if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID // We need to enable APIC EXT ID
printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n"); printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(nodes); enable_apic_ext_id(nodes);
} }

16
src/cpu/amd/dualcore/dualcore.c
View File

@ -19,7 +19,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
#if SET_NB_CFG_54 == 1 #if SET_NB_CFG_54 == 1
static inline uint8_t set_apicid_cpuid_lo(void) static inline uint8_t set_apicid_cpuid_lo(void)
{ {
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif #endif
@ -56,7 +56,7 @@ static inline void start_other_cores(void)
unsigned nodes; unsigned nodes;
unsigned nodeid; unsigned nodeid;
if (HAVE_OPTION_TABLE && if (CONFIG_HAVE_OPTION_TABLE &&
read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) {
return; // disable dual_core return; // disable dual_core
} }
@ -70,7 +70,7 @@ static inline void start_other_cores(void)
} }
} }
#if USE_DCACHE_RAM == 0 #if CONFIG_USE_DCACHE_RAM == 0
static void do_k8_init_and_stop_secondaries(void) static void do_k8_init_and_stop_secondaries(void)
{ {
struct node_core_id id; struct node_core_id id;
@ -106,22 +106,22 @@ static void do_k8_init_and_stop_secondaries(void)
pci_write_config32(dev_f0, 0x68, val); pci_write_config32(dev_f0, 0x68, val);
/* Set the lapicid */ /* Set the lapicid */
#if (ENABLE_APIC_EXT_ID == 1) #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
unsigned initial_apicid = get_initial_apicid(); unsigned initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0 #if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp if( initial_apicid != 0 ) // other than bsp
#endif #endif
{ {
/* use initial apic id to lift it */ /* use initial apic id to lift it */
uint32_t dword = lapic_read(LAPIC_ID); uint32_t dword = lapic_read(LAPIC_ID);
dword &= ~(0xff<<24); dword &= ~(0xff<<24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
lapic_write(LAPIC_ID, dword); lapic_write(LAPIC_ID, dword);
} }
#if LIFT_BSP_APIC_ID == 1 #if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET; bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif #endif
#endif #endif

12
src/cpu/amd/model_10xxx/Config.lb
View File

@ -17,13 +17,13 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
uses HAVE_INIT_TIMER uses CONFIG_HAVE_INIT_TIMER
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
uses CPU_ADDR_BITS uses CONFIG_CPU_ADDR_BITS
default HAVE_INIT_TIMER=1 default CONFIG_HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
default CPU_ADDR_BITS=48 default CONFIG_CPU_ADDR_BITS=48
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/fpu dir /cpu/x86/fpu
dir /cpu/x86/mmx dir /cpu/x86/mmx

36
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -19,7 +19,7 @@
#include "defaults.h" #include "defaults.h"
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef FAM10_SET_FIDVID #ifndef FAM10_SET_FIDVID
#define FAM10_SET_FIDVID 1 #define FAM10_SET_FIDVID 1
#endif #endif
@ -58,13 +58,13 @@ static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid); static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void); void cpuSetAMDMSR(void);
#if PCI_IO_CFG_EXT == 1 #if CONFIG_PCI_IO_CFG_EXT == 1
static void set_EnableCf8ExtCfg(void) static void set_EnableCf8ExtCfg(void)
{ {
// set the NB_CFG[46]=1; // set the NB_CFG[46]=1;
msr_t msr; msr_t msr;
msr = rdmsr(NB_CFG_MSR); msr = rdmsr(NB_CFG_MSR);
// EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
msr.hi |= (1<<(46-32)); msr.hi |= (1<<(46-32));
wrmsr(NB_CFG_MSR, msr); wrmsr(NB_CFG_MSR, msr);
} }
@ -80,12 +80,12 @@ static void set_EnableCf8ExtCfg(void) { }
static void set_pci_mmio_conf_reg(void) static void set_pci_mmio_conf_reg(void)
{ {
#if MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
msr_t msr; msr_t msr;
msr = rdmsr(0xc0010058); msr = rdmsr(0xc0010058);
msr.lo &= ~(0xfff00000 | (0xf << 2)); msr.lo &= ~(0xfff00000 | (0xf << 2));
// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0); msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
msr.hi &= ~(0x0000ffff); msr.hi &= ~(0x0000ffff);
msr.hi |= (PCI_MMIO_BASE >> (32-8)); msr.hi |= (PCI_MMIO_BASE >> (32-8));
wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
@ -168,11 +168,11 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range,
for (j = jstart; j <= jend; j++) { for (j = jstart; j <= jend; j++) {
ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64); ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
#if LIFT_BSP_APIC_ID == 0 #if CONFIG_LIFT_BSP_APIC_ID == 0
if( (i != 0) || (j != 0)) /* except bsp */ if( (i != 0) || (j != 0)) /* except bsp */
#endif #endif
ap_apicid += APIC_ID_OFFSET; ap_apicid += CONFIG_APIC_ID_OFFSET;
#endif #endif
if(ap_apicid == bsp_apicid) continue; if(ap_apicid == bsp_apicid) continue;
@ -307,8 +307,8 @@ static void STOP_CAR_AND_CPU()
} }
#ifndef MEM_TRAIN_SEQ #ifndef CONFIG_MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0 #define CONFIG_MEM_TRAIN_SEQ 0
#endif #endif
#if RAMINIT_SYSINFO == 1 #if RAMINIT_SYSINFO == 1
@ -337,7 +337,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if(id.coreid == 0) { if(id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */ set_apicid_cpuid_lo(); /* only set it on core0 */
set_EnableCf8ExtCfg(); /* only set it on core0 */ set_EnableCf8ExtCfg(); /* only set it on core0 */
#if (ENABLE_APIC_EXT_ID == 1) #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
enable_apic_ext_id(id.nodeid); enable_apic_ext_id(id.nodeid);
#endif #endif
} }
@ -345,23 +345,23 @@ static u32 init_cpus(u32 cpu_init_detectedx)
enable_lapic(); enable_lapic();
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid(); u32 initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0 #if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp if( initial_apicid != 0 ) // other than bsp
#endif #endif
{ {
/* use initial apic id to lift it */ /* use initial apic id to lift it */
u32 dword = lapic_read(LAPIC_ID); u32 dword = lapic_read(LAPIC_ID);
dword &= ~(0xff << 24); dword &= ~(0xff << 24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24); dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
lapic_write(LAPIC_ID, dword); lapic_write(LAPIC_ID, dword);
} }
#if LIFT_BSP_APIC_ID == 1 #if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET; bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif #endif
#endif #endif
@ -478,8 +478,8 @@ static void start_node(u8 node)
/* Enable routing table */ /* Enable routing table */
printk_debug("Start node %02x", node); printk_debug("Start node %02x", node);
#if CAR_FAM10 == 1 #if CONFIG_CAR_FAM10 == 1
/* For CAR_FAM10 support, we need to set Dram base/limit for the new node */ /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3); pci_write_config32(NODE_MP(node), 0x40, 3);
#endif #endif

2
src/cpu/amd/model_10xxx/update_microcode.c
View File

@ -47,7 +47,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
* 00100F62h (DA-C2) 1062h 0100009Fh * 00100F62h (DA-C2) 1062h 0100009Fh
*/ */
#include AMD_UCODE_PATCH_FILE #include CONFIG_AMD_UCODE_PATCH_FILE
#endif #endif
/* Dummy terminator */ /* Dummy terminator */

12
src/cpu/amd/model_fxx/Config.lb
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@ -1,10 +1,10 @@
uses HAVE_INIT_TIMER uses CONFIG_HAVE_INIT_TIMER
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
uses CPU_ADDR_BITS uses CONFIG_CPU_ADDR_BITS
default HAVE_INIT_TIMER=1 default CONFIG_HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
default CPU_ADDR_BITS=40 default CONFIG_CPU_ADDR_BITS=40
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/fpu dir /cpu/x86/fpu
dir /cpu/x86/mmx dir /cpu/x86/mmx

2
src/cpu/amd/model_fxx/fidvid.c
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@ -73,7 +73,7 @@ static void enable_fid_change(void)
// dword = 0x00070000; /* enable FID/VID change */ // dword = 0x00070000; /* enable FID/VID change */
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword); pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
#if HAVE_ACPI_RESUME #if CONFIG_HAVE_ACPI_RESUME
dword = 0x21132113; dword = 0x21132113;
#else #else
dword = 0x00132113; dword = 0x00132113;

34
src/cpu/amd/model_fxx/init_cpus.c
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@ -1,6 +1,6 @@
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID #ifndef K8_SET_FIDVID
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
#define K8_SET_FIDVID 0 #define K8_SET_FIDVID 0
#else #else
// for rev F, need to set FID to max // for rev F, need to set FID to max
@ -72,7 +72,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
nodes = get_nodes(); nodes = get_nodes();
disable_siblings = !CONFIG_LOGICAL_CPUS; disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1 #if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
disable_siblings = 1; disable_siblings = 1;
} }
@ -87,7 +87,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
if(nb_cfg_54) { if(nb_cfg_54) {
if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
e0_later_single_core = is_e0_later_in_bsp(i); // single core e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else #else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
@ -119,11 +119,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
#if (ENABLE_APIC_EXT_ID == 1) #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if LIFT_BSP_APIC_ID == 0 #if CONFIG_LIFT_BSP_APIC_ID == 0
if( (i!=0) || (j!=0)) /* except bsp */ if( (i!=0) || (j!=0)) /* except bsp */
#endif #endif
ap_apicid += APIC_ID_OFFSET; ap_apicid += CONFIG_APIC_ID_OFFSET;
#endif #endif
if(ap_apicid == bsp_apicid) continue; if(ap_apicid == bsp_apicid) continue;
@ -238,12 +238,12 @@ static void STOP_CAR_AND_CPU(void)
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
} }
#ifndef MEM_TRAIN_SEQ #ifndef CONFIG_MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0 #define CONFIG_MEM_TRAIN_SEQ 0
#endif #endif
#if MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
#endif #endif
@ -268,7 +268,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
/* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */ /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */
if(id.coreid == 0) { if(id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */ set_apicid_cpuid_lo(); /* only set it on core0 */
#if ENABLE_APIC_EXT_ID == 1 #if CONFIG_ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(id.nodeid); enable_apic_ext_id(id.nodeid);
#endif #endif
} }
@ -276,22 +276,22 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
enable_lapic(); enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change // init_timer(); // We need TMICT to pass msg for FID/VID change
#if (ENABLE_APIC_EXT_ID == 1) #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
unsigned initial_apicid = get_initial_apicid(); unsigned initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0 #if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp if( initial_apicid != 0 ) // other than bsp
#endif #endif
{ {
/* use initial apic id to lift it */ /* use initial apic id to lift it */
uint32_t dword = lapic_read(LAPIC_ID); uint32_t dword = lapic_read(LAPIC_ID);
dword &= ~(0xff<<24); dword &= ~(0xff<<24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
lapic_write(LAPIC_ID, dword); lapic_write(LAPIC_ID, dword);
} }
#if LIFT_BSP_APIC_ID == 1 #if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET; bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif #endif
#endif #endif
@ -346,7 +346,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
} }
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access(); set_init_ram_access();
#if MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
#endif #endif

28
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -32,15 +32,15 @@
void cpus_ready_for_init(void) void cpus_ready_for_init(void)
{ {
#if MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained // wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox); wait_all_core0_mem_trained(sysinfox);
#endif #endif
} }
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid) int is_e0_later_in_bsp(int nodeid)
{ {
uint32_t val; uint32_t val;
@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid)
} }
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
int is_cpu_f0_in_bsp(int nodeid) int is_cpu_f0_in_bsp(int nodeid)
{ {
uint32_t dword; uint32_t dword;
@ -289,8 +289,8 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) if (!is_cpu_pre_e0())
{ {
#endif #endif
@ -300,7 +300,7 @@ static void init_ecc_memory(unsigned node_id)
if(val & 1) { if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10); hole_startk = ((val & (0xff<<24)) >> 10);
} }
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
} }
#endif #endif
#endif #endif
@ -322,7 +322,7 @@ static void init_ecc_memory(unsigned node_id)
disable_lapic(); disable_lapic();
/* Walk through 2M chunks and zero them */ /* Walk through 2M chunks and zero them */
#if HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */ /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) { if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
for(basek = begink; basek < hole_startk; for(basek = begink; basek < hole_startk;
@ -368,7 +368,7 @@ static void init_ecc_memory(unsigned node_id)
static inline void k8_errata(void) static inline void k8_errata(void)
{ {
msr_t msr; msr_t msr;
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
/* Erratum 63... */ /* Erratum 63... */
msr = rdmsr(HWCR_MSR); msr = rdmsr(HWCR_MSR);
@ -438,7 +438,7 @@ static inline void k8_errata(void)
} }
#endif #endif
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) if (!is_cpu_pre_e0())
#endif #endif
{ {
@ -453,7 +453,7 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6; msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr); wrmsr(HWCR_MSR, msr);
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
/* Erratum 131... */ /* Erratum 131... */
msr = rdmsr(NB_CFG_MSR); msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20; msr.lo |= 1 << 20;
@ -478,7 +478,7 @@ void model_fxx_init(device_t dev)
unsigned siblings; unsigned siblings;
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
struct cpuinfo_x86 c; struct cpuinfo_x86 c;
get_fms(&c, dev->device); get_fms(&c, dev->device);
@ -564,7 +564,7 @@ static struct device_operations cpu_dev_ops = {
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
{ X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
{ X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
{ X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
@ -606,7 +606,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
/* /*
* AMD F0 support. * AMD F0 support.
* *

8
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@ -52,13 +52,13 @@ $1.0$
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
#include "microcode_rev_c.h" #include "microcode_rev_c.h"
#include "microcode_rev_d.h" #include "microcode_rev_d.h"
#include "microcode_rev_e.h" #include "microcode_rev_e.h"
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
// #include "microcode_rev_f.h" // #include "microcode_rev_f.h"
#endif #endif
/* Dummy terminator */ /* Dummy terminator */
@ -70,7 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = { static unsigned id_mapping_table[] = {
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
0x0f48, 0x0048, 0x0f48, 0x0048,
0x0f58, 0x0048, 0x0f58, 0x0048,
@ -93,7 +93,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20fb1, 0x0210, 0x20fb1, 0x0210,
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#endif #endif

2
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@ -169,7 +169,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
cpuid1 = cpuid(0x80000001); cpuid1 = cpuid(0x80000001);
pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14); pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++) for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
if (TDP[index].socket_type == CPU_SOCKET_TYPE && if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE &&
TDP[index].cmp_cap == cmp_cap && TDP[index].cmp_cap == cmp_cap &&
TDP[index].pwr_lmt == pwr_lmt) { TDP[index].pwr_lmt == pwr_lmt) {
power_limit = TDP[index].power_limit; power_limit = TDP[index].power_limit;

10
src/cpu/amd/model_fxx/processor_name.c
View File

@ -41,7 +41,7 @@
* your mainboard will not be posted on the AMD Recommended Motherboard Website * your mainboard will not be posted on the AMD Recommended Motherboard Website
*/ */
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
static char *processor_names[]={ static char *processor_names[]={
/* 0x00 */ "AMD Engineering Sample", /* 0x00 */ "AMD Engineering Sample",
/* 0x01-0x03 */ NULL, NULL, NULL, /* 0x01-0x03 */ NULL, NULL, NULL,
@ -163,7 +163,7 @@ int init_processor_name(void)
char program_string[48]; char program_string[48];
unsigned int *program_values = (unsigned int *)program_string; unsigned int *program_values = (unsigned int *)program_string;
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
/* Find out which CPU brand it is */ /* Find out which CPU brand it is */
EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
BrandId = cpuid_ebx(0x80000001) & 0xffff; BrandId = cpuid_ebx(0x80000001) & 0xffff;
@ -187,7 +187,7 @@ int init_processor_name(void)
processor_name_string = "AMD Processor model unknown"; processor_name_string = "AMD Processor model unknown";
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
u32 Socket; u32 Socket;
u32 CmpCap; u32 CmpCap;
u32 PwrLmt; u32 PwrLmt;
@ -343,7 +343,7 @@ int init_processor_name(void)
for (i=0; i<47; i++) { // 48 -1 for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) { if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) { switch (program_string[i]) {
#if K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
case 'X': ModelNumber = 22+ NN; break; case 'X': ModelNumber = 22+ NN; break;
case 'Y': ModelNumber = 38 + (2*NN); break; case 'Y': ModelNumber = 38 + (2*NN); break;
case 'Z': case 'Z':
@ -352,7 +352,7 @@ int init_processor_name(void)
case 'V': ModelNumber = 9 + NN; break; case 'V': ModelNumber = 9 + NN; break;
#endif #endif
#if K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
case 'R': ModelNumber = NN - 1; break; case 'R': ModelNumber = NN - 1; break;
case 'P': ModelNumber = 26 + NN; break; case 'P': ModelNumber = 26 + NN; break;
case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;

2
src/cpu/amd/model_gx2/vsmsetup.c
View File

@ -271,7 +271,7 @@ void do_vsmbios(void)
//rom = 0xfff80000; //rom = 0xfff80000;
//rom = 0xfffc0000; //rom = 0xfffc0000;
/* the VSA starts at the base of rom - 64 */ /* the VSA starts at the base of rom - 64 */
rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE + 64*1024);
buf = (unsigned char *) 0x60000; buf = (unsigned char *) 0x60000;
olen = unrv2b((uint8_t *)rom, buf, &ilen); olen = unrv2b((uint8_t *)rom, buf, &ilen);

28
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1) #define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ #define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ #define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
@ -82,7 +82,7 @@ DCacheSetup:
xorl %esi, %esi xorl %esi, %esi
xorl %ebp, %ebp xorl %ebp, %ebp
/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */ /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
/* remember, there is NO stack yet... */ /* remember, there is NO stack yet... */
/* Tell cache we want to fill WAY 0 starting at the top */ /* Tell cache we want to fill WAY 0 starting at the top */
@ -192,7 +192,7 @@ done_cache_as_ram_main:
mov string, %ebx ; \ mov string, %ebx ; \
CALLSP(crt_console_tx_string) CALLSP(crt_console_tx_string)
# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
# else # else
# define CONSOLE_DEBUG_TX_STRING(string) # define CONSOLE_DEBUG_TX_STRING(string)
@ -333,26 +333,26 @@ crt_console_tx_string:
RETSP RETSP
9: 9:
/* Base Address */ /* Base Address */
#ifndef TTYS0_BASE #ifndef CONFIG_TTYS0_BASE
#define TTYS0_BASE 0x3f8 #define CONFIG_TTYS0_BASE 0x3f8
#endif #endif
/* Data */ /* Data */
#define TTYS0_RBR (TTYS0_BASE+0x00) #define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
/* Control */ /* Control */
#define TTYS0_TBR TTYS0_RBR #define TTYS0_TBR TTYS0_RBR
#define TTYS0_IER (TTYS0_BASE+0x01) #define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
#define TTYS0_IIR (TTYS0_BASE+0x02) #define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
#define TTYS0_FCR TTYS0_IIR #define TTYS0_FCR TTYS0_IIR
#define TTYS0_LCR (TTYS0_BASE+0x03) #define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
#define TTYS0_MCR (TTYS0_BASE+0x04) #define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
#define TTYS0_DLL TTYS0_RBR #define TTYS0_DLL TTYS0_RBR
#define TTYS0_DLM TTYS0_IER #define TTYS0_DLM TTYS0_IER
/* Status */ /* Status */
#define TTYS0_LSR (TTYS0_BASE+0x05) #define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
#define TTYS0_MSR (TTYS0_BASE+0x06) #define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
#define TTYS0_SCR (TTYS0_BASE+0x07) #define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
mov %al, %ah mov %al, %ah
10: mov $TTYS0_LSR, %dx 10: mov $TTYS0_LSR, %dx

2
src/cpu/amd/model_lx/syspreinit.c
View File

@ -39,7 +39,7 @@ void SystemPreInit(void)
{ {
/* they want a jump ... */ /* they want a jump ... */
#ifndef USE_DCACHE_RAM #ifndef CONFIG_USE_DCACHE_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif #endif
StartTimer1(); StartTimer1();

2
src/cpu/amd/model_lx/vsmsetup.c
View File

@ -292,7 +292,7 @@ void do_vsmbios(void)
*/ */
//VSA is cat onto the end after LB builds //VSA is cat onto the end after LB builds
rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); rom = ((unsigned long)0) - (CONFIG_ROM_SIZE + 36 * 1024);
buf = (unsigned char *)VSA2_BUFFER; buf = (unsigned char *)VSA2_BUFFER;
olen = unrv2b((uint8_t *) rom, buf, &ilen); olen = unrv2b((uint8_t *) rom, buf, &ilen);
printk_debug("buf ilen %d olen%d\n", ilen, olen); printk_debug("buf ilen %d olen%d\n", ilen, olen);

4
src/cpu/amd/mtrr/amd_earlymtrr.c
View File

@ -41,11 +41,11 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
wrmsr(TOP_MEM, msr); wrmsr(TOP_MEM, msr);
#if defined(XIP_ROM_SIZE) #if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place /* enable write through caching so we can do execute in place
* on the flash rom. * on the flash rom.
*/ */
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif #endif
/* Set the default memory type and enable fixed and variable MTRRs /* Set the default memory type and enable fixed and variable MTRRs

2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -180,7 +180,7 @@ void amd_setup_mtrrs(void)
/* FIXME we should probably query the cpu for this /* FIXME we should probably query the cpu for this
* but so far this is all any recent AMD cpu has supported. * but so far this is all any recent AMD cpu has supported.
*/ */
address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
/* Now that I have mapped what is memory and what is not /* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory. * Setup the mtrrs so we can cache the memory.

2
src/cpu/amd/quadcore/amd_sibling.c
View File

@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) { if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID // We need to enable APIC EXT ID
printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(sysconf.nodes); enable_apic_ext_id(sysconf.nodes);
} }

16
src/cpu/amd/socket_AM2/Config.lb
View File

@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT uses CONFIG_K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT uses CONFIG_DIMM_SUPPORT
uses CPU_SOCKET_TYPE uses CONFIG_CPU_SOCKET_TYPE
config chip.h config chip.h
default K8_REV_F_SUPPORT=1 default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support #Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0004 #DDR2 unbuffered default CONFIG_DIMM_SUPPORT=0x0004 #DDR2 unbuffered
default CPU_SOCKET_TYPE=0x11 default CONFIG_CPU_SOCKET_TYPE=0x11
object socket_AM2.o object socket_AM2.o

16
src/cpu/amd/socket_F/Config.lb
View File

@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT uses CONFIG_K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT uses CONFIG_DIMM_SUPPORT
uses CPU_SOCKET_TYPE uses CONFIG_CPU_SOCKET_TYPE
config chip.h config chip.h
default K8_REV_F_SUPPORT=1 default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support #Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CPU_SOCKET_TYPE=0x10 default CONFIG_CPU_SOCKET_TYPE=0x10
object socket_F.o object socket_F.o

46
src/cpu/amd/socket_F_1207/Config.lb
View File

@ -17,37 +17,37 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
uses PCI_IO_CFG_EXT uses CONFIG_PCI_IO_CFG_EXT
uses MMCONF_SUPPORT uses CONFIG_MMCONF_SUPPORT
uses HT3_SUPPORT uses CONFIG_HT3_SUPPORT
uses EXT_RT_TBL_SUPPORT uses CONFIG_EXT_RT_TBL_SUPPORT
uses EXT_CONF_SUPPORT uses CONFIG_EXT_CONF_SUPPORT
uses DIMM_SUPPORT uses CONFIG_DIMM_SUPPORT
uses CPU_SOCKET_TYPE uses CONFIG_CPU_SOCKET_TYPE
uses CBB uses CONFIG_CBB
uses CDB uses CONFIG_CDB
uses PCI_BUS_SEGN_BITS uses CONFIG_PCI_BUS_SEGN_BITS
uses CAR_FAM10 uses CONFIG_CAR_FAM10
config chip.h config chip.h
default PCI_IO_CFG_EXT=1 default CONFIG_PCI_IO_CFG_EXT=1
default HT3_SUPPORT=1 default CONFIG_HT3_SUPPORT=1
default EXT_RT_TBL_SUPPORT=0 default CONFIG_EXT_RT_TBL_SUPPORT=0
default EXT_CONF_SUPPORT=0 default CONFIG_EXT_CONF_SUPPORT=0
default DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CPU_SOCKET_TYPE=0x10 default CONFIG_CPU_SOCKET_TYPE=0x10
default CAR_FAM10=1 default CONFIG_CAR_FAM10=1
if EXT_RT_TBL_SUPPORT if CONFIG_EXT_RT_TBL_SUPPORT
default CBB=0xff default CONFIG_CBB=0xff
default CDB=0 default CONFIG_CDB=0
end end
#default MMCONF_SUPPORT=1 #default CONFIG_MMCONF_SUPPORT=1
#default MMCONF_SUPPORT_DEFAULT=1 #default CONFIG_MMCONF_SUPPORT_DEFAULT=1
object socket_F_1207.o object socket_F_1207.o

16
src/cpu/amd/socket_S1G1/Config.lb
View File

@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT uses CONFIG_K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT uses CONFIG_DIMM_SUPPORT
uses CPU_SOCKET_TYPE uses CONFIG_CPU_SOCKET_TYPE
config chip.h config chip.h
default K8_REV_F_SUPPORT=1 default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support #Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 default CONFIG_DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1
default CPU_SOCKET_TYPE=0x12 default CONFIG_CPU_SOCKET_TYPE=0x12
object socket_S1G1.o object socket_S1G1.o

4
src/cpu/emulation/qemu-x86/northbridge.c
View File

@ -65,7 +65,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm; return tolm;
} }
#if HAVE_HIGH_TABLES==1 #if CONFIG_HAVE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
@ -118,7 +118,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768); ram_resource(dev, idx++, 768, tolmk - 768);
#if HAVE_HIGH_TABLES==1 #if CONFIG_HAVE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */ /* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024;

4
src/cpu/intel/model_6ex/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr

14
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x) #define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
@ -29,7 +29,7 @@
movl %eax, %ebp movl %eax, %ebp
cache_as_ram: cache_as_ram:
#if USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20) post_code(0x20)
@ -101,18 +101,18 @@ clear_mtrrs:
orl $(1 << 30), %eax orl $(1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax

6
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@ -27,7 +27,7 @@ void stage1_main(unsigned long bist)
{ {
unsigned int cpu_reset = 0; unsigned int cpu_reset = 0;
#if USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) { if (bios_reset_detected() && last_boot_normal()) {
goto normal_image; goto normal_image;
@ -87,10 +87,10 @@ cpu_reset_x:
} }
__asm__ volatile ( __asm__ volatile (
/* set new esp */ /* before _RAMBASE */ /* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t" "subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t" "subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
); );
{ {

4
src/cpu/intel/model_6fx/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr

14
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x) #define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
@ -29,7 +29,7 @@
movl %eax, %ebp movl %eax, %ebp
cache_as_ram: cache_as_ram:
#if USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20) post_code(0x20)
@ -108,18 +108,18 @@ clear_mtrrs:
orl $(1 << 30), %eax orl $(1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax

6
src/cpu/intel/model_6fx/cache_as_ram_disable.c
View File

@ -27,7 +27,7 @@ void stage1_main(unsigned long bist)
{ {
unsigned int cpu_reset = 0; unsigned int cpu_reset = 0;
#if USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) { if (bios_reset_detected() && last_boot_normal()) {
goto normal_image; goto normal_image;
@ -87,10 +87,10 @@ cpu_reset_x:
} }
__asm__ volatile ( __asm__ volatile (
/* set new esp */ /* before _RAMBASE */ /* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t" "subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t" "subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
); );
{ {

4
src/cpu/intel/model_f0x/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr
dir /cpu/x86/fpu dir /cpu/x86/fpu

4
src/cpu/intel/model_f1x/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr
dir /cpu/x86/fpu dir /cpu/x86/fpu

4
src/cpu/intel/model_f2x/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr
dir /cpu/x86/fpu dir /cpu/x86/fpu

4
src/cpu/intel/model_f3x/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr
dir /cpu/x86/fpu dir /cpu/x86/fpu

4
src/cpu/intel/model_f4x/Config.lb
View File

@ -1,5 +1,5 @@
uses HAVE_MOVNTI uses CONFIG_HAVE_MOVNTI
default HAVE_MOVNTI=1 default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc dir /cpu/x86/tsc
dir /cpu/x86/mtrr dir /cpu/x86/mtrr
dir /cpu/x86/fpu dir /cpu/x86/fpu

14
src/cpu/ppc/mpc74xx/Config.lb
View File

@ -1,19 +1,19 @@
## ##
## CPU initialization ## CPU initialization
## ##
uses _RAMBASE uses CONFIG_RAMBASE
uses USE_DCACHE_RAM uses CONFIG_USE_DCACHE_RAM
uses DCACHE_RAM_BASE uses CONFIG_DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE uses CONFIG_DCACHE_RAM_SIZE
## ##
## Use cache ram for initial setup ## Use cache ram for initial setup
## ##
default USE_DCACHE_RAM=1 default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image ## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000 default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 32Kb ## Dcache size is 32Kb
default DCACHE_RAM_SIZE=0x8000 default CONFIG_DCACHE_RAM_SIZE=0x8000
initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object cache.S object cache.S

8
src/cpu/ppc/mpc74xx/mpc74xx.inc
View File

@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow * - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions: * - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff) * - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff) * - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region * - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through * can be marked cache inhibited/write through
@ -147,7 +147,7 @@
* IBATS * IBATS
* *
* IBAT0 covers RAM (0 -> 256Mb) * IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/ */
lis r2, 0@h lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@ -156,8 +156,8 @@
mtibatl 0, r2 mtibatl 0, r2
isync isync
lis r2, _ROMBASE@h lis r2, CONFIG_ROMBASE@h
#if ROM_SIZE > 1048576 #if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else #else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER

14
src/cpu/ppc/ppc4xx/Config.lb
View File

@ -1,19 +1,19 @@
## ##
## CPU initialization ## CPU initialization
## ##
uses _RAMBASE uses CONFIG_RAMBASE
uses USE_DCACHE_RAM uses CONFIG_USE_DCACHE_RAM
uses DCACHE_RAM_BASE uses CONFIG_DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE uses CONFIG_DCACHE_RAM_SIZE
## ##
## PPC4XX always uses cache ram for initial setup ## PPC4XX always uses cache ram for initial setup
## ##
default USE_DCACHE_RAM=1 default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image ## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000 default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb ## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384 default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
initobject cache.S initobject cache.S

6
src/cpu/ppc/ppc4xx/cache.S
View File

@ -57,7 +57,7 @@ invalidate_icache:
invalidate_dcache: invalidate_dcache:
li r6,0x0000 /* clear GPR 6 */ li r6,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */ /* Do loop for # of dcache congruence classes. */
li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */ /* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */ mtctr r7 /* ways in the D cache */
1: 1:
@ -79,8 +79,8 @@ flush_dcache:
mtdccr r10 mtdccr r10
/* do loop for # of congruence classes. */ /* do loop for # of congruence classes. */
li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
mtctr r10 mtctr r10
li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */ li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */ add r11,r10,r11 /* add to get to other side of cache line */

2
src/cpu/ppc/ppc4xx/pci_domain.c
View File

@ -47,7 +47,7 @@ static void pci_domain_set_resources(device_t dev)
{ {
int idx = 3; /* who knows? */ int idx = 3; /* who knows? */
ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10); ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10);
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }

8
src/cpu/ppc/ppc4xx/ppc4xx.inc
View File

@ -94,15 +94,15 @@
isync isync
/* /*
* Enable dcache region containing DCACHE_RAM_BASE * Enable dcache region containing CONFIG_DCACHE_RAM_BASE
* On reset all regions are set to write-back, so we * On reset all regions are set to write-back, so we
* just leave them alone. * just leave them alone.
* *
* dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27)) * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
*/ */
lis r4, DCACHE_RAM_BASE@ha lis r4, CONFIG_DCACHE_RAM_BASE@ha
ori r4, r4, DCACHE_RAM_BASE@l ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
srwi r4, r4, 27 srwi r4, r4, 27
subfic r4, r4, 31 subfic r4, r4, 31
li r0, 1 li r0, 1

8
src/cpu/ppc/ppc4xx/sdram.c
View File

@ -98,17 +98,17 @@ void memory_init(void)
/* TODO: work out why this trashes cache ram */ /* TODO: work out why this trashes cache ram */
//mtsdram0(mem_mcopt1, 0x00000000); //mtsdram0(mem_mcopt1, 0x00000000);
#if EMBEDDED_RAM_SIZE==128*1024*1024 #if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024
/* TODO */ /* TODO */
#elif EMBEDDED_RAM_SIZE==64*1024*1024 #elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024
set_sdram0(mem_sdtr1, TR); set_sdram0(mem_sdtr1, TR);
set_sdram0(mem_mb0cf, B0CR); set_sdram0(mem_mb0cf, B0CR);
set_sdram0(mem_rtr, RTR); set_sdram0(mem_rtr, RTR);
set_sdram0(mem_ecccf, ECCCF); set_sdram0(mem_ecccf, ECCCF);
set_sdram0(mem_pmit, PMIT); set_sdram0(mem_pmit, PMIT);
#elif EMBEDDED_RAM_SIZE==32*1024*1024 #elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024
/* TODO */ /* TODO */
#elif EMBEDDED_RAM_SIZE==16*1024*1024 #elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024
/* TODO */ /* TODO */
#endif #endif

14
src/cpu/ppc/ppc7xx/Config.lb
View File

@ -1,19 +1,19 @@
## ##
## CPU initialization ## CPU initialization
## ##
uses _RAMBASE uses CONFIG_RAMBASE
uses USE_DCACHE_RAM uses CONFIG_USE_DCACHE_RAM
uses DCACHE_RAM_BASE uses CONFIG_DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE uses CONFIG_DCACHE_RAM_SIZE
## ##
## PPC7XX always uses cache ram for initial setup ## PPC7XX always uses cache ram for initial setup
## ##
default USE_DCACHE_RAM=1 default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image ## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000 default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb ## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384 default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc

14
src/cpu/ppc/ppc7xx/ppc7xx.inc
View File

@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow * - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions: * - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff) * - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff) * - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region * - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through * can be marked cache inhibited/write through
@ -113,7 +113,7 @@
* IBATS * IBATS
* *
* IBAT0 covers RAM (0 -> 256Mb) * IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/ */
lis r2, 0@h lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@ -122,8 +122,8 @@
mtibatl 0, r2 mtibatl 0, r2
isync isync
lis r2, _ROMBASE@h lis r2, CONFIG_ROMBASE@h
#if ROM_SIZE > 1048576 #if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else #else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@ -161,9 +161,9 @@
* Initialize data cache blocks * Initialize data cache blocks
* (assumes cache block size of 32 bytes) * (assumes cache block size of 32 bytes)
*/ */
lis r1, DCACHE_RAM_BASE@h lis r1, CONFIG_DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32) li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3 mtctr r3
0: dcbz r0, r1 0: dcbz r0, r1
addi r1, r1, 32 addi r1, r1, 32

6
src/cpu/ppc/ppc970/Config.lb
View File

@ -1,15 +1,15 @@
## ##
## CPU initialization ## CPU initialization
## ##
uses _RAMBASE uses CONFIG_RAMBASE
uses USE_DCACHE_RAM uses CONFIG_USE_DCACHE_RAM
## ##
## Assumes RAM already initialiazed ## Assumes RAM already initialiazed
## This is true for the Apache board, but may ## This is true for the Apache board, but may
## not be for other 970 systems. ## not be for other 970 systems.
## ##
default USE_DCACHE_RAM=0 default CONFIG_USE_DCACHE_RAM=0
initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc

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