soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
This commit adds power limit settings for 4+8 28W SOC sku and renames MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W settings. BUG=b:306677879 TEST=boot on rex with 4+8 SOC and power limit settings are correct Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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committed by
Subrata Banik
parent
d599e89d4d
commit
08db7cd0d0
@@ -43,7 +43,7 @@ struct ibecc_config {
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/* Types of different SKUs */
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enum soc_intel_meteorlake_power_limits {
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MTL_P_282_242_CORE,
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MTL_P_682_CORE,
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MTL_P_682_482_CORE,
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MTL_POWER_LIMITS_COUNT
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};
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@@ -61,7 +61,8 @@ static const struct {
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} cpuid_to_mtl[] = {
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{ PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W },
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{ PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W },
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{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_CORE, TDP_28W },
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{ PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W },
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{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W },
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};
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/* Types of display ports */
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@@ -8,7 +8,7 @@ chip soc/intel/meteorlake
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.tdp_pl4 = 114,
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}"
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register "power_limits_config[MTL_P_682_CORE]" = "{
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register "power_limits_config[MTL_P_682_482_CORE]" = "{
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.tdp_pl1_override = 28,
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.tdp_pl2_override = 64,
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.tdp_pl4 = 120,
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