soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU

This commit adds power limit settings for 4+8 28W SOC sku and renames
MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W
settings.

BUG=b:306677879
TEST=boot on rex with 4+8 SOC and power limit settings are correct

Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Curtis Chen
2023-10-31 16:18:35 +08:00
committed by Subrata Banik
parent d599e89d4d
commit 08db7cd0d0
2 changed files with 4 additions and 3 deletions

View File

@@ -43,7 +43,7 @@ struct ibecc_config {
/* Types of different SKUs */
enum soc_intel_meteorlake_power_limits {
MTL_P_282_242_CORE,
MTL_P_682_CORE,
MTL_P_682_482_CORE,
MTL_POWER_LIMITS_COUNT
};
@@ -61,7 +61,8 @@ static const struct {
} cpuid_to_mtl[] = {
{ PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W },
{ PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W },
{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_CORE, TDP_28W },
{ PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W },
{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W },
};
/* Types of display ports */

View File

@@ -8,7 +8,7 @@ chip soc/intel/meteorlake
.tdp_pl4 = 114,
}"
register "power_limits_config[MTL_P_682_CORE]" = "{
register "power_limits_config[MTL_P_682_482_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 64,
.tdp_pl4 = 120,