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mb/google/{poppy,soraka}: Enable LTR for Root port

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Enable LTR for Root port 0, where wifi card is connected.

BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
     by AER driver for root port 0.

Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Rizwan Qureshi
2017-09-16 02:01:13 +05:30
committed by Furquan Shaikh
parent 03937391bc
commit 09703f6494
2 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@@ -153,7 +153,9 @@ chip soc/intel/skylake
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register PcieRpAdvancedErrorReporting[0] = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port

4
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@@ -153,7 +153,9 @@ chip soc/intel/skylake
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register PcieRpAdvancedErrorReporting[0] = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port