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lib/stage_cache: Refactor Kconfig options

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Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.

Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.

There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.

As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.

Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kyösti Mälkki
2019-08-01 20:29:14 +03:00
parent cccb815c5e
commit 0a4457ff44
19 changed files with 29 additions and 32 deletions
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1
src/northbridge/intel/gm45/Kconfig
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@@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE
hex

1
src/northbridge/intel/haswell/Kconfig
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@@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL
select CACHE_MRC_SETTINGS
select INTEL_DDI
select INTEL_GMA_ACPI
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select C_ENVIRONMENT_BOOTBLOCK

1
src/northbridge/intel/i945/Kconfig
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@@ -30,7 +30,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n

1
src/northbridge/intel/pineview/Kconfig
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@@ -31,7 +31,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT

1
src/northbridge/intel/x4x/Kconfig
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@@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE
hex