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sb/intel/lynxpoint: Replace HPET_ADDR

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The `HPET_ADDRESS` Kconfig option has the same value. Use it instead.

Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2021-03-12 12:54:45 +01:00
committed by Patrick Georgi
parent ae5ab1826a
commit 0b39379c9c
2 changed files with 1 additions and 3 deletions
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2
src/northbridge/intel/haswell/romstage.c
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@@ -56,7 +56,7 @@ void mainboard_romstage_entry(void)
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = HPET_ADDR, .hpet_address = CONFIG_HPET_ADDRESS,
.rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,

2
src/southbridge/intel/lynxpoint/pch.h
View File

@@ -63,8 +63,6 @@
#define DEFAULT_GPIOSIZE 0x80 #define DEFAULT_GPIOSIZE 0x80
#endif #endif
#define HPET_ADDR 0xfed00000
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__ #ifndef __ACPI__