skl mainboards/dt: Drop SsicPortEnable setting if disabled

The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-23 03:56:43 +02:00
parent 1a77d1e437
commit 0c1daa59b9
17 changed files with 0 additions and 18 deletions
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "SataPortsDevSlp[2]" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
 		device ref igpu 	on	end
 		device ref sa_thermal	on	end
 		device ref south_xhci	on
-			register "SsicPortEnable" = "0"
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A, right
 			register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# 3G / LTE
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -197,8 +197,6 @@ chip soc/intel/skylake
 		[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-C Port 1 */
 	}"

-	register "SsicPortEnable" = "0"
-
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -71,7 +71,6 @@ chip soc/intel/skylake
 	register "SataPortsDevSlp[1]" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
 	register "SataSalpSupport" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "SataSpeedLimit" = "2"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "SataSalpSupport" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
 	register "SataPortsDevSlp[2]" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -30,7 +30,6 @@ chip soc/intel/skylake
 	}"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"