northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12008 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
committed by
Jonathan A. Kollasch
parent
6b6c653ce7
commit
0d0375b3c6
@@ -5631,7 +5631,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
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static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat, u8 dct)
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{
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
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@@ -5641,6 +5645,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
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u32 dword;
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u32 dev = pDCTstat->dev_dct;
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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/* FIXME
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* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
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* For now assume a maximum of 2 DIMMs per channel can be installed
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@@ -5955,6 +5961,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
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Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
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}
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}
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
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@@ -188,9 +188,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
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u32 dev = pDCTstat->dev_dct;
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u32 val;
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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do {
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val = Get_NB32_DCT(dev, dct, 0x98);
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} while (!(val & (1 << DctAccessDone)));
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
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@@ -235,6 +239,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
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u32 dev = pDCTstat->dev_dct;
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u32 val;
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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val = Get_NB32_DCT(dev, dct, 0x7c);
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val &= ~0x00ffffff;
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val |= EMRS;
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@@ -244,6 +250,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
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do {
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val = Get_NB32_DCT(dev, dct, 0x7c);
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} while (val & (1 << SendMrsCmd));
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
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@@ -553,6 +561,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
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u32 dev = pDCTstat->dev_dct;
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u32 dword;
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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/*1.Program MrsAddress[10]=1
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2.Set SendZQCmd=1
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*/
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@@ -569,6 +579,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
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/* 4.Wait 512 MEMCLKs */
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mct_Wait(300);
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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@@ -578,6 +590,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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u32 dword;
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u32 dev = pDCTstat->dev_dct;
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printk(BIOS_DEBUG, "%s: Start\n", __func__);
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if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
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/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
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dword = Get_NB32_DCT(dev, dct, 0x7c);
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@@ -659,4 +673,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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Set_NB32_DCT(dev, dct, 0x7C, dword);
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mct_DCTAccessDone(pDCTstat, dct);
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}
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printk(BIOS_DEBUG, "%s: Done\n", __func__);
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}
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