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northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements

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Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12008
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Timothy Pearson
2015-06-26 00:17:10 -05:00
committed by Jonathan A. Kollasch
parent 6b6c653ce7
commit 0d0375b3c6
2 changed files with 24 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@@ -5631,7 +5631,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct)
{
printk(BIOS_DEBUG, "%s: Start\n", __func__);
mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
@@ -5641,6 +5645,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
u32 dword;
u32 dev = pDCTstat->dev_dct;
printk(BIOS_DEBUG, "%s: Start\n", __func__);
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
@@ -5955,6 +5961,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
}
}
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,

16
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
View File

@@ -188,9 +188,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
u32 dev = pDCTstat->dev_dct;
u32 val;
printk(BIOS_DEBUG, "%s: Start\n", __func__);
do {
val = Get_NB32_DCT(dev, dct, 0x98);
} while (!(val & (1 << DctAccessDone)));
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
@@ -235,6 +239,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
u32 dev = pDCTstat->dev_dct;
u32 val;
printk(BIOS_DEBUG, "%s: Start\n", __func__);
val = Get_NB32_DCT(dev, dct, 0x7c);
val &= ~0x00ffffff;
val |= EMRS;
@@ -244,6 +250,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
do {
val = Get_NB32_DCT(dev, dct, 0x7c);
} while (val & (1 << SendMrsCmd));
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
@@ -553,6 +561,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
u32 dev = pDCTstat->dev_dct;
u32 dword;
printk(BIOS_DEBUG, "%s: Start\n", __func__);
/*1.Program MrsAddress[10]=1
2.Set SendZQCmd=1
*/
@@ -569,6 +579,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
/* 4.Wait 512 MEMCLKs */
mct_Wait(300);
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
@@ -578,6 +590,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
u32 dword;
u32 dev = pDCTstat->dev_dct;
printk(BIOS_DEBUG, "%s: Start\n", __func__);
if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
dword = Get_NB32_DCT(dev, dct, 0x7c);
@@ -659,4 +673,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x7C, dword);
mct_DCTAccessDone(pDCTstat, dct);
}
printk(BIOS_DEBUG, "%s: Done\n", __func__);
}