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soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default

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Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.

If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.

Also, add a release note for the upcoming 4.15 release.

Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2021-08-13 08:31:52 +02:00 committed by Michael Niewöhner
parent 621ae7c701
commit 0dcdb217cf
60 changed files with 9 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/releases/coreboot-4.15-relnotes.md
View File

@ -19,4 +19,11 @@ By using newer coreboot features like board variants and override devicetrees,
lots of code can now be shared. This should ease maintenance and also make it
easier for newcomers to add support for even more mainboards.
### Changed default setting for Intel chipset lockdown
Previously, the default behaviour for Intel chipset lockdown was to let the FSP
do it. Since all related mainboards used the coreboot mechanisms for chipset
lockdown, the default behaviour was changed to that.
### Add significant changes here

5
src/mainboard/51nb/x210/devicetree.cb
View File

@ -102,11 +102,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -41,10 +41,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

1
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
/* Touchpad */
.i2c[0] = {
.speed = I2C_SPEED_FAST,

4
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View File

@ -31,10 +31,6 @@ chip soc/intel/skylake
.tdp_pl2_override = 30,
}"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
}"

5
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -213,11 +213,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
}"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

2
src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
View File

@ -83,14 +83,12 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C3 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#+-------------------+---------------------------+
register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,

2
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
View File

@ -83,7 +83,6 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio and WFC |
#| I2C1 | Touchscreen |
@ -93,7 +92,6 @@ chip soc/intel/alderlake
#| | for TPM communication |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,

2
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -169,11 +169,9 @@ chip soc/intel/jasperlake
register "tcc_offset" = "10" # TCC of 90C
# chipset_lockdown configuration
# Use below format to override value in overridetree.cb if required
# format:
# register "common_soc_config.<variable_name>" = "value"
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
# VR config settings
# Imon Slope correction specified in 1/100 increment values. Range is 0-200.

2
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
View File

@ -62,7 +62,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Touchpad |
#| I2C2 | ISH ? |
@ -70,7 +69,6 @@ chip soc/intel/tigerlake
#| I2C5 | ISH ? |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},

2
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -162,7 +162,6 @@ chip soc/intel/cannonlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Touchpad |
#| I2C4 | H1 TPM |
@ -174,7 +173,6 @@ chip soc/intel/cannonlake
register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 180,

2
src/mainboard/google/eve/devicetree.cb
View File

@ -159,14 +159,12 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Early TPM access |
#| I2C2 | Touchpad |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.rise_time_ns = 98,

2
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -263,7 +263,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -272,7 +271,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

5
src/mainboard/google/glados/devicetree.cb
View File

@ -83,11 +83,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

2
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -195,11 +195,9 @@ chip soc/intel/cannonlake
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
# chipset_lockdown configuration
# Use below format to override value in overridetree.cb if required
# format:
# register "common_soc_config.<variable_name>" = "value"
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
device cpu_cluster 0 on
device lapic 0 on end

2
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -158,7 +158,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -170,7 +169,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,

2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -150,7 +150,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | H1 |
#| I2C2 | Camera |
@ -160,7 +159,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {

2
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -191,7 +191,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -203,7 +202,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -160,7 +160,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
@ -173,7 +172,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {

2
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -166,7 +166,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -179,7 +178,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 98,

2
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -157,14 +157,12 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Trackpad |
#| I2C5 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {

2
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -150,7 +150,6 @@ chip soc/intel/skylake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
@ -162,7 +161,6 @@ chip soc/intel/skylake
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -151,7 +151,6 @@ chip soc/intel/cannonlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Touchpad |
#| I2C4 | H1 TPM |
@ -163,7 +162,6 @@ chip soc/intel/cannonlake
register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 52,

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -152,7 +152,6 @@ chip soc/intel/cannonlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| I2C0 | Touchscreen |
#| I2C1 | Touchpad |
#| I2C4 | H1 TPM |
@ -164,7 +163,6 @@ chip soc/intel/cannonlake
register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 100,

2
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -309,7 +309,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -321,7 +320,6 @@ chip soc/intel/tigerlake
#| I2C3 | Camera, SAR1 |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,

4
src/mainboard/hp/280_g2/devicetree.cb
View File

@ -1,10 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */
}"

1
src/mainboard/intel/adlrvp/devicetree.cb
View File

@ -180,7 +180,6 @@ chip soc/intel/alderlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},

1
src/mainboard/intel/adlrvp/devicetree_m.cb
View File

@ -153,7 +153,6 @@ chip soc/intel/alderlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

4
src/mainboard/intel/cedarisland_crb/devicetree.cb
View File

@ -1,9 +1,5 @@
chip soc/intel/xeon_sp/cpx
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

2
src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
View File

@ -1,7 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
View File

@ -163,10 +163,6 @@ chip soc/intel/elkhartlake
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device

2
src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
View File

@ -165,7 +165,6 @@ chip soc/intel/icelake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -173,7 +172,6 @@ chip soc/intel/icelake
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
View File

@ -165,7 +165,6 @@ chip soc/intel/icelake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -173,7 +172,6 @@ chip soc/intel/icelake
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

1
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
View File

@ -136,7 +136,6 @@ chip soc/intel/jasperlake
register "sdcard_cd_gpio" = "VGPIO_39"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

4
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -110,10 +110,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -158,11 +158,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio" = "GPP_A7"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -35,11 +35,6 @@ chip soc/intel/skylake
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
# VR Settings Configuration for 4 Domains
#+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT |

2
src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
View File

@ -130,7 +130,6 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@ -143,7 +142,6 @@ chip soc/intel/alderlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

1
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -147,7 +147,6 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

1
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -151,7 +151,6 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,

4
src/mainboard/kontron/bsl6/devicetree.cb
View File

@ -2,10 +2,6 @@
chip soc/intel/skylake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"

5
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -154,11 +154,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/ocp/deltalake/devicetree.cb
View File

@ -48,10 +48,6 @@ chip soc/intel/xeon_sp/cpx
register "cstate_states" = "CSTATES_C1C6"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/ocp/tiogapass/devicetree.cb
View File

@ -40,10 +40,6 @@ chip soc/intel/xeon_sp/skx
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

2
src/mainboard/prodrive/hermes/devicetree.cb
View File

@ -1,6 +1,4 @@
chip soc/intel/cannonlake
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -191,11 +191,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
}"
# Lock Down CHIPSET_LOCKDOWN_COREBOOT
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

1
src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/cannonlake
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
/* Touchpad */
.i2c[0] = {
.speed = I2C_SPEED_FAST,

4
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
View File

@ -1,8 +1,4 @@
chip soc/intel/cannonlake
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit

5
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -151,11 +151,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -154,11 +154,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \

4
src/mainboard/siemens/chili/variants/base/devicetree.cb
View File

@ -7,10 +7,6 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/siemens/chili/variants/chili/devicetree.cb
View File

@ -7,10 +7,6 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

4
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
View File

@ -135,10 +135,6 @@ chip soc/intel/elkhartlake
register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
register "PchTsnGbeSgmiiEnable" = "1"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device

5
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -26,11 +26,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end

1
src/mainboard/system76/gaze15/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,

1
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
/* Touchpad */
.i2c[0] = {
.speed = I2C_SPEED_FAST,

1
src/mainboard/system76/oryp5/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,

1
src/mainboard/system76/oryp6/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,

1
src/mainboard/system76/whl-u/devicetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/cannonlake
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,

4
src/soc/intel/common/block/include/intelblocks/cfg.h
View File

@ -8,8 +8,8 @@
#include <intelblocks/mmc.h>
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
CHIPSET_LOCKDOWN_COREBOOT = 0, /* coreboot handles locking */
CHIPSET_LOCKDOWN_FSP, /* FSP handles locking per UPDs */
};
/*