soc/intel/cannonlake: Define soc_intel_cannonlake_config
- Populate soc_intel_cannonlake_config - Add usb.h and vr_config.h for CannonLake Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Pratik Prajapati
Aaron Durbin
parent
4bd68b8e4f
commit
0f2f069b4f
@ -20,17 +20,172 @@
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#include <intelblocks/gspi.h>
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#include <stdint.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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struct soc_intel_cannonlake_config {
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/* GSPI */
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struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/* Interrupt Routing configuration.
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* If bit7 is 1, the interrupt is disabled. */
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/* GPE configuration */
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uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
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uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
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uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
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uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form GPP_[A:G] or GPD. */
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uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable;
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int deep_s5_enable;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
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* DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin */
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uint32_t deep_sx_config;
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/* TCC activation offset */
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uint32_t tcc_offset;
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uint64_t PlatformMemorySize;
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uint8_t SmramMask;
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uint8_t MrcFastBoot;
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uint32_t TsegSize;
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uint16_t MmioSize;
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/* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t DdrFreqLimit;
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/* SAGV Low Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvLow;
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/* SAGV Mid Frequency Selections in Mhz.
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* Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
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uint16_t FreqSaGvMid;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* When enabled memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */
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uint8_t SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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/* LAN controller. 1:Enable, 0:Disable */
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uint8_t PchLanEnable;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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uint8_t XdciEnable;
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uint8_t SsicPortEnable;
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/* SATA related */
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uint8_t SataEnable;
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uint8_t SataMode;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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/* Audio related */
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uint8_t PchHdaEnable;
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uint8_t PchHdaDspEnable;
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/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
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uint8_t PchHdaAudioLinkHda;
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/* Pcie Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
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/* SMBus */
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uint8_t SmbusEnable;
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/* eMMC and SD */
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uint8_t ScsEmmcEnabled;
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uint8_t ScsEmmcHs400Enabled;
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uint8_t PchScsEmmcHs400TuningRequired;
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uint8_t ScsSdCardEnabled;
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uint8_t ScsUfsEnabled;
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/* Integrated Sensor */
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uint8_t PchIshEnable;
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/* Heci related */
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uint8_t Heci3Enabled;
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/* Gfx related */
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uint8_t IgdDvmt50PreAlloc;
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uint8_t InternalGfx;
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uint8_t SkipExtGfxScan;
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uint32_t GraphicsConfigPtr;
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uint8_t Device4Enable;
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/* GPIO IRQ Select. The valid value is 14 or 15 */
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uint8_t GpioIrqRoute;
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/* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t SciIrqSelect;
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/* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
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uint8_t TcoIrqSelect;
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uint8_t TcoIrqEnable;
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enum {
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CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
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CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
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} chipset_lockdown;
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uint8_t SkipMpInit;
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/* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced */
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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/* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS */
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uint8_t HeciEnabled;
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/* PL2 Override value in Watts */
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uint32_t tdp_pl2_override;
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/* Intel Speed Shift Technology */
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uint8_t speed_shift_enable;
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/* Enable VR specific mailbox command
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* 00b - no VR specific cmd sent
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* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
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* 10b - VR specific cmd sent for PS4 exit issue
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* 11b - Reserved */
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uint8_t SendVrMbxCmd;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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};
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typedef struct soc_intel_cannonlake_config config_t;
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38
src/soc/intel/cannonlake/include/soc/usb.h
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38
src/soc/intel/cannonlake/include/soc/usb.h
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_USB_H_
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#define _SOC_USB_H_
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#include <stdint.h>
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struct usb2_port_config {
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uint8_t enable;
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uint8_t ocpin;
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uint8_t tx_bias;
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uint8_t tx_emp_enable;
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uint8_t pre_emp_bias;
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uint8_t pre_emp_bit;
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};
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struct usb3_port_config {
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uint8_t enable;
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uint8_t ocpin;
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uint8_t tx_de_emp;
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uint8_t tx_downscale_amp;
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};
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#endif
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69
src/soc/intel/cannonlake/include/soc/vr_config.h
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69
src/soc/intel/cannonlake/include/soc/vr_config.h
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@ -0,0 +1,69 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* VR Settings for each domain */
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#ifndef _SOC_VR_CONFIG_H_
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#define _SOC_VR_CONFIG_H_
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#include <fsp/api.h>
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struct vr_config {
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/* The below settings will take effect when this is set to 1
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* for that domain. */
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uint8_t vr_config_enable;
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/* Power State X current cuttof in 1/4 Amp increments
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* Range is 0-128A */
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uint16_t psi1threshold;
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uint16_t psi2threshold;
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uint16_t psi3threshold;
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/* Enable power state 3/4 for different domains */
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uint8_t psi3enable;
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uint8_t psi4enable;
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/* Imon slope correction. Specified in 1/100 increment
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* values. Range is 0-200. 125 = 1.25 */
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uint8_t imon_slope;
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/* Imon offset correction. Units 1/1000, Range 0-63999
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* For an offset = 12.580, use 12580. 0 = Auto */
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uint8_t imon_offset;
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/* VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A */
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uint16_t icc_max;
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/* VR Voltage Limit. Range is 0-7999mV */
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uint16_t voltage_limit;
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/* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */
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uint16_t ac_loadline;
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uint16_t dc_loadline;
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};
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/* VrConfig Settings for 4 domains
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* 0 = System Agent, 1 = IA Core,
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* 2 = GT unsliced, 3 = GT sliced */
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enum vr_domain {
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VR_SYSTEM_AGENT,
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VR_IA_CORE,
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VR_GT_UNSLICED,
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VR_GT_SLICED,
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NUM_VR_DOMAINS
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};
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#endif
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