mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP

In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, this CL enables both
the UFS controller and ISH.

TEST=Boot to kernel and check lspci output
     00:12.0 Serial controller: Intel Corporation Device 54fc
     00:12.7 Mass storage controller [0109]: Intel Corporation
     Device 54ff

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Meera Ravindranath
2022-03-08 16:17:29 +05:30
committed by Angel Pons
parent b37468a73c
commit 0f5b8ba53d

View File

@ -270,6 +270,8 @@ chip soc/intel/alderlake
device ref gspi0 on end
device ref p2sb on end
device ref emmc on end
device ref ish on end
device ref ufs on end
device ref hda on
chip drivers/intel/soundwire
device generic 0 on