sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

google/pyro: Update DPTF settings

Browse Source 
1. Update DPTF CPU/TSR1 passive trigger points.
   CPU  passive point: 80
   TSR1 passive point: 46

2. Update DPTF TRT Sample Period
   TSR1: 8s

BUG=chrome-os-partner:62133
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18174
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kevin Chiu 2017-01-19 15:25:15 +08:00 committed by Aaron Durbin
parent 35d7d361e3
commit 0f6d10ba8f
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl
View File

@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
#define DPTF_CPU_PASSIVE 57
#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 90
#define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 80
@ -29,7 +29,7 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Ambient"
#define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_PASSIVE 46
#define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 2
@ -61,7 +61,7 @@ Name (DTRT, Package () {
#endif
/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 550, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },