soc/intel/xeon_sp: Use fixed BDF for IBL

Integrated Boot Logic (IBL) codes doesn't support bootloader
controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden.
Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF)
by bootloader is not supported, because when P2SB is hidden the
register access is denied.

TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB

Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu
2024-03-19 02:06:30 +08:00
committed by Lean Sheng Tan
parent 45a670d223
commit 1043080900
3 changed files with 33 additions and 3 deletions

View File

@@ -4,6 +4,7 @@
#define _XEON_SP_SOC_UTIL_H_
#include <cpu/x86/msr.h>
#include <intelblocks/p2sb.h>
#include <soc/soc_util.h>
#define MEM_ADDR_64MB_SHIFT_BITS 26
@@ -27,6 +28,8 @@ bool is_ubox_stack_res(const xSTACK_RES *res);
bool is_ioat_iio_stack_res(const xSTACK_RES *res);
bool is_iio_cxl_stack_res(const xSTACK_RES *res);
void bios_done_msr(void *unused);
union p2sb_bdf soc_get_hpet_bdf(void);
union p2sb_bdf soc_get_ioapic_bdf(void);
enum xeonsp_cxl_mode get_cxl_mode(void);

View File

@@ -18,7 +18,6 @@
#include <soc/pci_devs.h>
#include <soc/soc_util.h>
#include <soc/util.h>
#include <intelblocks/p2sb.h>
#include "chip.h"
/* NUMA related ACPI table generation. SRAT, SLIT, etc */
@@ -283,7 +282,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm
// Add PCH IOAPIC
if (is_dev_on_domain0(iommu)) {
union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf();
union p2sb_bdf ioapic_bdf = soc_get_ioapic_bdf();
printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
"PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus,
ioapic_bdf.dev, ioapic_bdf.fn);
@@ -363,7 +362,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm
//BIT 15
if (num_hpets && (num_hpets != 0x1f) &&
(read32p(HPET_BASE_ADDRESS + 0x100) & (0x00008000))) {
union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf();
union p2sb_bdf hpet_bdf = soc_get_hpet_bdf();
printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, "
"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn);

View File

@@ -9,8 +9,10 @@
#include <device/pci_ids.h>
#include <intelblocks/cfg.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
#include <soc/chip_common.h>
#include <soc/pch_pci_devs.h>
#include <soc/pci_devs.h>
#include <soc/msr.h>
#include <soc/soc_util.h>
@@ -88,6 +90,32 @@ unsigned int soc_get_num_cpus(void)
return get_iio_uds()->SystemStatus.numCpus;
}
union p2sb_bdf soc_get_hpet_bdf(void)
{
if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
union p2sb_bdf bdf = {
.bus = HPET_BUS_NUM,
.dev = HPET_DEV_NUM,
.fn = HPET0_FUNC_NUM
};
return bdf;
}
return p2sb_get_hpet_bdf();
}
union p2sb_bdf soc_get_ioapic_bdf(void)
{
if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
union p2sb_bdf bdf = {
.bus = PCH_IOAPIC_BUS_NUMBER,
.dev = PCH_IOAPIC_DEV_NUM,
.fn = PCH_IOAPIC_FUNC_NUM
};
return bdf;
}
return p2sb_get_ioapic_bdf();
}
#if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */
void lock_pam0123(void)