soc/amd: Use common reset code for PHX & Glinda SoCs

This switches the Phoenix & Glinda SoCs to use the common reset code.

Cezanne and newer do not support warm reset, so use cold resets in all
cases (including the OS).

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/glinda/Kconfig

@@ -61,6 +61,7 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_BLOCK_PM			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2		# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_RESET
 	select SOC_AMD_COMMON_BLOCK_SMBUS		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_SMI			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_SMM			# TODO: Check if this is still correct

src/soc/amd/glinda/Makefile.inc

@@ -15,19 +15,16 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
-bootblock-y	+= reset.c
 bootblock-y	+= uart.c
 
 verstage-y	+= i2c.c
 verstage-y	+= espi_util.c
 verstage_x86-y	+= gpio.c
-verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
 romstage-y	+= gpio.c
 romstage-y	+= i2c.c
-romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
@@ -40,7 +37,6 @@ ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
-ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
 ramstage-y	+= xhci.c

src/soc/amd/glinda/fch.c

@@ -6,6 +6,7 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/gpio.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smi.h>
 #include <assert.h>
 #include <bootstate.h>
@@ -196,6 +197,7 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
+	set_resets_to_cold();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

src/soc/amd/glinda/reset.c

@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Move to common? */
-
-#include <arch/io.h>
-#include <cf9_reset.h>
-#include <reset.h>
-#include <soc/southbridge.h>
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/reset.h>
-
-void do_cold_reset(void)
-{
-	/* De-assert and then assert all PwrGood signals on CF9 reset. */
-	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
-		TOGGLE_ALL_PWR_GOOD);
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_warm_reset(void)
-{
-	/* Assert reset signals only. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_board_reset(void)
-{
-	do_cold_reset();
-}

src/soc/amd/phoenix/Kconfig

@@ -61,6 +61,7 @@ config SOC_AMD_PHOENIX
 	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2		# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_RESET
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMM

src/soc/amd/phoenix/Makefile.inc

@@ -15,19 +15,16 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
-bootblock-y	+= reset.c
 bootblock-y	+= uart.c
 
 verstage-y	+= i2c.c
 verstage-y	+= espi_util.c
 verstage_x86-y	+= gpio.c
-verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
 romstage-y	+= gpio.c
 romstage-y	+= i2c.c
-romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
@@ -40,7 +37,6 @@ ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
-ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
 ramstage-y	+= xhci.c

src/soc/amd/phoenix/fch.c

@@ -5,6 +5,7 @@
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/gpio.h>
 #include <amdblocks/pci_clk_req.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smi.h>
 #include <assert.h>
 #include <bootstate.h>
@@ -192,6 +193,7 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
+	set_resets_to_cold();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

src/soc/amd/phoenix/reset.c

@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Move to common? */
-
-#include <arch/io.h>
-#include <cf9_reset.h>
-#include <reset.h>
-#include <soc/southbridge.h>
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/reset.h>
-
-void do_cold_reset(void)
-{
-	/* De-assert and then assert all PwrGood signals on CF9 reset. */
-	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
-		TOGGLE_ALL_PWR_GOOD);
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_warm_reset(void)
-{
-	/* Assert reset signals only. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_board_reset(void)
-{
-	do_cold_reset();
-}