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soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

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Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nico Huber
2019-10-02 16:02:06 +02:00
committed by Nico Huber
parent 2b9035ed6e
commit 119ace0908
23 changed files with 171 additions and 50 deletions
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12
src/mainboard/purism/librem_whl/devicetree.cb
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@@ -293,12 +293,18 @@ chip soc/intel/cannonlake
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8 (WLAN)
device pci 1c.7 on # PCI Express Port 8 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10 (LAN)
device pci 1d.1 on # PCI Express Port 10 (LAN)
register "PcieRpSlotImplemented[9]" = "1"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (NVMe)
device pci 1d.4 on # PCI Express Port 13 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16