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soc/intel/xeon_sp: Use native CAR teardown

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This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.

Note that ramstage CPU init sets up different final MTRRs anyway.

TESTED on ocp/deltalake and ocp/tiogapass.

Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2020-12-08 13:21:49 +01:00 committed by Patrick Georgi
parent 98cc7830e7
commit 129ed0a264
2 changed files with 16 additions and 9 deletions
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2
src/soc/intel/xeon_sp/Kconfig
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@ -67,6 +67,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select X86_SMM_LOADER_VERSION2 select X86_SMM_LOADER_VERSION2
select REG_SCRIPT select REG_SCRIPT
select NO_FSP_TEMP_RAM_EXIT
select INTEL_CAR_NEM # For postcar only now
config MAINBOARD_USES_FSP2_0 config MAINBOARD_USES_FSP2_0
bool bool

23
src/soc/intel/xeon_sp/memmap.c
View File

@ -29,17 +29,22 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf) void fill_postcar_frame(struct postcar_frame *pcf)
{ {
/* const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
* We need to make sure ramstage will be run cached. At this uintptr_t cbmem_base;
* point exact location of ramstage in cbmem is not known. size_t cbmem_size;
* Instruct postcar to cache 16 megs under cbmem top which is
* a safe bet to cover ramstage.
*/
uintptr_t top_of_ram = (uintptr_t)cbmem_top();
/* Try account for the CBMEM region currently used and for future use */
cbmem_get_region((void **)&cbmem_base, &cbmem_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16 * MiB; printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK); /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */
cbmem_base -= 4 * MiB;
cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB);
/* Align the top to make sure we don't use too many MTRR's */
cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB);
postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */ /* Cache the TSEG region */
if (CONFIG(TSEG_STAGE_CACHE)) if (CONFIG(TSEG_STAGE_CACHE))
postcar_enable_tseg_cache(pcf); postcar_enable_tseg_cache(pcf);