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WIP: undo changes that might impact CPU PCIe

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Change-Id: Ied4e4ed4c11172a9bb1c7aa47787ba6fb7e72803
This commit is contained in:
Jeremy Soller
2020-11-18 20:27:00 -07:00
parent 18cb9b5ab0
commit 130a3b0281
5 changed files with 0 additions and 26 deletions
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6
src/soc/intel/tigerlake/acpi/pci_irqs.asl
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@@ -67,9 +67,6 @@ Name (PICP, Package () {
Package(){0x0007FFFF, 3, 0, 19 }, Package(){0x0007FFFF, 3, 0, 19 },
/* D6 */ /* D6 */
Package(){0x0006FFFF, 0, 0, 16 }, Package(){0x0006FFFF, 0, 0, 16 },
Package(){0x0006FFFF, 1, 0, 17 },
Package(){0x0006FFFF, 2, 0, 18 },
Package(){0x0006FFFF, 3, 0, 19 },
/* D5 */ /* D5 */
Package(){0x0005FFFF, 0, 0, 16 }, Package(){0x0005FFFF, 0, 0, 16 },
/* D4 */ /* D4 */
@@ -145,9 +142,6 @@ Name (PICN, Package () {
Package(){0x0007FFFF, 3, 0, 11 }, Package(){0x0007FFFF, 3, 0, 11 },
/* D6 */ /* D6 */
Package(){0x0006FFFF, 0, 0, 11 }, Package(){0x0006FFFF, 0, 0, 11 },
Package(){0x0006FFFF, 1, 0, 10 },
Package(){0x0006FFFF, 2, 0, 11 },
Package(){0x0006FFFF, 3, 0, 11 },
/* D5 */ /* D5 */
Package(){0x0005FFFF, 0, 0, 11 }, Package(){0x0005FFFF, 0, 0, 11 },
/* D4 */ /* D4 */

10
src/soc/intel/tigerlake/acpi/pcie.asl
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@@ -96,16 +96,6 @@ Method (IRQM, 1, Serialized) {
} }
} }
Device (PEG0)
{
Name (_ADR, 0x00060000)
Method (_PRT)
{
Return (IRQM (1))
}
}
Device (RP01) Device (RP01)
{ {
Name (_ADR, 0x001C0000) Name (_ADR, 0x001C0000)

1
src/soc/intel/tigerlake/chip.c
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@@ -66,7 +66,6 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_ROOT: return "MCHC";
case SA_DEVFN_CPU_PCIE: return "PEG0";
case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TCSS_XDCI: return "TXDC";
case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT0: return "TRP0";
case SA_DEVFN_TBT1: return "TRP1"; case SA_DEVFN_TBT1: return "TRP1";

6
src/soc/intel/tigerlake/fsp_params.c
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@@ -194,12 +194,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
sizeof(config->PcieRpClkReqDetect)); sizeof(config->PcieRpClkReqDetect));
/* TODO: CPU RP Configs */
for (i = 0; i < 4; i++) {
params->CpuPcieRpAdvancedErrorReporting[i] = 0;
params->CpuPcieRpPtmEnabled[i] = 0;
}
/* Enable xDCI controller if enabled in devicetree and allowed */ /* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) { if (dev) {

3
src/soc/intel/tigerlake/romstage/fsp_params.c
View File

@@ -212,9 +212,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
/* Disable clock req messaging */
m_cfg->CpuPcieRpClockReqMsgEnable = 0;
/* Change TmeEnable UPD value according to INTEL_TME Kconfig */ /* Change TmeEnable UPD value according to INTEL_TME Kconfig */
m_cfg->TmeEnable = CONFIG(INTEL_TME); m_cfg->TmeEnable = CONFIG(INTEL_TME);
} }