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mb/system76/adl-p: Add Darter Pro 8

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Change-Id: If337b7ad3a4433890d847b77614c0130511610a7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-06-21 15:14:53 -06:00
parent 1957255f5e
commit 137b12aee4
21 changed files with 851 additions and 0 deletions
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65
src/mainboard/system76/adl-p/Kconfig Normal file
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if BOARD_SYSTEM76_DARP8
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_BAT_THRESHOLDS
select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_MEASURED_BOOT
config MAINBOARD_DIR
default "system76/adl-p"
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
config CBFS_SIZE
default 0xA00000
config CONSOLE_POST
default y
config DIMM_SPD_SIZE
default 512
config POST_DEVICE
default n
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

2
src/mainboard/system76/adl-p/Kconfig.name Normal file
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config BOARD_SYSTEM76_DARP8
bool "darp8"

10
src/mainboard/system76/adl-p/Makefile.inc Normal file
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c

31
src/mainboard/system76/adl-p/acpi/backlight.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0)
{
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

13
src/mainboard/system76/adl-p/acpi/mainboard.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
}
}

46
src/mainboard/system76/adl-p/acpi/sleep.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < 6, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

6
src/mainboard/system76/adl-p/board_info.txt Normal file
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Vendor name: System76
Category: laptop
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

9
src/mainboard/system76/adl-p/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <mainboard/gpio.h>
void bootblock_mainboard_early_init(void)
{
mainboard_configure_early_gpios();
}

3
src/mainboard/system76/adl-p/cmos.default Normal file
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boot_option=Fallback
debug_level=Debug
me_state=Enable

39
src/mainboard/system76/adl-p/cmos.layout Normal file
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# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

92
src/mainboard/system76/adl-p/devicetree.cb Normal file
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chip soc/intel/alderlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
register "s0ix_enable" = "1"
# Enable C6 DRAM
register "enable_c6dram" = "1"
# Thermal
register "tcc_offset" = "8"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device ref system_agent on end
device ref igpu on
# DDIA is eDP, DDIB is HDMI
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
device ref tbt_pcie_rp0 on end
device ref shared_sram on end
device ref cnvi_wifi on
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on end
device ref sata on
register "sata_ports_enable[0]" = "1" # SSD1
register "sata_ports_dev_slp[0]" = "1" # GPP_H12 (SATA1_DEVSLP1)
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0e01" # AP/EC command
register "gen3_dec" = "0x00fc0f01" # AP/EC debug
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref hda on
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end
device ref smbus on end
device ref fast_spi on end
end
end

33
src/mainboard/system76/adl-p/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
#include <soc/intel/alderlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

9
src/mainboard/system76/adl-p/include/mainboard/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

24
src/mainboard/system76/adl-p/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};

2
src/mainboard/system76/adl-p/variants/darp8/board_info.txt Normal file
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Board name: darp8
Release year: 2022

BIN
src/mainboard/system76/adl-p/variants/darp8/data.vbt Normal file
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Binary file not shown.

227
src/mainboard/system76/adl-p/variants/darp8/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKE#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
PAD_NC(GPP_A6, NONE),
PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SATAGP0_PCIE_SSD2
PAD_CFG_GPO(GPP_A8, 1, PLTRST), // GPIO_LANRTD3
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1_SATA_SSD1
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
PAD_NC(GPP_A14, NONE),
PAD_NC(GPP_A15, NONE),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LID_SW#
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
PAD_NC(GPP_B2, NONE),
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
//PAD_CFG_GPI(GPP_B9, NONE, DEEP),
//PAD_CFG_GPI(GPP_B10, NONE, DEEP),
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
PAD_NC(GPP_B15, NONE),
PAD_CFG_GPO(GPP_B16, 1, PLTRST), // M2_SSD1_RST#
PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#_R
PAD_NC(GPP_B18, NONE), // NO REBOOT strap
//PAD_CFG_GPI(GPP_B19, NONE, DEEP),
//PAD_CFG_GPI(GPP_B20, NONE, DEEP),
//PAD_CFG_GPI(GPP_B21, NONE, DEEP),
//PAD_CFG_GPI(GPP_B22, NONE, DEEP),
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC CLOCK FREQ strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_TP
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA_TP
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK_R
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA_R
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // ESPI OR EC LESS strap
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
//PAD_NC(GPP_C8, NONE),
//PAD_NC(GPP_C9, NONE),
//PAD_NC(GPP_C10, NONE),
//PAD_NC(GPP_C11, NONE),
//PAD_NC(GPP_C12, NONE),
//PAD_NC(GPP_C13, NONE),
//PAD_NC(GPP_C14, NONE),
//PAD_NC(GPP_C15, NONE),
//PAD_NC(GPP_C16, NONE),
//PAD_NC(GPP_C17, NONE),
//PAD_NC(GPP_C18, NONE),
//PAD_NC(GPP_C19, NONE),
//PAD_NC(GPP_C20, NONE),
//PAD_NC(GPP_C21, NONE),
//PAD_NC(GPP_C22, NONE),
//PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPO(GPP_D4, 1, DEEP), // GPIO_LAN_EN
//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP), // Board ID
PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
PAD_CFG_GPO(GPP_D15, 1, DEEP), // GPP_D2_SDCARD_RST#
PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_CFG_GPI(GPP_D19, NONE, DEEP), // SATA_LED#
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_NC(GPP_E2, NONE),
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WLAN_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // GPP_E10_STRAP
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // GPP_E11_STRAP
PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_NC(GPP_E13, NONE),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_CFG_GPI(GPP_E16, NONE, DEEP), // SDCARD_WAKE#
PAD_NC(GPP_E17, NONE),
PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
//PAD_CFG_GPI(GPP_F8, NONE, DEEP),
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
PAD_NC(GPP_F11, NONE), // BOARD_ID3
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // BOARD_ID1
PAD_NC(GPP_F15, NONE), // BOARD_ID2
PAD_NC(GPP_F16, NONE),
PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ6#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_NC(GPP_H1, NONE),
PAD_NC(GPP_H2, NONE),
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000), // SATA1_DEVSLP1
PAD_NC(GPP_H13, NONE),
//PAD_CFG_GPI(GPP_H14, NONE, DEEP),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
//PAD_CFG_GPI(GPP_H16, NONE, DEEP),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE), // DMIC_CLK
PAD_NC(GPP_R7, NONE), // DMIC_DAT
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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src/mainboard/system76/adl-p/variants/darp8/gpio_early.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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src/mainboard/system76/adl-p/variants/darp8/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256,
0x15587716,
11,
AZALIA_SUBVENDOR(0, 0x15587716),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/system76/adl-p/variants/darp8/overridetree.cb Normal file
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chip soc/intel/alderlake
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,
.tdp_pl4 = 65,
}"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_A"
register "pmc_gpe0_dw1" = "PMC_GPP_R"
register "pmc_gpe0_dw2" = "PMC_GPD"
device domain 0 on
subsystemid 0x1558 0x7716 inherit
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
register "srcclk_pin" = "0" # SSD2_CLKREQ#
device generic 0 on end
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 TBT Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Motherboard
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Multi Board
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen 2)
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunderbolt)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Motherboard
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH2
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 UJ_USB1""
register "type" = "UPC_TYPE_A"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB3_1""
register "type" = "UPC_TYPE_A"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Fingerprint""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_TYPEC2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB3_1""
register "type" = "UPC_TYPE_A"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC1 CH0""
register "type" = "UPC_TYPE_A"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC1 CH1""
register "type" = "UPC_TYPE_A"
device ref usb3_port3 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref pcie_rp5 on
# PCIe RP#5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST#_R
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe RP#6 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp8 on
# PCIe RP#8 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(8)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp9 on
# PCIe RP#9 x4, Clock 4 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
register "srcclk_pin" = "4" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
# J_TYPEC2
use usb2_port6 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
end
end
end
end
end

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src/mainboard/system76/adl-p/variants/darp8/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
.rcomp = { .resistor = 100, },
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}