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Enable PCIE debug info and disable fake devices under thunderbolt controller

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This commit is contained in:
Jeremy Soller
2019-10-09 15:11:14 -06:00
parent 57d53e9635
commit 14fa57aa54
3 changed files with 36 additions and 41 deletions
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68
src/drivers/thunderbolt/thunderbolt.c
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@@ -22,47 +22,47 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
static void slot_dev_read_resources(struct device *dev)
{
struct resource *resource;
resource = new_resource(dev, 0x10);
resource->size = 1 << 28;
resource->align = 22;
resource->gran = 22;
resource->limit = 0xffffffff;
resource->flags |= IORESOURCE_MEM;
resource = new_resource(dev, 0x14);
resource->size = 1 << 28;
resource->align = 22;
resource->gran = 22;
resource->limit = 0xffffffff;
resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource = new_resource(dev, 0x18);
resource->size = 1 << 13;
resource->align = 12;
resource->gran = 12;
resource->limit = 0xffff;
resource->flags |= IORESOURCE_IO;
}
static struct device_operations slot_dev_ops = {
.read_resources = slot_dev_read_resources,
};
// static void slot_dev_read_resources(struct device *dev)
// {
// struct resource *resource;
//
// resource = new_resource(dev, 0x10);
// resource->size = 1 << 28;
// resource->align = 22;
// resource->gran = 22;
// resource->limit = 0xffffffff;
// resource->flags |= IORESOURCE_MEM;
//
// resource = new_resource(dev, 0x14);
// resource->size = 1 << 28;
// resource->align = 22;
// resource->gran = 22;
// resource->limit = 0xffffffff;
// resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
//
// resource = new_resource(dev, 0x18);
// resource->size = 1 << 13;
// resource->align = 12;
// resource->gran = 12;
// resource->limit = 0xffff;
// resource->flags |= IORESOURCE_IO;
// }
//
// static struct device_operations slot_dev_ops = {
// .read_resources = slot_dev_read_resources,
// };
static void tbt_pciexp_scan_bridge(struct device *dev) {
printk(BIOS_DEBUG, "tbt_pciexp_scan_bridge\n");
printk(BIOS_DEBUG, "tbt_pciexp_scan_bridge %s\n", dev_path(dev));
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
/* Add dummy slot to preserve resources */
struct device *slot;
struct device_path slot_path = { .type = DEVICE_PATH_NONE };
slot = alloc_dev(dev->link_list, &slot_path);
slot->ops = &slot_dev_ops;
// struct device *slot;
// struct device_path slot_path = { .type = DEVICE_PATH_NONE };
// slot = alloc_dev(dev->link_list, &slot_path);
// slot->ops = &slot_dev_ops;
}
static struct pci_operations pcie_ops = {

1
src/mainboard/system76/cml-u/Kconfig
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@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
# select MAINBOARD_HAS_SPI_TPM_CR50
# select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select PCIE_DEBUG_INFO
select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COMMON_BLOCK_HDA

8
src/mainboard/system76/cml-u/devicetree.cb
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@@ -209,13 +209,7 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 on
chip drivers/thunderbolt
device pci 00.0 on end # Thunderbolt 3 NHI
device pci 01.0 on end # Thunderbolt 3 PCI bridge
device pci 02.0 on end # Thunderbolt 3 USB controller
end
end # PCI Express Port 1
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4