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soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7

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Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was
not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor
Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping".

Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya 2024-02-22 20:37:17 +05:30 committed by Felix Held
parent a99b580c75
commit 15d55439da
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/glinda/include/soc/southbridge.h
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@ -87,7 +87,7 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_OUTPUT_AVAILABLE 4
#define GPP_CLK_OUTPUT_AVAILABLE 7
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)