cml-u: sync with lemp9, enable i2c-hid
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@@ -2,8 +2,8 @@ if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ADD_FSP_BINARIES
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select EC_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select USE_BLOBS
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select USE_OPTION_TABLE
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select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
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@@ -116,13 +116,17 @@ Device (EC0)
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Method (_Q11, 0, NotSerialized) // Brightness Down
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{
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Debug = "EC: Brightness Down"
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^^^^HIDD.HPEM (20)
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if (^^^^HIDD.HRDY) {
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^^^^HIDD.HPEM (20)
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}
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}
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Method (_Q12, 0, NotSerialized) // Brightness Up
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{
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Debug = "EC: Brightness Up"
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^^^^HIDD.HPEM (19)
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if (^^^^HIDD.HRDY) {
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^^^^HIDD.HPEM (19)
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}
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}
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Method (_Q13, 0, NotSerialized) // Camera Toggle
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@@ -133,10 +137,10 @@ Device (EC0)
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Method (_Q14, 0, NotSerialized) // Airplane Mode
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{
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Debug = "EC: Airplane Mode"
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// Only send HIDD message when hardware airplane mode not in use
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If (ECOS == 2) {
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if (^^^^HIDD.HRDY) {
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^^^^HIDD.HPEM (8)
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}
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// TODO: hardware airplane mode
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}
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Method (_Q15, 0, NotSerialized) // Suspend Button
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@@ -2,6 +2,11 @@ chip soc/intel/cannonlake
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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@@ -19,8 +24,10 @@ chip soc/intel/cannonlake
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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register "tdp_pl1_override" = "15"
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register "tdp_pl2_override" = "25"
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register "power_limits_config" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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}"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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@@ -33,6 +40,22 @@ chip soc/intel/cannonlake
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#register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Serial I/O
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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# SATA
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register "SataMode" = "Sata_AHCI"
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register "SataSalpSupport" = "0"
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@@ -127,7 +150,7 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[5]" = "5"
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# Misc
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register "Device4Enable" = "0"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "Heci3Enabled" = "0"
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register "AcousticNoiseMitigation" = "1"
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@@ -183,7 +206,7 @@ chip soc/intel/cannonlake
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 04.0 on end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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@@ -195,7 +218,16 @@ chip soc/intel/cannonlake
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device pci 14.3 on end # CNVi wifi
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#end
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device pci 14.5 off end # SDCard
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device pci 15.0 off end # I2C #0
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device pci 15.0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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@@ -250,8 +250,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPP_C22),
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// NC
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PAD_CFG_NC(GPP_C23),
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// TP_ATTN#
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PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
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// GPP_D
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// SPI1
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