Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
@@ -1,51 +0,0 @@
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if BOARD_AMD_DBM690T
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_S1G1
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_RS690
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select SOUTHBRIDGE_AMD_SB600
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select SUPERIO_ITE_IT8712F
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select HAVE_ACPI_TABLES
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select HAVE_MP_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_OPTION_TABLE
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select BOARD_ROMSIZE_KB_1024
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select QRANK_DIMM_SUPPORT
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default amd/dbm690t
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "DBM690T"
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config MAX_CPUS
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int
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default 2
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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endif # BOARD_AMD_DBM690T
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@@ -1,2 +0,0 @@
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config BOARD_AMD_DBM690T
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bool "DBM690T (Herring)"
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@@ -1,240 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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Scope (_SB) {
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Device(PCI0) {
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Device(IDEC) {
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Name(_ADR, 0x00140001)
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#include "ide.asl"
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}
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}
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}
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*/
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/* Some timing tables */
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Name(UDTT, Package(){ /* Udma timing table */
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120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
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})
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Name(MDTT, Package(){ /* MWDma timing table */
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480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
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})
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Name(POTT, Package(){ /* Pio timing table */
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600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
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})
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/* Some timing register value tables */
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Name(MDRT, Package(){ /* MWDma timing register table */
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0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
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})
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Name(PORT, Package(){
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0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
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})
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OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
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Field(ICRG, AnyAcc, NoLock, Preserve)
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{
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PPTS, 8, /* Primary PIO Slave Timing */
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PPTM, 8, /* Primary PIO Master Timing */
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OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
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PMTM, 8, /* Primary MWDMA Master Timing */
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OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
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OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
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PPSM, 4, /* Primary PIO slave Mode */
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OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
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OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
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PDSM, 4, /* Primary UltraDMA Mode */
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}
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Method(GTTM, 1) /* get total time*/
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{
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Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
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Increment(Local0)
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Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
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Increment(Local1)
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Return(Multiply(30, Add(Local0, Local1)))
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}
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Device(PRID)
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{
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Name (_ADR, Zero)
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Method(_GTM, 0)
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{
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NAME(OTBF, Buffer(20) { /* out buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
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CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
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/* Just return if the channel is disabled */
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If(And(PPCR, 0x01)) { /* primary PIO control */
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Return(OTBF)
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}
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/* Always tell them independent timing available and IOChannelReady used on both drives */
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Or(BFFG, 0x1A, BFFG)
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Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
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Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
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If(And(PDCR, 0x01)) { /* It's under UDMA mode */
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Or(BFFG, 0x01, BFFG)
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Store(DerefOf(Index(UDTT, PDMM)), DSD0)
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}
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Else {
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Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
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}
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If(And(PDCR, 0x02)) { /* It's under UDMA mode */
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Or(BFFG, 0x04, BFFG)
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Store(DerefOf(Index(UDTT, PDSM)), DSD1)
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}
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Else {
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Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
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}
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Return(OTBF) /* out buffer */
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} /* End Method(_GTM) */
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Method(_STM, 3, NotSerialized)
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{
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NAME(INBF, Buffer(20) { /* in buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
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CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(INBF, 16, BFFG) /*buffer flag */
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Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
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Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
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Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
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Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
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Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
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Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
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If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDMM,)
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Or(PDCR, 0x01, PDCR)
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}
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Else {
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If(LNotEqual(DSD0, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTM)
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}
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}
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If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDSM,)
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Or(PDCR, 0x02, PDCR)
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}
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Else {
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If(LNotEqual(DSD1, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTS)
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}
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}
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/* Return(INBF) */
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} /*End Method(_STM) */
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Device(MST)
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{
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Name(_ADR, 0)
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Method(_GTF) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xA0, CMDA)
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Store(0xA0, CMDB)
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Store(0xA0, CMDC)
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Or(PPMM, 0x08, POMD)
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If(And(PDCR, 0x01)) {
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Or(PDMM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTM),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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}
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Return(CMBF)
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}
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} /* End Device(MST) */
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Device(SLAV)
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{
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Name(_ADR, 1)
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Method(_GTF) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xB0, CMDA)
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Store(0xB0, CMDB)
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Store(0xB0, CMDC)
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Or(PPSM, 0x08, POMD)
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If(And(PDCR, 0x02)) {
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Or(PDSM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTS),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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||||
}
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||||
Return(CMBF)
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}
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} /* End Device(SLAV) */
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||||
}
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||||
@@ -1,254 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
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||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS690 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0012FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 2, INTC, 0 },
|
||||
Package(){0x0013FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS690 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
Package(){0x0006FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
Package(){0x0007FFFF, 0, 0, 19 },
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0012FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0013FFFF, 0, 0, 16 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 2, 0, 18 },
|
||||
Package(){0x0013FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00120000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,157 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,51 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include "northbridge/amd/amdk8/acpi.h"
|
||||
#include <arch/cpu.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
get_bus_conf();
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB600 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,3 +0,0 @@
|
||||
Board name: dbM690T (Herring)
|
||||
Category: eval
|
||||
Board URL: http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf
|
||||
@@ -1,69 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,121 +0,0 @@
|
||||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_S1G1
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3050 inherit
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge
|
||||
chip southbridge/amd/rs690
|
||||
device pci 0.0 on end # HT 0x7910
|
||||
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
|
||||
device pci 5.0 on end # Internal Graphics 0x791F
|
||||
end
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x791b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x7914
|
||||
device pci 5.0 on end # PCIE P2P bridge 0x7915
|
||||
device pci 6.0 on end # PCIE P2P bridge 0x7916
|
||||
device pci 7.0 on end # PCIE P2P bridge 0x7917
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
register "gpp_configuration" = "4"
|
||||
register "port_enable" = "0xfc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 12.0 on end # SATA 0x4380
|
||||
device pci 13.0 on end # USB 0x4387
|
||||
device pci 13.1 on end # USB 0x4388
|
||||
device pci 13.2 on end # USB 0x4389
|
||||
device pci 13.3 on end # USB 0x438a
|
||||
device pci 13.4 on end # USB 0x438b
|
||||
device pci 13.5 on end # USB 2 0x4386
|
||||
device pci 14.0 on # SM 0x4385
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x438c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x438d
|
||||
chip superio/ite/it8712f
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # EC
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio/ite/it8712f
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # ACI 0x4382
|
||||
device pci 14.6 on end # MCI 0x438e
|
||||
register "hda_viddid" = "0x10ec0882"
|
||||
end #southbridge/amd/sb600
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end #northbridge/amd/amdk8
|
||||
end #domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,197 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include "southbridge/amd/sb600/sb600.h"
|
||||
|
||||
/*extern*/ u16 pm_base = 0x800;
|
||||
/* pm_base should be set in sb ACPI */
|
||||
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
|
||||
* registers into 32 bytes limit.
|
||||
* */
|
||||
|
||||
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
|
||||
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
|
||||
#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
|
||||
#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
|
||||
#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
|
||||
#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
pm_base &= 0xFFFF;
|
||||
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = 244;
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 0;
|
||||
|
||||
fadt->firmware_ctrl = (u32) facs;
|
||||
fadt->dsdt = (u32) dsdt;
|
||||
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0xe2;
|
||||
|
||||
pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
|
||||
pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
|
||||
pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
|
||||
pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
|
||||
pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
|
||||
pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
|
||||
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
|
||||
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
|
||||
|
||||
/* CpuControl is in \_PR.CP00, 6 bytes */
|
||||
pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
|
||||
pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
|
||||
|
||||
pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
|
||||
pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
|
||||
|
||||
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
|
||||
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
|
||||
|
||||
pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
|
||||
* the contents of the PM registers at
|
||||
* index 20-2B to decode ACPI I/O address.
|
||||
* AcpiSmiEn & SmiCmdEn*/
|
||||
pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
|
||||
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
|
||||
|
||||
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
|
||||
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
|
||||
fadt->gpe0_blk = ACPI_GPE0_BLK;
|
||||
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
|
||||
fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x0001c1a5;/* 0x25; */
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32) facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32) dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
@@ -1,109 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u8 bus_rs690[8];
|
||||
u8 bus_sb600[2];
|
||||
u32 apicid_sb600;
|
||||
|
||||
/*
|
||||
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
* You may need to preset pci1234 for HTIO board,
|
||||
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
*/
|
||||
u32 pci1234x[] = {
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
/*
|
||||
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||
* assume every chain only have 4 ht device at most
|
||||
*/
|
||||
u32 hcdnx[] = {
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
u32 sbdn_rs690;
|
||||
u32 sbdn_sb600;
|
||||
|
||||
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
struct device *dev;
|
||||
int i;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
sbdn_rs690 = sysconf.sbdn;
|
||||
sbdn_sb600 = 0;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
bus_sb600[i] = 0;
|
||||
}
|
||||
for (i = 0; i < 8; i++) {
|
||||
bus_rs690[i] = 0;
|
||||
}
|
||||
|
||||
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
bus_sb600[0] = bus_rs690[0];
|
||||
|
||||
/* sb600 */
|
||||
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
|
||||
if (dev) {
|
||||
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
|
||||
/* rs690 */
|
||||
for (i = 1; i < 8; i++) {
|
||||
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
|
||||
if (dev) {
|
||||
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb600 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern u8 bus_rs690[8];
|
||||
extern u8 bus_sb600[2];
|
||||
extern unsigned long sbdn_sb600;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_sb600[0];
|
||||
pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,190 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb600/sb600.h>
|
||||
|
||||
#define ADT7461_ADDRESS 0x4C
|
||||
#define ARA_ADDRESS 0x0C /* Alert Response Address */
|
||||
#define SMBUS_IO_BASE 0x1000
|
||||
|
||||
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
||||
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
||||
u8 val);
|
||||
#define ADT7461_read_byte(address) \
|
||||
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
||||
#define ARA_read_byte(address) \
|
||||
do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
|
||||
#define ADT7461_write_byte(address, val) \
|
||||
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
|
||||
|
||||
|
||||
/********************************************************
|
||||
* dbm690t uses a BCM5789 as on-board NIC.
|
||||
* It has a pin named LOW_POWER to enable it into LOW POWER state.
|
||||
* In order to run NIC, we should let it out of Low power state. This pin is
|
||||
* controlled by sb600 GPM3.
|
||||
* RRG4.2.3 GPM as GPIO
|
||||
* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
|
||||
* I/O C50, C51, C52, PM I/O94, 95, 96.
|
||||
* RRG4.2.3.1 GPM pins as Input
|
||||
* RRG4.2.3.2 GPM pins as Output
|
||||
********************************************************/
|
||||
static void enable_onboard_nic(void)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
printk(BIOS_INFO, "%s.\n", __func__);
|
||||
|
||||
/* set index register 0C50h to 13h (miscellaneous control) */
|
||||
outb(0x13, 0xC50); /* CMIndex */
|
||||
|
||||
/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
|
||||
byte = inb(0xC51);
|
||||
byte &= 0x3F;
|
||||
byte |= 0x40;
|
||||
outb(byte, 0xC51);
|
||||
|
||||
/* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
|
||||
byte = inb(0xC52);
|
||||
byte &= ~0x8;
|
||||
outb(byte, 0xC52);
|
||||
|
||||
/* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
|
||||
byte = inb(0xC51);
|
||||
byte &= 0x3F;
|
||||
byte |= 0x80; /* 7:6=10 */
|
||||
outb(byte, 0xC51);
|
||||
|
||||
/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
|
||||
byte = inb(0xC52);
|
||||
byte &= ~0x8;
|
||||
outb(byte, 0xC52);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
|
||||
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
|
||||
* get the cable type, 40 pin or 80 pin?
|
||||
********************************************************/
|
||||
static void get_ide_dma66(void)
|
||||
{
|
||||
u8 byte;
|
||||
struct device *sm_dev;
|
||||
struct device *ide_dev;
|
||||
|
||||
printk(BIOS_INFO, "%s.\n", __func__);
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
|
||||
byte = pci_read_config8(sm_dev, 0xA9);
|
||||
byte |= (1 << 5); /* Set Gpio9 as input */
|
||||
pci_write_config8(sm_dev, 0xA9, byte);
|
||||
|
||||
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
|
||||
byte = pci_read_config8(ide_dev, 0x56);
|
||||
byte &= ~(7 << 0);
|
||||
if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
|
||||
byte |= 2 << 0; /* mode 2 */
|
||||
else
|
||||
byte |= 5 << 0; /* mode 5 */
|
||||
pci_write_config8(ide_dev, 0x56, byte);
|
||||
}
|
||||
|
||||
/*
|
||||
* set thermal config
|
||||
*/
|
||||
static void set_thermal_config(void)
|
||||
{
|
||||
u8 byte;
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* set ADT 7461 */
|
||||
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
|
||||
ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
|
||||
ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
|
||||
ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
|
||||
|
||||
ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
|
||||
ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
|
||||
|
||||
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
|
||||
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
|
||||
printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
|
||||
|
||||
/* sb600 settings for thermal config */
|
||||
/* set SB600 GPIO 64 to GPIO with pull-up */
|
||||
byte = pm2_ioread(0x42);
|
||||
byte &= 0x3f;
|
||||
pm2_iowrite(0x42, byte);
|
||||
|
||||
/* set GPIO 64 to input */
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
word = pci_read_config16(sm_dev, 0x56);
|
||||
word |= 1 << 7;
|
||||
pci_write_config16(sm_dev, 0x56, word);
|
||||
|
||||
/* set GPIO 64 internal pull-up */
|
||||
byte = pm2_ioread(0xf0);
|
||||
byte &= 0xee;
|
||||
pm2_iowrite(0xf0, byte);
|
||||
|
||||
/* set Talert to be active low */
|
||||
byte = pm_ioread(0x67);
|
||||
byte &= ~(1 << 5);
|
||||
pm_iowrite(0x67, byte);
|
||||
|
||||
/* set Talert to generate ACPI event */
|
||||
byte = pm_ioread(0x3c);
|
||||
byte &= 0xf3;
|
||||
pm_iowrite(0x3c, byte);
|
||||
|
||||
/* THERMTRIP pin */
|
||||
/* byte = pm_ioread(0x68);
|
||||
* byte |= 1 << 3;
|
||||
* pm_iowrite(0x68, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x55);
|
||||
* byte |= 1 << 0;
|
||||
* pm_iowrite(0x55, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x67);
|
||||
* byte &= ~( 1 << 6);
|
||||
* pm_iowrite(0x67, byte);
|
||||
*/
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in dbm690t board.
|
||||
* This function called early than rs690_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
|
||||
|
||||
enable_onboard_nic();
|
||||
get_ide_dma66();
|
||||
set_thermal_config();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,111 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
extern u8 bus_rs690[8];
|
||||
extern u8 bus_sb600[2];
|
||||
|
||||
extern u32 apicid_sb600;
|
||||
|
||||
extern u32 sbdn_rs690;
|
||||
extern u32 sbdn_sb600;
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(bus_sb600[0],
|
||||
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb600,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
static void setup_dbm690t_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8712f/it8712f.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "southbridge/amd/rs690/early_setup.c"
|
||||
#include "southbridge/amd/sb600/early_setup.c"
|
||||
#include <northbridge/amd/amdk8/f.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
|
||||
|
||||
void memreset(int controllers, const struct mem_controller *ctrl) { }
|
||||
void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include <northbridge/amd/amdk8/amdk8.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
|
||||
int needs_reset = 0;
|
||||
u32 bsp_apicid = 0;
|
||||
msr_t msr;
|
||||
struct cpuid_result cpuid1;
|
||||
struct sys_info *sysinfo = &sysinfo_car;
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
/* sb600_lpc_port80(); */
|
||||
sb600_pci_port80();
|
||||
}
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
enable_rs690_dev8();
|
||||
sb600_lpc_init();
|
||||
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
|
||||
|
||||
setup_dbm690t_resource_map();
|
||||
|
||||
setup_coherent_ht_domain();
|
||||
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
/* It is said that we should start core1 after all core0 launched */
|
||||
wait_all_core0_started();
|
||||
start_other_cores();
|
||||
#endif
|
||||
wait_all_aps_started(bsp_apicid);
|
||||
|
||||
ht_setup_chains_x(sysinfo);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs690_early_setup();
|
||||
sb600_early_setup();
|
||||
|
||||
/* Check to see if processor is capable of changing FIDVID */
|
||||
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6) == 0x6) {
|
||||
/* Read FIDVID_STATUS */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
|
||||
enable_fid_change();
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
|
||||
}
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
rs690_htinit();
|
||||
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now; */
|
||||
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
|
||||
sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
rs690_before_pci_init();
|
||||
sb600_before_pci_init();
|
||||
}
|
||||
@@ -1,66 +0,0 @@
|
||||
if BOARD_AMD_MAHOGANY
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM2
|
||||
select DIMM_DDR2
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SUPERIO_ITE_IT8718F
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_OPTION_TABLE
|
||||
select LIFT_BSP_APIC_ID
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select GFXUMA
|
||||
select QRANK_DIMM_SUPPORT
|
||||
select SET_FIDVID
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/mahogany
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MAHOGANY"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "1002,9615"
|
||||
|
||||
endif # BOARD_AMD_MAHOGANY
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_MAHOGANY
|
||||
bool "Mahogany"
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0, Serialized)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, Serialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,307 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0012FFFF, 2, INTC, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTD, 0 },
|
||||
Package(){0x0013FFFF, 2, INTA, 0 },
|
||||
|
||||
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0012FFFF, 2, 0, 18 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0013FFFF, 2, 0, 16 },
|
||||
|
||||
/* Package(){0x00140000, 0, 0, 16 }, */
|
||||
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,157 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include "northbridge/amd/amdk8/acpi.h"
|
||||
#include <arch/cpu.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
get_bus_conf();
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,3 +0,0 @@
|
||||
Board name: DB780E (Mahogany)
|
||||
Category: eval
|
||||
ROM protocol: SPI
|
||||
@@ -1,69 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,121 +0,0 @@
|
||||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3060 inherit
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 on end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end #
|
||||
device pci a.0 on end #
|
||||
register "gppsb_configuration" = "1" # Configuration B
|
||||
register "gpp_configuration" = "3" # Configuration D default
|
||||
register "port_enable" = "0x6fc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "1"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8718f
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # EC
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio/ite/it8718f
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # USB 2
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/sb700
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end #northbridge/amd/amdk8
|
||||
end #domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,109 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u8 bus_rs780[11];
|
||||
u8 bus_sb700[2];
|
||||
u32 apicid_sb700;
|
||||
|
||||
/*
|
||||
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
* You may need to preset pci1234 for HTIO board,
|
||||
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
*/
|
||||
u32 pci1234x[] = {
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
/*
|
||||
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||
* assume every chain only have 4 ht device at most
|
||||
*/
|
||||
u32 hcdnx[] = {
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
u32 sbdn_rs780;
|
||||
u32 sbdn_sb700;
|
||||
|
||||
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
struct device *dev;
|
||||
int i;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
sbdn_rs780 = sysconf.sbdn;
|
||||
sbdn_sb700 = 0;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
bus_sb700[i] = 0;
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
bus_rs780[i] = 0;
|
||||
}
|
||||
|
||||
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
bus_sb700[0] = bus_rs780[0];
|
||||
|
||||
/* sb700 */
|
||||
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
|
||||
if (dev) {
|
||||
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
|
||||
/* rs780 */
|
||||
for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
|
||||
if (dev) {
|
||||
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb700 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern u8 bus_rs780[8];
|
||||
extern u8 bus_sb700[2];
|
||||
extern unsigned long sbdn_sb700;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_sb700[0];
|
||||
pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,77 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "southbridge/amd/sb700/sb700.h"
|
||||
#include "southbridge/amd/sb700/smbus.h"
|
||||
|
||||
void set_pcie_dereset(void);
|
||||
void set_pcie_reset(void);
|
||||
u8 is_dev3_present(void);
|
||||
/*
|
||||
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
|
||||
* pull it up before training the slot.
|
||||
***/
|
||||
void set_pcie_dereset()
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
|
||||
word = pci_read_config16(sm_dev, 0xA8);
|
||||
word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
|
||||
word &= ~((1 << 8) | (1 << 10));
|
||||
pci_write_config16(sm_dev, 0xA8, word);
|
||||
}
|
||||
|
||||
void set_pcie_reset()
|
||||
{
|
||||
u16 word;
|
||||
struct device *sm_dev;
|
||||
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
|
||||
word = pci_read_config16(sm_dev, 0xA8);
|
||||
word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
|
||||
word &= ~((1 << 8) | (1 << 10));
|
||||
pci_write_config16(sm_dev, 0xA8, word);
|
||||
}
|
||||
|
||||
u8 is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
/*************************************************
|
||||
* enable the dedicated function in mahogany board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,112 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
extern u8 bus_rs780[11];
|
||||
extern u8 bus_sb700[2];
|
||||
|
||||
extern u32 apicid_sb700;
|
||||
|
||||
extern u32 sbdn_rs780;
|
||||
extern u32 sbdn_sb700;
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(bus_sb700[0],
|
||||
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb700,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
static void setup_mahogany_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,146 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8718f/it8718f.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
#include <southbridge/amd/sb700/smbus.h>
|
||||
#include <northbridge/amd/amdk8/f.h>
|
||||
|
||||
unsigned get_sbdn(unsigned bus);
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
|
||||
|
||||
void memreset(int controllers, const struct mem_controller *ctrl) { }
|
||||
void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
#include <southbridge/amd/rs780/rs780.h>
|
||||
#include <northbridge/amd/amdk8/amdk8.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
|
||||
int needs_reset = 0;
|
||||
u32 bsp_apicid = 0;
|
||||
msr_t msr;
|
||||
struct cpuid_result cpuid1;
|
||||
struct sys_info *sysinfo = &sysinfo_car;
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
/* sb7xx_51xx_lpc_port80(); */
|
||||
sb7xx_51xx_pci_port80();
|
||||
}
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb7xx_51xx_lpc_init();
|
||||
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
|
||||
|
||||
setup_mahogany_resource_map();
|
||||
|
||||
setup_coherent_ht_domain();
|
||||
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
/* It is said that we should start core1 after all core0 launched */
|
||||
wait_all_core0_started();
|
||||
start_other_cores();
|
||||
#endif
|
||||
wait_all_aps_started(bsp_apicid);
|
||||
|
||||
ht_setup_chains_x(sysinfo);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
/* Check to see if processor is capable of changing FIDVID */
|
||||
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6) == 0x6) {
|
||||
/* Read FIDVID_STATUS */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
|
||||
enable_fid_change();
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
|
||||
}
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
rs780_htinit();
|
||||
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now; */
|
||||
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
|
||||
sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
sb7xx_51xx_before_pci_init();
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
if BOARD_AMD_PISTACHIO
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_AM2
|
||||
select DIMM_DDR2
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_RS690
|
||||
select SOUTHBRIDGE_AMD_SB600
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select QRANK_DIMM_SUPPORT
|
||||
select SET_FIDVID
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/pistachio
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Pistachio"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
endif # BOARD_AMD_PISTACHIO
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_PISTACHIO
|
||||
bool "Pistachio"
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, NotSerialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
@@ -1,254 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS690 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0012FFFF, 1, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0013FFFF, 0, INTA, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
Package(){0x0013FFFF, 2, INTC, 0 },
|
||||
Package(){0x0013FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS690 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
Package(){0x0006FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
Package(){0x0007FFFF, 0, 0, 19 },
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0012FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
|
||||
Package(){0x0013FFFF, 0, 0, 16 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
Package(){0x0013FFFF, 2, 0, 18 },
|
||||
Package(){0x0013FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00130004, 2, 0, 18 }, */
|
||||
/* Package(){0x00130005, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
@@ -1,145 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00120000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,159 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
/*
|
||||
* If (LLessEqual(UOM5,9)) {
|
||||
* Scope (\_GPE) {
|
||||
* Method (_L1A) {
|
||||
* UCOC()
|
||||
* if (LEqual(GPB5,PLC5)) {
|
||||
* Not(PLC5,PLC5)
|
||||
* Store(PLC5, \_SB.PT5D)
|
||||
* }
|
||||
* }
|
||||
* }
|
||||
* }
|
||||
*/
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include "northbridge/amd/amdk8/acpi.h"
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/amd/powernow.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
get_bus_conf();
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB600 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
Category: eval
|
||||
@@ -1,69 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,80 +0,0 @@
|
||||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3050 inherit
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge, K8 HT Configuration
|
||||
chip southbridge/amd/rs690
|
||||
device pci 0.0 on end # HT 0x7910
|
||||
# device pci 0.1 off end # CLK
|
||||
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
|
||||
device pci 5.0 on end # Internal Graphics 0x791F
|
||||
end
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x791b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x7914
|
||||
device pci 5.0 on end # PCIE P2P bridge 0x7915
|
||||
device pci 6.0 on end # PCIE P2P bridge 0x7916
|
||||
device pci 7.0 on end # PCIE P2P bridge 0x7917
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
register "gpp_configuration" = "4"
|
||||
register "port_enable" = "0xfc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 12.0 on end # SATA 0x4380
|
||||
device pci 13.0 on end # USB 0x4387
|
||||
device pci 13.1 on end # USB 0x4388
|
||||
device pci 13.2 on end # USB 0x4389
|
||||
device pci 13.3 on end # USB 0x438a
|
||||
device pci 13.4 on end # USB 0x438b
|
||||
device pci 13.5 on end # USB 2 0x4386
|
||||
device pci 14.0 on # SM 0x4385
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 off end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 off end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 off end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x438c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x438d
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # ACI 0x4382
|
||||
device pci 14.6 on end # MCI 0x438e
|
||||
end #southbridge/amd/sb600
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.1 on end # K8 Address Map
|
||||
device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
|
||||
device pci 18.3 on end # K8 Miscellaneous Control
|
||||
end #northbridge/amd/amdk8
|
||||
end #domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,197 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include "southbridge/amd/sb600/sb600.h"
|
||||
|
||||
/*extern*/ u16 pm_base = 0x800;
|
||||
/* pm_base should be set in sb ACPI */
|
||||
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
|
||||
* registers into 32 bytes limit.
|
||||
* */
|
||||
|
||||
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
|
||||
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
|
||||
#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
|
||||
#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
|
||||
#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
|
||||
#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
pm_base &= 0xFFFF;
|
||||
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = 244;
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 0;
|
||||
|
||||
fadt->firmware_ctrl = (u32) facs;
|
||||
fadt->dsdt = (u32) dsdt;
|
||||
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0xe2;
|
||||
|
||||
pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
|
||||
pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
|
||||
pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
|
||||
pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
|
||||
pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
|
||||
pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
|
||||
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
|
||||
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
|
||||
|
||||
/* CpuControl is in \_PR.CP00, 6 bytes */
|
||||
pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
|
||||
pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
|
||||
|
||||
pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
|
||||
pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
|
||||
|
||||
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
|
||||
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
|
||||
|
||||
pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
|
||||
* the contents of the PM registers at
|
||||
* index 20-2B to decode ACPI I/O address.
|
||||
* AcpiSmiEn & SmiCmdEn*/
|
||||
pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
|
||||
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
|
||||
|
||||
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
|
||||
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
|
||||
fadt->gpe0_blk = ACPI_GPE0_BLK;
|
||||
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
|
||||
fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x0001c1a5;/* 0x25; */
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32) facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32) dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
@@ -1,109 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u8 bus_rs690[8];
|
||||
u8 bus_sb600[2];
|
||||
u32 apicid_sb600;
|
||||
|
||||
/*
|
||||
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
* You may need to preset pci1234 for HTIO board,
|
||||
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
*/
|
||||
u32 pci1234x[] = {
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
/*
|
||||
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||
* assume every chain only have 4 ht device at most
|
||||
*/
|
||||
u32 hcdnx[] = {
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
u32 sbdn_rs690;
|
||||
u32 sbdn_sb600;
|
||||
|
||||
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
struct device *dev;
|
||||
int i;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
sbdn_rs690 = sysconf.sbdn;
|
||||
sbdn_sb600 = 0;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
bus_sb600[i] = 0;
|
||||
}
|
||||
for (i = 0; i < 8; i++) {
|
||||
bus_rs690[i] = 0;
|
||||
}
|
||||
|
||||
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
bus_sb600[0] = bus_rs690[0];
|
||||
|
||||
/* sb600 */
|
||||
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
|
||||
if (dev) {
|
||||
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
|
||||
/* rs690 */
|
||||
for (i = 1; i < 8; i++) {
|
||||
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
|
||||
if (dev) {
|
||||
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb600 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern u8 bus_rs690[8];
|
||||
extern u8 bus_sb600[2];
|
||||
extern u32 sbdn_sb600;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_sb600[0];
|
||||
pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,259 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/sb600/sb600.h>
|
||||
|
||||
#define ADT7475_ADDRESS 0x2E
|
||||
#define SMBUS_IO_BASE 0x1000
|
||||
|
||||
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
||||
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
||||
u8 val);
|
||||
#define ADT7475_read_byte(address) \
|
||||
do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
|
||||
#define ADT7475_write_byte(address, val) \
|
||||
do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
|
||||
|
||||
|
||||
/********************************************************
|
||||
* pistachio uses a BCM5787 as on-board NIC.
|
||||
* It has a pin named LOW_POWER to enable it into LOW POWER state.
|
||||
* In order to run NIC, we should let it out of Low power state. This pin is
|
||||
* controlled by GPM8.
|
||||
* RRG4.2.3 GPM as GPIO
|
||||
* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
|
||||
* I/O C50, C51, C52, PM I/O94, 95, 96.
|
||||
* RRG4.2.3.1 GPM pins as Input
|
||||
* RRG4.2.3.2 GPM pins as Output
|
||||
* The R77 (on BRASS) / R81 (on Bronze) is not load!
|
||||
* So NIC can work whether this function runs.
|
||||
********************************************************/
|
||||
static void enable_onboard_nic(void)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
printk(BIOS_INFO, "%s.\n", __func__);
|
||||
|
||||
/* enable GPM8 output */
|
||||
byte = pm_ioread(0x95);
|
||||
byte &= 0xfe;
|
||||
pm_iowrite(0x95, byte);
|
||||
|
||||
/* GPM8 outputs low. */
|
||||
byte = pm_ioread(0x94);
|
||||
byte &= 0xfe;
|
||||
pm_iowrite(0x94, byte);
|
||||
}
|
||||
|
||||
/*
|
||||
* set thermal config
|
||||
*/
|
||||
static void set_thermal_config(void)
|
||||
{
|
||||
u8 byte, byte2;
|
||||
u16 word;
|
||||
u32 dword;
|
||||
struct device *sm_dev;
|
||||
|
||||
/* set adt7475 */
|
||||
ADT7475_write_byte(0x40, 0x04);
|
||||
/* Config Register 6 */
|
||||
ADT7475_write_byte(0x10, 0x00);
|
||||
/* Config Register 7 */
|
||||
ADT7475_write_byte(0x11, 0x00);
|
||||
|
||||
/* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
|
||||
ADT7475_write_byte(0x7c, 0xa0);
|
||||
/* No offset for remote 2 */
|
||||
ADT7475_write_byte(0x72, 0x00);
|
||||
/* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
|
||||
ADT7475_write_byte(0x5c, 0x02);
|
||||
/* PWM 3 configuration register Case fan controlled by 690 temp */
|
||||
ADT7475_write_byte(0x5e, 0x42);
|
||||
|
||||
/* remote 1 low temp limit */
|
||||
ADT7475_write_byte(0x4e, 0x00);
|
||||
/* remote 1 High temp limit (90C) */
|
||||
ADT7475_write_byte(0x4f, 0x9a);
|
||||
|
||||
/* remote2 Low Temp Limit */
|
||||
ADT7475_write_byte(0x52, 0x00);
|
||||
/* remote2 High Limit (90C) */
|
||||
ADT7475_write_byte(0x53, 0x9a);
|
||||
|
||||
/* remote 1 therm temp limit (95C) */
|
||||
ADT7475_write_byte(0x6a, 0x9f);
|
||||
/* remote 2 therm temp limit (95C) */
|
||||
ADT7475_write_byte(0x6c, 0x9f);
|
||||
|
||||
/* PWM 1 minimum duty cycle (37%) */
|
||||
ADT7475_write_byte(0x64, 0x60);
|
||||
/* PWM 1 Maximum duty cycle (100%) */
|
||||
ADT7475_write_byte(0x38, 0xff);
|
||||
/* PWM 3 minimum duty cycle (37%) */
|
||||
ADT7475_write_byte(0x66, 0x60);
|
||||
/* PWM 3 Maximum Duty Cycle (100%) */
|
||||
ADT7475_write_byte(0x3a, 0xff);
|
||||
|
||||
/* Remote 1 temperature Tmin (32C) */
|
||||
ADT7475_write_byte(0x67, 0x60);
|
||||
/* Remote 2 temperature Tmin (32C) */
|
||||
ADT7475_write_byte(0x69, 0x60);
|
||||
/* remote 1 Trange (53C ramp range) */
|
||||
ADT7475_write_byte(0x5f, 0xe8);
|
||||
/* remote 2 Trange (53C ramp range) */
|
||||
ADT7475_write_byte(0x61, 0xe8);
|
||||
|
||||
/* PWM2 Duty cycle */
|
||||
ADT7475_write_byte(0x65, 0x00);
|
||||
/* PWM2 Disabled */
|
||||
ADT7475_write_byte(0x5d, 0x80);
|
||||
/* PWM2 Max Duty Cycle */
|
||||
ADT7475_write_byte(0x39, 0x00);
|
||||
|
||||
/* Config Register 3 - enable smbalert & therm */
|
||||
ADT7475_write_byte(0x78, 0x03);
|
||||
/* Config Register 4 - enable therm output */
|
||||
ADT7475_write_byte(0x7d, 0x09);
|
||||
/* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
|
||||
ADT7475_write_byte(0x75, 0x2a);
|
||||
/* Config Register 1 Set Start bit */
|
||||
ADT7475_write_byte(0x40, 0x05);
|
||||
/* Read status register to clear any old errors */
|
||||
byte2 = ADT7475_read_byte(0x42);
|
||||
byte = ADT7475_read_byte(0x41);
|
||||
|
||||
/* remote 1 temperature offset */
|
||||
ADT7475_write_byte(0x70, 0x00);
|
||||
|
||||
printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
|
||||
byte2, byte);
|
||||
|
||||
/* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
|
||||
/* set GPM5 as GPM5, not DDR3_memory disable */
|
||||
byte = pm_ioread(0x8f);
|
||||
byte |= 1 << 6; /* enable GPE */
|
||||
pm_iowrite(0x8f, byte);
|
||||
|
||||
/* GPM5 as GPIO not USB OC */
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
dword = pci_read_config32(sm_dev, 0x64);
|
||||
dword |= 1 << 19;
|
||||
pci_write_config32(sm_dev, 0x64, dword);
|
||||
|
||||
/* Enable Client Management Index/Data registers */
|
||||
dword = pci_read_config32(sm_dev, 0x78);
|
||||
dword |= 1 << 11; /* Cms_enable */
|
||||
pci_write_config32(sm_dev, 0x78, dword);
|
||||
|
||||
/* MiscfuncEnable */
|
||||
byte = pci_read_config8(sm_dev, 0x41);
|
||||
byte |= (1 << 5);
|
||||
pci_write_config8(sm_dev, 0x41, byte);
|
||||
|
||||
/* set GPM5 as input */
|
||||
/* set index register 0C50h to 13h (miscellaneous control) */
|
||||
outb(0x13, 0xC50); /* CMIndex */
|
||||
/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
|
||||
byte = inb(0xC51); /* CMData */
|
||||
byte &= 0x3f;
|
||||
byte |= 1 << 6;
|
||||
outb(byte, 0xC51);
|
||||
/* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */
|
||||
byte = inb(0xc52); /* GpmPort */
|
||||
byte |= 1 << 5;
|
||||
outb(byte, 0xc52);
|
||||
/* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
|
||||
byte = inb(0xc51);
|
||||
byte &= 0x3f;
|
||||
outb(byte, 0xc51);
|
||||
|
||||
/* trigger SCI/SMI */
|
||||
byte = pm_ioread(0x34);
|
||||
byte &= 0xcf;
|
||||
pm_iowrite(0x34, byte);
|
||||
|
||||
/* set GPM5 to not wake from s5 */
|
||||
byte = pm_ioread(0x77);
|
||||
byte &= ~(1 << 5);
|
||||
pm_iowrite(0x77, byte);
|
||||
|
||||
/* trigger on falling edge */
|
||||
byte = pm_ioread(0x38);
|
||||
byte &= ~(1 << 2);
|
||||
pm_iowrite(0x38, byte);
|
||||
|
||||
/* set SB600 GPIO 64 to GPIO with pull-up */
|
||||
byte = pm2_ioread(0x42);
|
||||
byte &= 0x3f;
|
||||
pm2_iowrite(0x42, byte);
|
||||
|
||||
/* set GPIO 64 to input */
|
||||
word = pci_read_config16(sm_dev, 0x56);
|
||||
word |= 1 << 7;
|
||||
pci_write_config16(sm_dev, 0x56, word);
|
||||
|
||||
/* set GPIO 64 internal pull-up */
|
||||
byte = pm2_ioread(0xf0);
|
||||
byte &= 0xee;
|
||||
pm2_iowrite(0xf0, byte);
|
||||
|
||||
/* set Talert to be active low */
|
||||
byte = pm_ioread(0x67);
|
||||
byte &= ~(1 << 5);
|
||||
pm_iowrite(0x67, byte);
|
||||
|
||||
/* set Talert to generate ACPI event */
|
||||
byte = pm_ioread(0x3c);
|
||||
byte &= 0xf3;
|
||||
pm_iowrite(0x3c, byte);
|
||||
|
||||
/* THERMTRIP pin */
|
||||
/* byte = pm_ioread(0x68);
|
||||
* byte |= 1 << 3;
|
||||
* pm_iowrite(0x68, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x55);
|
||||
* byte |= 1 << 0;
|
||||
* pm_iowrite(0x55, byte);
|
||||
*
|
||||
* byte = pm_ioread(0x67);
|
||||
* byte &= ~( 1 << 6);
|
||||
* pm_iowrite(0x67, byte);
|
||||
*/
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in pistachio board.
|
||||
* This function called early than rs690_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
|
||||
|
||||
enable_onboard_nic();
|
||||
set_thermal_config();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,111 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
extern u8 bus_rs690[8];
|
||||
extern u8 bus_sb600[2];
|
||||
|
||||
extern u32 apicid_sb600;
|
||||
|
||||
extern u32 sbdn_rs690;
|
||||
extern u32 sbdn_sb600;
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
struct device *dev;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
dev =
|
||||
dev_find_slot(bus_sb600[0],
|
||||
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
|
||||
if (dev) {
|
||||
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||
smp_write_ioapic(mc, apicid_sb600,
|
||||
0x11,(void *) dword);
|
||||
|
||||
/* Initialize interrupt mapping */
|
||||
/* aza */
|
||||
byte = pci_read_config8(dev, 0x63);
|
||||
byte &= 0xf8;
|
||||
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||
pci_write_config8(dev, 0x63, byte);
|
||||
|
||||
/* SATA */
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~(7 << 26);
|
||||
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||
/* dword |= 1 << 22; PIC and APIC co exists */
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
/*
|
||||
* 00:12.0: PROG SATA : INT F
|
||||
* 00:13.0: INTA USB_0
|
||||
* 00:13.1: INTB USB_1
|
||||
* 00:13.2: INTC USB_2
|
||||
* 00:13.3: INTD USB_3
|
||||
* 00:13.4: INTC USB_4
|
||||
* 00:13.5: INTD USB2
|
||||
* 00:14.1: INTA IDE
|
||||
* 00:14.2: Prog HDA : INT E
|
||||
* 00:14.5: INTB ACI
|
||||
* 00:14.6: INTB MCI
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
static void setup_pistachio_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,156 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <delay.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "southbridge/amd/rs690/early_setup.c"
|
||||
#include "southbridge/amd/sb600/early_setup.c"
|
||||
#include <northbridge/amd/amdk8/f.h>
|
||||
|
||||
void memreset(int controllers, const struct mem_controller *ctrl) { }
|
||||
void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include <northbridge/amd/amdk8/amdk8.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
|
||||
int needs_reset = 0;
|
||||
u32 bsp_apicid = 0;
|
||||
msr_t msr;
|
||||
struct cpuid_result cpuid1;
|
||||
struct sys_info *sysinfo = &sysinfo_car;
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
sb600_lpc_port80();
|
||||
/* sb600_pci_port80(); */
|
||||
}
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
enable_rs690_dev8();
|
||||
sb600_lpc_init();
|
||||
|
||||
/* Pistachio used a FPGA to enable serial debug instead of a SIO
|
||||
* and it doesn't require any special setup. */
|
||||
|
||||
console_init();
|
||||
|
||||
post_code(0x03);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
|
||||
|
||||
setup_pistachio_resource_map();
|
||||
|
||||
setup_coherent_ht_domain();
|
||||
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
/* It is said that we should start core1 after all core0 launched */
|
||||
wait_all_core0_started();
|
||||
start_other_cores();
|
||||
#endif
|
||||
wait_all_aps_started(bsp_apicid);
|
||||
|
||||
/* it will set up chains and store link pair for optimization later,
|
||||
* it will init sblnk and sbbusn, nodes, sbdn */
|
||||
ht_setup_chains_x(sysinfo);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs690_early_setup();
|
||||
sb600_early_setup();
|
||||
|
||||
post_code(0x04);
|
||||
|
||||
/* Check to see if processor is capable of changing FIDVID */
|
||||
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6) == 0x6) {
|
||||
/* Read FIDVID_STATUS */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
|
||||
enable_fid_change();
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
|
||||
}
|
||||
|
||||
post_code(0x05);
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
rs690_htinit();
|
||||
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
|
||||
|
||||
post_code(0x06);
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now; */
|
||||
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
|
||||
sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x07);
|
||||
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
post_code(0x08);
|
||||
|
||||
rs690_before_pci_init();
|
||||
sb600_before_pci_init();
|
||||
}
|
||||
@@ -1,71 +0,0 @@
|
||||
if BOARD_AMD_SERENGETI_CHEETAH
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select SOUTHBRIDGE_AMD_AMD8132
|
||||
select SOUTHBRIDGE_AMD_AMD8151
|
||||
select CPU_AMD_SOCKET_F
|
||||
select DIMM_DDR2
|
||||
select DIMM_REGISTERED
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select HT_CHAIN_DISTRIBUTE
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PARALLEL_CPU_INIT
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select LIFT_BSP_APIC_ID
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select WAIT_BEFORE_CPUS_INIT
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_512
|
||||
select QRANK_DIMM_SUPPORT
|
||||
select DRIVERS_I2C_I2CMUX
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/serengeti_cheetah
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x8
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Serengeti Cheetah"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config MEM_TRAIN_SEQ
|
||||
int
|
||||
default 1
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x6
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0xa
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
endif # BOARD_AMD_SERENGETI_CHEETAH
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_AMD_SERENGETI_CHEETAH
|
||||
bool "Serengeti Cheetah"
|
||||
@@ -1,3 +0,0 @@
|
||||
$(eval $(call asl_template,ssdt2))
|
||||
$(eval $(call asl_template,ssdt3))
|
||||
$(eval $(call asl_template,ssdt4))
|
||||
@@ -1,183 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
//AMD8111
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
|
||||
// Update the Device Number according to SBDN
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
|
||||
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) {
|
||||
Return (PICM)
|
||||
}
|
||||
Else {
|
||||
Return (APIC)
|
||||
}
|
||||
}
|
||||
|
||||
Device (SBC3)
|
||||
{
|
||||
/* ACPI smbus it should be 0x00040003 if 8131 present */
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
|
||||
}
|
||||
OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
|
||||
Field (PIRQ, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
PIBA, 8,
|
||||
PIDC, 8
|
||||
}
|
||||
/*
|
||||
OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
|
||||
Field (TS3_, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
PTS3, 16
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
Device (HPET)
|
||||
{
|
||||
Name (HPT, 0x00)
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (_UID, 0x00)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
#include "amd8111_pic.asl"
|
||||
|
||||
#include "amd8111_isa.asl"
|
||||
|
||||
Device (TP2P)
|
||||
{
|
||||
/* 8111 P2P and it should 0x00030000 when 8131 present*/
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x08, 0x01 }) }
|
||||
}
|
||||
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x00000001)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
|
||||
})
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,191 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <cpu/x86/lapic_def.h>
|
||||
|
||||
/*
|
||||
* Copyright 2005 AMD
|
||||
*/
|
||||
//AMD8111 isa
|
||||
|
||||
Device (ISA)
|
||||
{
|
||||
/* lpc 0x00040000 */
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
|
||||
}
|
||||
|
||||
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
|
||||
Field (PIRY, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z000, 2, // Parallel Port Range
|
||||
, 1,
|
||||
ECP, 1, // ECP Enable
|
||||
FDC1, 1, // Floppy Drive Controller 1
|
||||
FDC2, 1, // Floppy Drive Controller 2
|
||||
Offset (0x01),
|
||||
Z001, 3, // Serial Port A Range
|
||||
SAEN, 1, // Serial Post A Enabled
|
||||
Z002, 3, // Serial Port B Range
|
||||
SBEN, 1 // Serial Post B Enabled
|
||||
}
|
||||
|
||||
Device (PIC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0000"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
|
||||
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {2}
|
||||
})
|
||||
}
|
||||
|
||||
Device (DMA1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0200"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
|
||||
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
|
||||
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
|
||||
DMA (Compatibility, NotBusMaster, Transfer16) {4}
|
||||
})
|
||||
}
|
||||
|
||||
Device (TMR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0100"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {0}
|
||||
})
|
||||
}
|
||||
|
||||
Device (RTC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0B00"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {8}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SPKR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0800"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
|
||||
})
|
||||
}
|
||||
|
||||
Device (COPR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C04"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {13}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SYSR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x00)
|
||||
Name (SYR1, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
|
||||
IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
|
||||
IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
|
||||
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
|
||||
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
|
||||
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
|
||||
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
|
||||
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
|
||||
IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
|
||||
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
|
||||
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
|
||||
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
|
||||
IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
})
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (SYR1)
|
||||
}
|
||||
}
|
||||
|
||||
Device (MEM)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
|
||||
Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
|
||||
Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
|
||||
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
|
||||
Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
|
||||
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
|
||||
})
|
||||
// Read the Video Memory length
|
||||
CreateDWordField (BUF0, 0x14, CLEN)
|
||||
CreateDWordField (BUF0, 0x10, CBAS)
|
||||
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Store (Local0, CLEN)
|
||||
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2M)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (FLG0, 0x04, Local0)
|
||||
If (LEqual (Local0, 0x04)) { Return (0x0F) }
|
||||
Else { Return (0x00) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2K)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
}
|
||||
#include "superio.asl"
|
||||
|
||||
}
|
||||
@@ -1,366 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
//AMD8111 pic LNKA B C D
|
||||
|
||||
Device (LNKA)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
|
||||
Else { Return (0x0B) } //Enabled
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{ // Routing enable
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x03)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x04)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
@@ -1,130 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
/* 8132 pcix bridge*/
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x14)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot B - PIRQ CDAB
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
|
||||
|
||||
//Cypress Slot C - PIRQ DABC
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
|
||||
|
||||
//Cypress Slot D - PIRQ ABCD
|
||||
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
|
||||
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
|
||||
})
|
||||
Name (PICM, Package (0x14)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
/* 8132 pcix bridge 2 */
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,125 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
/* 8132 pcix bridge*/
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
|
||||
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
/* 8132 pcix bridge 2 */
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,125 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
/* 8132 pcix bridge*/
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
|
||||
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
/* 8132 pcix bridge 2 */
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// AMD8151
|
||||
Device (AGPB)
|
||||
{
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
@@ -1,15 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "amd8111.asl" //real SB at first
|
||||
#include "amd8131.asl"
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "amd8132_2.asl"
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "amd8151.asl"
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "amd8131_2.asl"
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// #include "w83627hf.asl"
|
||||
@@ -1,192 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* written by Stefan Reinauer <stepan@openbios.org>
|
||||
* (C) 2005 Stefan Reinauer
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Island Aruma ACPI support
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include <cbfs.h>
|
||||
#include "northbridge/amd/amdk8/acpi.h"
|
||||
#include "mb_sysconf.h"
|
||||
#include "mainboard.h"
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
u32 gsi_base = 0x18;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write 8111 IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
/* Write all 8131 IOAPICs */
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
|
||||
res->base, gsi_base);
|
||||
gsi_base+=7;
|
||||
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
|
||||
res->base, gsi_base);
|
||||
gsi_base+=7;
|
||||
}
|
||||
}
|
||||
|
||||
int i;
|
||||
int j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
u32 d = 0;
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
/* 8131 need to use +4 */
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
d = 7;
|
||||
break;
|
||||
case 3:
|
||||
d = 4;
|
||||
break;
|
||||
}
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
|
||||
res->base, gsi_base);
|
||||
gsi_base+=d;
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
|
||||
res->base, gsi_base);
|
||||
gsi_base+=d;
|
||||
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 5);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high*/
|
||||
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapic_nmis(current, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long mainboard_write_acpi_tables(struct device *dev, unsigned long start, acpi_rsdp_t *rsdp)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_header_t *ssdtx;
|
||||
const void *p;
|
||||
size_t p_size;
|
||||
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
|
||||
|
||||
/* Align ACPI tables to 16 bytes */
|
||||
start = ALIGN(start, 16);
|
||||
current = start;
|
||||
|
||||
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
|
||||
const char *file_name;
|
||||
if ((sysconf.pci1234[i] & 1) != 1)
|
||||
continue;
|
||||
u8 c;
|
||||
if (i < 7)
|
||||
c = (u8) ('4' + i - 1);
|
||||
else
|
||||
c = (u8) ('A' + i - 1 - 6);
|
||||
current = ALIGN(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
|
||||
ssdtx = (acpi_header_t *)current;
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1: /* 8132 */
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
|
||||
break;
|
||||
case 2: /* 8151 */
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
|
||||
break;
|
||||
case 3: /* 8131 */
|
||||
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
p = cbfs_boot_map_with_leak(
|
||||
file_name,
|
||||
CBFS_TYPE_RAW, &p_size);
|
||||
if (!p || p_size < sizeof(acpi_header_t))
|
||||
continue;
|
||||
|
||||
memcpy(ssdtx, p, sizeof(acpi_header_t));
|
||||
current += ssdtx->length;
|
||||
memcpy(ssdtx, p, ssdtx->length);
|
||||
update_ssdtx((void *)ssdtx, i);
|
||||
ssdtx->checksum = 0;
|
||||
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
|
||||
acpi_add_table(rsdp, ssdtx);
|
||||
}
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
Category: server
|
||||
@@ -1,52 +0,0 @@
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,147 +0,0 @@
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x2b80 inherit
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/amd/amd8132
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 off end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on
|
||||
chip drivers/i2c/i2cmux # pca9556 smbus mux
|
||||
device i2c 18 on #0 pca9516 1
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 18 on #1 pca9516 2
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # acpi
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on # northbridge
|
||||
chip southbridge/amd/amd8151
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 1.0 on end
|
||||
end
|
||||
end # device pci 19.0
|
||||
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
end
|
||||
|
||||
|
||||
end #domain
|
||||
end
|
||||
@@ -1,219 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_PR)
|
||||
{
|
||||
Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
|
||||
Processor (CPU1, 0x01, 0x00000000, 0x00) {}
|
||||
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
|
||||
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
|
||||
|
||||
}
|
||||
|
||||
Method (FWSO, 0, NotSerialized) { }
|
||||
|
||||
|
||||
Scope (_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
/* BUS0 root bus */
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
|
||||
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00180000)
|
||||
Name (_UID, 0x01)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
|
||||
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
|
||||
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x8100, // Address Range Minimum
|
||||
0xFFFF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x7F00,,,
|
||||
, TypeStatic) //8100h-FFFFh
|
||||
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x000C0000, // Address Range Minimum
|
||||
0x000CFFFF, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00010000,,,
|
||||
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
|
||||
|
||||
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x03AF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x03B0,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x03E0, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0918,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
})
|
||||
\_SB.OSVR ()
|
||||
CreateDWordField (BUF0, 0x3E, VLEN)
|
||||
CreateDWordField (BUF0, 0x36, VMAX)
|
||||
CreateDWordField (BUF0, 0x32, VMIN)
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Add (VMIN, Local0, VMAX)
|
||||
Decrement (VMAX)
|
||||
Store (Local0, VLEN)
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci0_hc.asl"
|
||||
|
||||
}
|
||||
Device (PCI1)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBST)
|
||||
}
|
||||
Name (_BBN, 0x00)
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
Scope (_GPE)
|
||||
{
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
|
||||
}
|
||||
|
||||
Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0B, 0x02)
|
||||
}
|
||||
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
/*
|
||||
Method (_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xE0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
*/
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
}
|
||||
@@ -1,162 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
extern unsigned pm_base; /* pm_base should be set in sb ACPI */
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
||||
|
||||
acpi_header_t *header=&(fadt->header);
|
||||
|
||||
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt,0,sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature,"FACP",4);
|
||||
header->length = 244;
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id,OEM_ID,6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id,ASLC,4);
|
||||
header->asl_compiler_revision = 0;
|
||||
|
||||
fadt->firmware_ctrl=(u32)facs;
|
||||
fadt->dsdt= (u32)dsdt;
|
||||
/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;/* pm_base+0x2f */
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0xe2;
|
||||
|
||||
fadt->pm1a_evt_blk = pm_base;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = pm_base+0x04;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = 0x0000;
|
||||
fadt->pm_tmr_blk = pm_base+0x08;
|
||||
fadt->gpe0_blk = pm_base+0x20;
|
||||
fadt->gpe1_blk = pm_base+0xb0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 4;
|
||||
fadt->gpe1_blk_len = 8;
|
||||
fadt->gpe1_base = 16;
|
||||
|
||||
fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x25;
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pm_base;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = pm_base+0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 64;
|
||||
fadt->x_gpe1_blk.bit_offset = 16;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = pm_base+0xb0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
|
||||
}
|
||||
@@ -1,217 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
|
||||
struct mb_sysconf_t mb_sysconf;
|
||||
|
||||
static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */
|
||||
/* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
static unsigned get_hcid(unsigned i)
|
||||
{
|
||||
unsigned id = 0;
|
||||
|
||||
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
|
||||
|
||||
unsigned devn = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
struct device *dev;
|
||||
|
||||
dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
|
||||
|
||||
switch (dev->device) {
|
||||
case 0x7458: /*8132 */
|
||||
id = 1;
|
||||
break;
|
||||
case 0x7454: /*8151 */
|
||||
id = 2;
|
||||
break;
|
||||
case 0x7450: /*8131 */
|
||||
id = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
/* we may need more way to find out hcid: subsystem id? GPIO read ? */
|
||||
|
||||
/* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
struct device *dev;
|
||||
int i, j;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.mb = &mb_sysconf;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
|
||||
m->sbdn3 = sysconf.hcdn[0] & 0xff;
|
||||
|
||||
m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
m->bus_8111_0 = m->bus_8132_0;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0));
|
||||
if (dev) {
|
||||
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8111_0, sysconf.sbdn);
|
||||
}
|
||||
|
||||
/* 8132-1 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0));
|
||||
if (dev) {
|
||||
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8132_0, m->sbdn3);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0));
|
||||
if (dev) {
|
||||
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8132_0, m->sbdn3 + 1);
|
||||
}
|
||||
|
||||
/* HT chain 1 */
|
||||
j = 0;
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
|
||||
/* check hcid type here */
|
||||
sysconf.hcid[i] = get_hcid(i);
|
||||
|
||||
switch (sysconf.hcid[i]) {
|
||||
|
||||
case 1: /* 8132 */
|
||||
case 3: /* 8131 */
|
||||
|
||||
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
|
||||
|
||||
m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
/* 8132-1 */
|
||||
dev =
|
||||
dev_find_slot(m->bus_8132a[j][0],
|
||||
PCI_DEVFN(m->sbdn3a[j], 0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][1] =
|
||||
pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8132a[j][0], m->sbdn3a[j]);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev =
|
||||
dev_find_slot(m->bus_8132a[j][0],
|
||||
PCI_DEVFN(m->sbdn3a[j] + 1, 0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][2] =
|
||||
pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8132a[j][0], m->sbdn3a[j] + 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case 2: /* 8151 */
|
||||
|
||||
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
|
||||
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
|
||||
/* 8151 */
|
||||
dev =
|
||||
dev_find_slot(m->bus_8151[j][0],
|
||||
PCI_DEVFN(m->sbdn5[j] + 1, 0));
|
||||
|
||||
if (dev) {
|
||||
m->bus_8151[j][1] =
|
||||
pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG,
|
||||
"ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
m->bus_8151[j][0], m->sbdn5[j] + 1);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(3);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
m->apicid_8111 = apicid_base + 0;
|
||||
m->apicid_8132_1 = apicid_base + 1;
|
||||
m->apicid_8132_2 = apicid_base + 2;
|
||||
for (i = 0; i < j; i++) {
|
||||
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
|
||||
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
|
||||
}
|
||||
}
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
|
||||
uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2,
|
||||
uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
|
||||
uint8_t sum = 0;
|
||||
int i;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = m->bus_8111_0;
|
||||
pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1022;
|
||||
pirq->rtr_device = 0x746b;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
{
|
||||
struct device *dev;
|
||||
dev =
|
||||
dev_find_slot(m->bus_8111_0,
|
||||
PCI_DEVFN(sysconf.sbdn + 1, 3));
|
||||
if (dev) {
|
||||
/* initialize PCI interupts - these assignments depend
|
||||
on the PCB routing of PINTA-D
|
||||
|
||||
PINTA = IRQ3
|
||||
PINTB = IRQ5
|
||||
PINTC = IRQ10
|
||||
PINTD = IRQ11
|
||||
*/
|
||||
pci_write_config16(dev, 0x56, 0xba53);
|
||||
}
|
||||
}
|
||||
|
||||
/* pci bridge */
|
||||
printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
|
||||
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
|
||||
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4);
|
||||
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
|
||||
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11 };
|
||||
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
|
||||
write_pirq_info(pirq_info, m->bus_8111_1, 0, 0, 0, 0, 0, 0, 0, 0x4,
|
||||
0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
/* pcix bridge */
|
||||
|
||||
int j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
|
||||
unsigned devn = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8,
|
||||
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
j++;
|
||||
|
||||
}
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include "mainboard.h"
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp);
|
||||
@@ -1,40 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MB_SYSCONF_H
|
||||
|
||||
#define MB_SYSCONF_H
|
||||
|
||||
struct mb_sysconf_t {
|
||||
unsigned char bus_8132_0;
|
||||
unsigned char bus_8132_1;
|
||||
unsigned char bus_8132_2;
|
||||
unsigned char bus_8111_0;
|
||||
unsigned char bus_8111_1;
|
||||
|
||||
unsigned char bus_8132a[7][3];
|
||||
|
||||
unsigned char bus_8151[7][2];
|
||||
|
||||
unsigned apicid_8111;
|
||||
unsigned apicid_8132_1;
|
||||
unsigned apicid_8132_2;
|
||||
unsigned apicid_8132a[7][2];
|
||||
|
||||
unsigned sbdn3;
|
||||
unsigned sbdn3a[7];
|
||||
unsigned sbdn5[7];
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,179 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
#include <cpu/amd/multicore.h>
|
||||
#endif
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int i, j, bus_isa;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
|
||||
{
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
|
||||
j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1: /* 8132 */
|
||||
case 3: /* 8131 */
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
|
||||
res2mmio(res, 0, 0));
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
/* ??? What */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
|
||||
|
||||
/* Onboard AMD USB */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
|
||||
|
||||
/*Slot 3 PCI 32 */
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
|
||||
|
||||
|
||||
/* Slot 4 PCI 32 */
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
|
||||
|
||||
|
||||
/* Slot 1 PCI-X 133/100/66 */
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
|
||||
|
||||
|
||||
/* Slot 2 PCI-X 133/100/66 */
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
|
||||
|
||||
j = 0;
|
||||
|
||||
for (i = 1; i < sysconf.hc_possible_num; i++) {
|
||||
if (!(sysconf.pci1234[i] & 0x1))
|
||||
continue;
|
||||
int ii;
|
||||
struct device *dev;
|
||||
struct resource *res;
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
/* Slot 1 PCI-X 133/100/66 */
|
||||
for (ii = 0; ii < 4; ii++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
/* Slot 2 PCI-X 133/100/66 */
|
||||
for (ii = 0; ii < 4; ii++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case 2:
|
||||
|
||||
/* Slot AGP */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
At this time, For ACPI support We got
|
||||
1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
|
||||
2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
|
||||
3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
|
||||
4. Chipset support: amd8111, amd8132
|
||||
|
||||
The developers need to change for different MB
|
||||
|
||||
Change dsdt.asl, according to MB layout
|
||||
pci1, pci2, pci3, pci4, ...., pci8
|
||||
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
|
||||
|
||||
Change acpi_tables.c
|
||||
sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
|
||||
if there is HT-IO board, need to preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
|
||||
|
||||
Regarding pci bridge apic and pic
|
||||
need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c
|
||||
|
||||
About other chipsets, need to develop their special asl such as
|
||||
ck804.asl --- NB ck804
|
||||
bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000
|
||||
|
||||
use a to create hex file
|
||||
use c to delele hex file
|
||||
|
||||
yhlu
|
||||
|
||||
09/18/2005
|
||||
@@ -1,272 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
static void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
@@ -1,197 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
||||
#include <reset.h>
|
||||
#include <northbridge/amd/amdk8/raminit.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <delay.h>
|
||||
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include <northbridge/amd/amdk8/f.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
unsigned get_sbdn(unsigned bus);
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* GPIO on amd8111 to enable MEMRST ???? */
|
||||
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */
|
||||
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
void memreset(int controllers, const struct mem_controller *ctrl) { }
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
#define SMBUS_HUB 0x18
|
||||
int ret,i;
|
||||
unsigned device=(ctrl->channel0[0])>>8;
|
||||
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */
|
||||
i = 2;
|
||||
do {
|
||||
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
|
||||
} while ((ret != 0) && (i-->0));
|
||||
|
||||
smbus_write_byte(SMBUS_HUB, 0x03, 0);
|
||||
}
|
||||
|
||||
int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
||||
#include <northbridge/amd/amdk8/amdk8.h>
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include <spd.h>
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
|
||||
#define RC0 ((1 << 0)<<8)
|
||||
#define RC1 ((1 << 1)<<8)
|
||||
#define RC2 ((1 << 2)<<8)
|
||||
#define RC3 ((1 << 3)<<8)
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
/* first node */
|
||||
RC0|DIMM0, RC0|DIMM2, 0, 0,
|
||||
RC0|DIMM1, RC0|DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
/* second node */
|
||||
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
|
||||
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
/* third node */
|
||||
RC2|DIMM0, RC2|DIMM2, 0, 0,
|
||||
RC2|DIMM1, RC2|DIMM3, 0, 0,
|
||||
/* four node */
|
||||
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
|
||||
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct sys_info *sysinfo = &sysinfo_car;
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
#if IS_ENABLED(CONFIG_SET_FIDVID)
|
||||
struct cpuid_result cpuid1;
|
||||
#endif
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
|
||||
setup_mb_resource_map();
|
||||
|
||||
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
|
||||
|
||||
set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
|
||||
setup_coherent_ht_domain(); /* routing table and start other core0 */
|
||||
|
||||
wait_all_core0_started();
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
/* It is said that we should start core1 after all core0 launched */
|
||||
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
|
||||
* So here need to make sure last core0 is started, esp for two way system,
|
||||
* (there may be apic id conflicts in that case)
|
||||
*/
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
/* it will set up chains and store link pair for optimization later */
|
||||
ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
|
||||
|
||||
#if IS_ENABLED(CONFIG_SET_FIDVID)
|
||||
/* Check to see if processor is capable of changing FIDVID */
|
||||
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6) == 0x6) {
|
||||
|
||||
{
|
||||
/* Read FIDVID_STATUS */
|
||||
msr_t msr;
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
enable_fid_change();
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* show final fid and vid */
|
||||
{
|
||||
msr_t msr;
|
||||
msr = rdmsr(0xc0010042);
|
||||
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
|
||||
/* fidvid change will issue one LDTSTOP and the HT change will be effective too */
|
||||
if (needs_reset) {
|
||||
printk(BIOS_INFO, "ht reset -\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
}
|
||||
#endif
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
|
||||
/* do we need apci timer, tsc...., only debug need it for better output */
|
||||
/* all ap stopped? */
|
||||
/* Need to use TMICT to synchronize FID/VID */
|
||||
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci2_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci3_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2005 AMD
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci4_hc.asl"
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
if BOARD_ASROCK_939A785GMH
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_SOCKET_939
|
||||
select K8_HT_FREQ_1G_SUPPORT
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select SOUTHBRIDGE_AMD_RS780
|
||||
select SOUTHBRIDGE_AMD_SB700
|
||||
select SUPERIO_WINBOND_W83627DHG
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_OPTION_TABLE
|
||||
select LIFT_BSP_APIC_ID
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select GFXUMA
|
||||
select RAMINIT_SYSINFO
|
||||
select QRANK_DIMM_SUPPORT
|
||||
select SET_FIDVID
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asrock/939a785gmh
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "939A785GMH"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
endif # BOARD_ASROCK_939A785GMH
|
||||
@@ -1,2 +0,0 @@
|
||||
config BOARD_ASROCK_939A785GMH
|
||||
bool "939A785GMH/128M"
|
||||
@@ -1,188 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, INTA, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTA, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
Package(){0x0012FFFF, 2, INTC, 0 },
|
||||
Package(){0x0012FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTD, 0 },
|
||||
Package(){0x0013FFFF, 2, INTA, 0 },
|
||||
Package(){0x0013FFFF, 3, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Package(){0x0001FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0001FFFF, 1, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
Package(){0x0002FFFF, 1, 0, 19 },
|
||||
Package(){0x0002FFFF, 2, 0, 16 },
|
||||
Package(){0x0002FFFF, 3, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe x1 slot */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
Package(){0x0009FFFF, 1, 0, 18 },
|
||||
Package(){0x0009FFFF, 2, 0, 19 },
|
||||
Package(){0x0009FFFF, 3, 0, 10 },
|
||||
|
||||
/* Bus 0, Dev A - PCIe internal ethernet */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
Package(){0x000AFFFF, 1, 0, 19 },
|
||||
Package(){0x000AFFFF, 2, 0, 16 },
|
||||
Package(){0x000AFFFF, 3, 0, 17 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 22 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
Package(){0x0012FFFF, 2, 0, 18 },
|
||||
Package(){0x0012FFFF, 3, 0, 19 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 19 },
|
||||
Package(){0x0013FFFF, 2, 0, 16 },
|
||||
Package(){0x0013FFFF, 3, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTC, 0 },
|
||||
Package(){0x0005FFFF, 1, INTD, 0 },
|
||||
Package(){0x0005FFFF, 2, INTA, 0 },
|
||||
Package(){0x0005FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
Package(){0x0005FFFF, 2, 0, 16 },
|
||||
Package(){0x0005FFFF, 3, 0, 11 },
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe x1 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe x1 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to ethernet */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
})
|
||||
}
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include "northbridge/amd/amdk8/acpi.h"
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/amd/powernow.h>
|
||||
#include <southbridge/amd/sb700/sb700.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
get_bus_conf();
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB700 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,6 +0,0 @@
|
||||
Board name: 939A785GMH/128M
|
||||
Category: desktop
|
||||
Board URL: http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939
|
||||
ROM package: DIP8
|
||||
ROM protocol: SPI
|
||||
Release year: 2009
|
||||
@@ -1,69 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
@@ -1,131 +0,0 @@
|
||||
#Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots)
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_939
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x3060 inherit
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
|
||||
device pci 2.0 on end # PCIE P2P bridge 16x slot
|
||||
device pci 3.0 off end # used in dual slot config
|
||||
device pci 4.0 off end # GPPSB
|
||||
device pci 5.0 off end # GPPSB
|
||||
device pci 6.0 off end # GPPSB
|
||||
device pci 7.0 off end # GPPSB
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end # GPP for x1 slot
|
||||
device pci a.0 on end # GPP for internal network adapter
|
||||
register "gppsb_configuration" = "4" # Configuration ?
|
||||
register "gpp_configuration" = "3" # Configuration D default
|
||||
register "port_enable" = "0x60c"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.1 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.1 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
|
||||
chip superio/winbond/w83627dhg
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
#device pnp 2e.6 off # SPI
|
||||
#end
|
||||
device pnp 2e.307 off # GPIO6
|
||||
end
|
||||
device pnp 2e.8 on # WDTO#, PLED
|
||||
end
|
||||
device pnp 2e.009 on # GPIO2
|
||||
end
|
||||
device pnp 2e.109 on # GPIO3
|
||||
end
|
||||
device pnp 2e.209 on # GPIO4
|
||||
end
|
||||
device pnp 2e.309 off # GPIO5
|
||||
end
|
||||
device pnp 2e.a off # ACPI
|
||||
end
|
||||
device pnp 2e.b on # HWM
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
device pnp 2e.c off # PECI, SST
|
||||
end
|
||||
end #superio/winbond/w8362
|
||||
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # USB 2
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/sb700
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end #northbridge/amd/amdk8
|
||||
end #domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
@@ -1,634 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"ASROCK", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
Name(HPBA, 0xFED00000) /* Base address of HPET table */
|
||||
|
||||
Name(PMOD, One) /* Assume APIC */
|
||||
|
||||
/* PIC IRQ mapping registers, C00h-C01h */
|
||||
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
|
||||
Field(PRQM, ByteAcc, NoLock, Preserve) {
|
||||
PRQI, 0x00000008,
|
||||
PRQD, 0x00000008, /* Offset: 1h */
|
||||
}
|
||||
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
|
||||
PINA, 0x00000008, /* Index 0 */
|
||||
PINB, 0x00000008, /* Index 1 */
|
||||
PINC, 0x00000008, /* Index 2 */
|
||||
PIND, 0x00000008, /* Index 3 */
|
||||
AINT, 0x00000008, /* Index 4 */
|
||||
SINT, 0x00000008, /* Index 5 */
|
||||
, 0x00000008, /* Index 6 */
|
||||
AAUD, 0x00000008, /* Index 7 */
|
||||
AMOD, 0x00000008, /* Index 8 */
|
||||
PINE, 0x00000008, /* Index 9 */
|
||||
PINF, 0x00000008, /* Index A */
|
||||
PING, 0x00000008, /* Index B */
|
||||
PINH, 0x00000008, /* Index C */
|
||||
}
|
||||
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Scope(\_SB) {
|
||||
|
||||
Method(_PIC, 0x01, NotSerialized)
|
||||
{
|
||||
If (Arg0)
|
||||
{
|
||||
\_SB.CIRQ()
|
||||
}
|
||||
Store(Arg0, PMOD)
|
||||
}
|
||||
|
||||
Method(CIRQ, 0x00, NotSerialized){
|
||||
Store(0, PINA)
|
||||
Store(0, PINB)
|
||||
Store(0, PINC)
|
||||
Store(0, PIND)
|
||||
Store(0, PINE)
|
||||
Store(0, PINF)
|
||||
Store(0, PING)
|
||||
Store(0, PINH)
|
||||
}
|
||||
|
||||
Name(IRQB, ResourceTemplate(){
|
||||
IRQ(Level,ActiveLow,Shared){15}
|
||||
})
|
||||
|
||||
Name(IRQP, ResourceTemplate(){
|
||||
IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
|
||||
})
|
||||
|
||||
Name(PITF, ResourceTemplate(){
|
||||
IRQ(Level,ActiveLow,Exclusive){9}
|
||||
})
|
||||
|
||||
Device(INTA) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 1)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINA) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTA._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKA\\_DIS\n") */
|
||||
Store(0, PINA)
|
||||
} /* End Method(_SB.INTA._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKA\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTA._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKA\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINA, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTA._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKA\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINA)
|
||||
} /* End Method(_SB.INTA._SRS) */
|
||||
} /* End Device(INTA) */
|
||||
|
||||
Device(INTB) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 2)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINB) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTB._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKB\\_DIS\n") */
|
||||
Store(0, PINB)
|
||||
} /* End Method(_SB.INTB._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKB\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTB._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKB\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINB, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTB._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKB\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINB)
|
||||
} /* End Method(_SB.INTB._SRS) */
|
||||
} /* End Device(INTB) */
|
||||
|
||||
Device(INTC) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 3)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINC) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTC._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKC\\_DIS\n") */
|
||||
Store(0, PINC)
|
||||
} /* End Method(_SB.INTC._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKC\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTC._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKC\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINC, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTC._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKC\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINC)
|
||||
} /* End Method(_SB.INTC._SRS) */
|
||||
} /* End Device(INTC) */
|
||||
|
||||
Device(INTD) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 4)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PIND) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTD._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKD\\_DIS\n") */
|
||||
Store(0, PIND)
|
||||
} /* End Method(_SB.INTD._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKD\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTD._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKD\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PIND, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTD._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKD\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PIND)
|
||||
} /* End Method(_SB.INTD._SRS) */
|
||||
} /* End Device(INTD) */
|
||||
|
||||
Device(INTE) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 5)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINE) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTE._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKE\\_DIS\n") */
|
||||
Store(0, PINE)
|
||||
} /* End Method(_SB.INTE._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKE\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTE._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKE\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINE, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTE._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKE\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINE)
|
||||
} /* End Method(_SB.INTE._SRS) */
|
||||
} /* End Device(INTE) */
|
||||
|
||||
Device(INTF) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 6)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINF) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTF._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKF\\_DIS\n") */
|
||||
Store(0, PINF)
|
||||
} /* End Method(_SB.INTF._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKF\\_PRS\n") */
|
||||
Return(PITF)
|
||||
} /* Method(_SB.INTF._PRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKF\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINF, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTF._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKF\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINF)
|
||||
} /* End Method(_SB.INTF._SRS) */
|
||||
} /* End Device(INTF) */
|
||||
|
||||
Device(INTG) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 7)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PING) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTG._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_DIS\n") */
|
||||
Store(0, PING)
|
||||
} /* End Method(_SB.INTG._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTG._CRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PING, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTG._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PING)
|
||||
} /* End Method(_SB.INTG._SRS) */
|
||||
} /* End Device(INTG) */
|
||||
|
||||
Device(INTH) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 8)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PINH) {
|
||||
Return(0x0B) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTH._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_DIS\n") */
|
||||
Store(0, PINH)
|
||||
} /* End Method(_SB.INTH._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTH._CRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PINH, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTH._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PINH)
|
||||
} /* End Method(_SB.INTH._SRS) */
|
||||
} /* End Device(INTH) */
|
||||
|
||||
} /* End Scope(_SB) */
|
||||
|
||||
#include <southbridge/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Wake status package */
|
||||
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
|
||||
|
||||
/* _SB.PCI0 */
|
||||
/* Note: Only need HID on Primary Bus */
|
||||
Device(PCI0) {
|
||||
|
||||
Name(_HID, EISAID("PNP0A03"))
|
||||
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
|
||||
Method(_BBN, 0) { /* Bus number = 0 */
|
||||
Return(0)
|
||||
}
|
||||
Method(_STA, 0) {
|
||||
/* DBGO("\\_SB\\PCI0\\_STA\n") */
|
||||
Return(0x0B) /* Status is visible */
|
||||
}
|
||||
|
||||
Method(_PRT,0) {
|
||||
If(PMOD){ Return(APR0) } /* APIC mode */
|
||||
Return (PR0) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
|
||||
/* Describe the Northbridge devices */
|
||||
Device(AMRT) {
|
||||
Name(_ADR, 0x00000000)
|
||||
} /* end AMRT */
|
||||
|
||||
/* The internal GFX bridge */
|
||||
Device(AGPB) {
|
||||
Name(_ADR, 0x00010000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
Return (APR1)
|
||||
}
|
||||
} /* end AGPB */
|
||||
|
||||
/* The external GFX bridge */
|
||||
Device(PBR2) {
|
||||
Name(_ADR, 0x00020000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
If(PMOD){ Return(APS2) } /* APIC mode */
|
||||
Return (PS2) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR2 */
|
||||
|
||||
/* GPP x1 */
|
||||
Device(PBR9) {
|
||||
Name(_ADR, 0x00090000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
If(PMOD){ Return(APS9) } /* APIC mode */
|
||||
Return (PS9) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR9 */
|
||||
|
||||
/* ethernet */
|
||||
Device(PBRa) {
|
||||
Name(_ADR, 0x000A0000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
If(PMOD){ Return(APSa) } /* APIC mode */
|
||||
Return (PSa) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBRa */
|
||||
|
||||
|
||||
/* PCI slot 1, 2, 3 */
|
||||
Device(PIBR) {
|
||||
Name(_ADR, 0x00140004)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
|
||||
Method(_PRT, 0) {
|
||||
Return (PCIB)
|
||||
}
|
||||
}
|
||||
|
||||
Device(LIBR) {
|
||||
Name(_ADR, 0x00140003)
|
||||
/* Method(_INI) {
|
||||
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
|
||||
} */ /* End Method(_SB.SBRDG._INI) */
|
||||
|
||||
/* Real Time Clock Device */
|
||||
Device(RTC0) {
|
||||
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags(){8}
|
||||
IO(Decode16,0x0070, 0x0070, 0, 2)
|
||||
/* IO(Decode16,0x0070, 0x0070, 0, 4) */
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
|
||||
|
||||
Device(TMR) { /* Timer */
|
||||
Name(_HID,EISAID("PNP0100")) /* System Timer */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags(){0}
|
||||
IO(Decode16, 0x0040, 0x0040, 0, 4)
|
||||
/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
|
||||
|
||||
Device(SPKR) { /* Speaker */
|
||||
Name(_HID,EISAID("PNP0800")) /* AT style speaker */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x0061, 0x0061, 0, 1)
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
|
||||
|
||||
Device(PIC) {
|
||||
Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags(){2}
|
||||
IO(Decode16,0x0020, 0x0020, 0, 2)
|
||||
IO(Decode16,0x00A0, 0x00A0, 0, 2)
|
||||
/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
|
||||
/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
|
||||
|
||||
Device(MAD) { /* 8257 DMA */
|
||||
Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
DMA(Compatibility,BusMaster,Transfer8){4}
|
||||
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
|
||||
IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
|
||||
IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
|
||||
IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
|
||||
IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
|
||||
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
|
||||
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
|
||||
|
||||
Device(COPR) {
|
||||
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
|
||||
IRQNoFlags(){13}
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
|
||||
|
||||
Device(HPTM) {
|
||||
Name(_HID,EISAID("PNP0103"))
|
||||
Name(CRS,ResourceTemplate() {
|
||||
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
|
||||
})
|
||||
Method(_STA, 0) {
|
||||
Return(0x0F) /* sata is visible */
|
||||
}
|
||||
Method(_CRS, 0) {
|
||||
CreateDwordField(CRS, ^HPT._BAS, HPBX)
|
||||
Store(HPBA, HPBX)
|
||||
Return(CRS)
|
||||
}
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
|
||||
} /* end LIBR */
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0CF8, // Address Range Minimum
|
||||
0x0CF8, // Address Range Maximum
|
||||
0x01, // Address Alignment
|
||||
0x08, // Address Length
|
||||
)
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0CF8, // Address Length
|
||||
,, , TypeStatic)
|
||||
})
|
||||
/* Methods bellow use SSDT to get actual MMIO regs
|
||||
The IO ports are from 0xd00, optionally an VGA,
|
||||
otherwise the info from MMIO is used.
|
||||
*/
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
} /* End Device(PCI0) */
|
||||
|
||||
} /* End \_SB scope */
|
||||
}
|
||||
/* End of ASL file */
|
||||
@@ -1,109 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
u8 bus_rs780[11];
|
||||
u8 bus_sb700[2];
|
||||
u32 apicid_sb700;
|
||||
|
||||
/*
|
||||
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
* You may need to preset pci1234 for HTIO board,
|
||||
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
*/
|
||||
u32 pci1234x[] = {
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
/*
|
||||
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||
* assume every chain only have 4 ht device at most
|
||||
*/
|
||||
u32 hcdnx[] = {
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
u32 sbdn_rs780;
|
||||
u32 sbdn_sb700;
|
||||
|
||||
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
struct device *dev;
|
||||
int i;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
sbdn_rs780 = sysconf.sbdn;
|
||||
sbdn_sb700 = 0;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
bus_sb700[i] = 0;
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
bus_rs780[i] = 0;
|
||||
}
|
||||
|
||||
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
bus_sb700[0] = bus_rs780[0];
|
||||
|
||||
/* sb700 */
|
||||
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
|
||||
if (dev) {
|
||||
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
|
||||
/* rs780 */
|
||||
for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
|
||||
if (dev) {
|
||||
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
|
||||
apicid_base = get_apicid_base(1);
|
||||
else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
apicid_sb700 = apicid_base + 0;
|
||||
}
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern u8 bus_rs780[8];
|
||||
extern u8 bus_sb700[2];
|
||||
extern unsigned long sbdn_sb700;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_sb700[0];
|
||||
pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
@@ -1,126 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "southbridge/amd/sb700/sb700.h"
|
||||
#include "southbridge/amd/sb700/smbus.h"
|
||||
|
||||
void set_pcie_dereset(void);
|
||||
void set_pcie_reset(void);
|
||||
u8 is_dev3_present(void);
|
||||
|
||||
static void pcie_rst_toggle(u8 val) {
|
||||
u8 byte;
|
||||
|
||||
byte = pm_ioread(0x8d);
|
||||
byte &= ~(3 << 1);
|
||||
pm_iowrite(0x8d, byte);
|
||||
|
||||
byte = pm_ioread(0x94);
|
||||
/* Output enable */
|
||||
byte &= ~(3 << 2);
|
||||
/* Toggle GPM8, GPM9 */
|
||||
byte &= ~(3 << 0);
|
||||
byte |= val;
|
||||
pm_iowrite(0x94, byte);
|
||||
}
|
||||
|
||||
void set_pcie_dereset()
|
||||
{
|
||||
pcie_rst_toggle(0x3);
|
||||
}
|
||||
|
||||
void set_pcie_reset()
|
||||
{
|
||||
pcie_rst_toggle(0x0);
|
||||
}
|
||||
|
||||
#if 0 /* not tested yet */
|
||||
/********************************************************
|
||||
* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
|
||||
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
|
||||
* get the cable type, 40 pin or 80 pin?
|
||||
********************************************************/
|
||||
static void get_ide_dma66(void)
|
||||
{
|
||||
u8 byte;
|
||||
/*u32 sm_dev, ide_dev; */
|
||||
struct device *sm_dev, ide_dev;
|
||||
|
||||
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
||||
|
||||
byte = pci_read_config8(sm_dev, 0xA9);
|
||||
byte |= (1 << 5); /* Set Gpio9 as input */
|
||||
pci_write_config8(sm_dev, 0xA9, byte);
|
||||
|
||||
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
|
||||
byte = pci_read_config8(ide_dev, 0x56);
|
||||
byte &= ~(7 << 0);
|
||||
if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
|
||||
byte |= 2 << 0; /* mode 2 */
|
||||
else
|
||||
byte |= 5 << 0; /* mode 5 */
|
||||
pci_write_config8(ide_dev, 0x56, byte);
|
||||
}
|
||||
#endif /* get_ide_dma66 */
|
||||
|
||||
u8 is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in mahogany board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
|
||||
|
||||
set_pcie_dereset();
|
||||
/* get_ide_dma66(); */
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
||||
/* override the default SATA PHY setup */
|
||||
void sb7xx_51xx_setup_sata_phys(struct device *dev) {
|
||||
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
|
||||
pci_write_config16(dev, 0x86, 0x2c00);
|
||||
|
||||
/* RPR7.6.2 SATA GENI PHY ports setting */
|
||||
pci_write_config32(dev, 0x88, 0x01B48016);
|
||||
pci_write_config32(dev, 0x8c, 0x01B48016);
|
||||
pci_write_config32(dev, 0x90, 0x01B48016);
|
||||
pci_write_config32(dev, 0x94, 0x01B48016);
|
||||
pci_write_config32(dev, 0x98, 0x01B48016);
|
||||
pci_write_config32(dev, 0x9C, 0x01B48016);
|
||||
|
||||
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
|
||||
pci_write_config16(dev, 0xA0, 0xA07A);
|
||||
pci_write_config16(dev, 0xA2, 0xA07A);
|
||||
pci_write_config16(dev, 0xA4, 0xA07A);
|
||||
pci_write_config16(dev, 0xA6, 0xA07A);
|
||||
pci_write_config16(dev, 0xA8, 0xA07A);
|
||||
pci_write_config16(dev, 0xAA, 0xA0FF);
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user