Get the Via EPIA-N(L)/CN400 to a reasonable level of maturity::

Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25 kernel) from SATA HDD. ACPI is working for PCI interrupt routing, some memory stuff and Soft-Off. USB/SATA Working VGA Console Working X Working via Onboard AGP Removed dsdt.c, fixed some whitespace. Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 17:09:46 +00:00
parent b5f4e77bff
commit 1825be291f
19 changed files with 962 additions and 571 deletions
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -1190,6 +1190,8 @@
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e
 #define PCI_DEVICE_ID_VIA_VT8237R_UHCI	0x3038
 #define PCI_DEVICE_ID_VIA_VT8237R_EHCI	0x3104
 #define PCI_DEVICE_ID_VIA_VX855_LPC	0x8353
 #define PCI_DEVICE_ID_VIA_VX855_IDE	0x5324
 #define PCI_DEVICE_ID_VIA_VX855_VGA	0x5122
--- a/src/mainboard/via/epia-n/Config.lb
+++ b/src/mainboard/via/epia-n/Config.lb
@@ -42,7 +42,12 @@ if CONFIG_HAVE_MP_TABLE object mptable.o end
 if CONFIG_HAVE_ACPI_TABLES
 #acpi_create_fadt is located in VT8237R code
-	object dsdt.o
+	makerule dsdt.c
 		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
 		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
 		action  "mv dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o
 	object acpi_tables.o
 end
 makerule ./failover.E
@@ -141,13 +146,14 @@ chip northbridge/via/cn400			# Northbridge
      register "ide1_80pin_cable" = "0"
      device pci f.0 on end			# IDE/SATA
 	  device pci f.1 on end			# IDE
-      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_lo" = "0xC0"    # Disable AC/MC97
-      register "fn_ctrl_hi" = "0x1d"
+      register "fn_ctrl_hi" = "0x9d"    # Disable USB Direct & LAN Gating
      device pci 10.0 on end			# OHCI
      device pci 10.1 on end			# OHCI
      device pci 10.2 on end			# OHCI
      device pci 10.3 on end			# OHCI
      device pci 10.4 on end			# EHCI
      device pci 10.5 off end			# USB Direct
      device pci 11.0 on			# Southbridge LPC
        chip superio/winbond/w83697hf		# Super I/O
          device pnp 2e.0 off			# Floppy
@@ -190,7 +196,7 @@ chip northbridge/via/cn400			# Northbridge
        end
      end
      device pci 11.5 off end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 Modem
+      device pci 11.6 off end			# AC'97 Modem
      device pci 12.0 on end			# Ethernet
    end
  end
--- a/src/mainboard/via/epia-n/Options.lb
+++ b/src/mainboard/via/epia-n/Options.lb
@@ -19,7 +19,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_FAILOVER_BOOT
@@ -53,6 +52,7 @@ uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
 uses CONFIG_SMP
 uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -73,12 +73,13 @@ uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 uses CONFIG_COMPRESS
 uses CONFIG_EPIA_VT8237R_INIT
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 default CONFIG_EPIA_VT8237R_INIT = 1
 #default CONFIG_LB_MEM_TOPK = 4 * 1024
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_COMPRESS = 1
-default CONFIG_IOAPIC = 0
+default CONFIG_IOAPIC = 1
 default CONFIG_VIDEO_MB = 64
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
@@ -86,13 +87,14 @@ default CONFIG_CONSOLE_VGA = 0
 default CONFIG_HAVE_FAILOVER_BOOT = 0
 default CONFIG_USE_FAILOVER_IMAGE = 0
 default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_SMP = 1
 default CONFIG_HAVE_MP_TABLE = 1
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_HAVE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9
+default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_HAVE_ACPI_TABLES = 0
+default CONFIG_HAVE_ACPI_TABLES = 1
 default CONFIG_HAVE_OPTION_TABLE = 1
 #default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
 #default CONFIG_PAYLOAD_SIZE = 125 * 1024
@@ -110,6 +112,7 @@ default CONFIG_CROSS_COMPILE = ""
 default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
 default HOSTCC = "gcc"
 #default CONFIG_MAINBOARD = "EPIA-N"
 default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
 ##
 ## Set this to the max PCI bus number you would ever use for PCI config I/O.
--- a/src/mainboard/via/epia-n/acpi_tables.c
+++ b/src/mainboard/via/epia-n/acpi_tables.c
@@ -5,14 +5,54 @@
 * Nick Barker <nick.barker9@btinternet.com>, and those portions
 * (C) Copyright 2004 Nick Barker
 * (C) Copyright 2005 Stefan Reinauer
 * (C) Copyright 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 /*
 * Most parts of this file copied from via\epia-m\acpi_tables.c,
 * and via\epia-m700\acpi_tables.c
 */
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "../../../southbridge/via/vt8237r/vt8237r.h"
 extern unsigned char AmlCode[];
 /*
 * These four macros are copied from <arch/smp/mpspec.h>, I have to do this
 * since the "default CONFIG_HAVE_MP_TABLE = 0" in Options.lb, and also since
 * mainboard/via/... have no mptable.c (so that I can not set
 * CONFIG_HAVE_MP_TABLE = 1) as many other mainboards.
 * So I have to copy these four to here. acpi_fill_madt() needs this.
 */
 #define MP_IRQ_POLARITY_DEFAULT	0x0
 #define MP_IRQ_POLARITY_HIGH	0x1
 #define MP_IRQ_POLARITY_LOW		0x3
 #define MP_IRQ_POLARITY_MASK    0x3
 #define MP_IRQ_TRIGGER_DEFAULT	0x0
 #define MP_IRQ_TRIGGER_EDGE		0x4
 #define MP_IRQ_TRIGGER_LEVEL	0xc
 #define MP_IRQ_TRIGGER_MASK     0xc
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	/* Nothing to do */
@@ -25,9 +65,49 @@ unsigned long acpi_fill_slit(unsigned long current)
 	return current;
 }
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
 					  u8 lint)
 {
 	device_t cpu;
 	int cpu_index = 0;
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
 		    (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
 			continue;
 		}
 		if (!cpu->enabled)
 			continue;
 		current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
 					      current, cpu_index, flags, lint);
 		cpu_index++;
 	}
 	return current;
 }
 unsigned long acpi_fill_madt(unsigned long current)
 {
-	/* Nothing to do */
+	unsigned int gsi_base = 0x00;
 	/* Create all subtables for processors. */
 	current = acpi_create_madt_lapics(current);
 	/* Write SB IOAPIC. */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
 				   VT8237R_APIC_ID, VT8237R_APIC_BASE, gsi_base);
 	/* IRQ0 -> APIC IRQ2. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 						current, 0, 0, 2, 0x0);
 	/* IRQ9 ACPI active low. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
 	/* Create all subtables for processors. */
 	current = acpi_create_madt_lapic_nmis(current,
 			      MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
 	return current;
 }
@@ -37,12 +117,16 @@ unsigned long acpi_fill_srat(unsigned long current)
 	return current;
 }
 #define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 #define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
-	acpi_hpet_t *hpet;
+	acpi_xsdt_t *xsdt;
 	acpi_madt_t *madt;
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
@@ -70,10 +154,12 @@ unsigned long write_acpi_tables(unsigned long start)
 	 * We explicitly add these tables later on:
 	 */
 	printk_debug("ACPI:     * FACS\n");
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 	printk_debug("ACPI:     * DSDT\n");
 	dsdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
@@ -88,6 +174,13 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_create_fadt(fadt,facs,dsdt);
 	acpi_add_table(rsdp,fadt);
 	/* If we want IOAPIC Support Linux wants it in MADT. */
 	printk_debug("ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 	printk_info("ACPI: done.\n");
 	return current;
 }
--- a/src/mainboard/via/epia-n/auto.c
+++ b/src/mainboard/via/epia-n/auto.c
@@ -73,13 +73,6 @@ static void enable_mainboard_devices(void)
 	device_t dev;
 	u8 reg;
 	dev = pci_locate_device(PCI_ID(0x1106, 0x7259), 0);
 	if (dev == PCI_DEV_INVALID)
 		die("Northbridge V-Link not found!!!\n");
 	pci_write_config8(dev, 0x4F, 0x01);
 	pci_write_config8(dev, 0x48, 0x13);
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 	if (dev == PCI_DEV_INVALID)
 		die("Southbridge not found!!!\n");
@@ -93,7 +86,7 @@ static void enable_mainboard_devices(void)
 	 *   2 16.2 USB 3
 	 *   1 16.4 USB EHCI
 	 */
-	pci_write_config8(dev, 0x50, 0x80);
+	pci_write_config8(dev, 0x50, 0xC0);
 	/*bit=0 means enable internal function (per VT8237R datasheet)
 	 *   7 USB Device Mode
@@ -106,7 +99,7 @@ static void enable_mainboard_devices(void)
 	 *   1 Internal KBC Configuration
 	 *   0 Internal Keyboard Controller
 	 */
-	pci_write_config8(dev, 0x51, 0x1d);
+	pci_write_config8(dev, 0x51, 0x9d);
 }
 static void enable_shadow_ram(void) 
--- a/src/mainboard/via/epia-n/dsdt.asl
+++ b/src/mainboard/via/epia-n/dsdt.asl
@@ -1,255 +1,352 @@
 /*
- * Minimalist ACPI DSDT table for EPIA-M / MII
+ * Minimalist ACPI DSDT table for EPIA-N / NL
 * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
 * Heavily based on EPIA-M dstd.asl
 * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
 *
 * 
 */
-
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1)
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 {
-	/*  
+    Scope (\_PR)
-	 * Define the main processor
+    {
-	 */
+        Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {}
-	Scope (\_PR)
+    }
 	{
 		Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
 	}
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on
 	 *  - S5 which is soft off
 	 * any others would involve declaring the wake up methods
 	 */
-	Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+    Name (\_S0, Package (0x04)
-	Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+    {
        0x00,
        0x00,
        0x00,
        0x00
    })
    Name (\_S5, Package (0x04)
    {
        0x02,
        0x02,
        0x02,
        0x02
    })
 	/* Global Flag Used to Indicate State of */
 	/* ATA Interface                         */
    Name (ATFL, 0x00)
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
-    	{
+    {
 		/* Define how interrupt Link A is plumbed in */ 
 		Device (LNKA)
 		{
 			Name (_HID, EisaId ("PNP0C0F"))
 			Name (_UID, 0x01)
 			/* Status - always return ready */
 			Method (_STA, 0, NotSerialized)
 			{
 				Return (0x0B)
 			}
 			/* Current Resources - return irq set up in BIOS */  
 			Method (_CRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
 				{
 					IRQ (Level, ActiveLow, Shared) {5}
 				})
 				Return (BUFF)
                	}
 			/* Possible Resources - return the range of irqs
 			 * we are using for PCI - only here to keep Linux ACPI
 			 * happy 
 			 */
 			Method (_PRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
                    		{
 					IRQ (Level, ActiveLow, Shared) {5,9,10}
                    		})
                    		Return (BUFF)
                	}
 			/* Set Resources - dummy function to keep Linux ACPI happy
                         * Linux is more than happy not to tinker with irq
 			 * assignments as long as the CRS and STA functions 
 			 * return good values
 			 */
 			Method (_SRS, 1, NotSerialized ) {}
 			/* Disable - dummy function to keep Linux ACPI happy */
 			Method (_DIS, 0, NotSerialized ) {}
 		} // End of LNKA 
-		/* Define how interrupt Link B is plumbed in */ 
+       Device (PCI0)
-		Device (LNKB)
+       {
-		{
+           Name (_HID, EisaId ("PNP0A03"))
-			Name (_HID, EisaId ("PNP0C0F"))
+           Name (_ADR, 0x00)
-			Name (_UID, 0x02)
+           Name (_UID, 0x01)
-			/* Status - always return ready */
+           Name (_BBN, 0x00)
 			Method (_STA, 0, NotSerialized)
 			{
 				Return (0x0B)
 			}
 			/* Current Resources - return irq set up in BIOS */  
 			Method (_CRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
 				{
 					IRQ (Level, ActiveLow, Shared) {9}
 				})
 				Return (BUFF)
                	}
 			/* Possible Resources - return the range of irqs
 			 * we are using for PCI - only here to keep Linux ACPI
 			 * happy 
 			 */
 			Method (_PRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
                    		{
 					IRQ (Level, ActiveLow, Shared) {5,9,10}
                    		})
                    		Return (BUFF)
                	}
 			/* Set Resources - dummy function to keep Linux ACPI happy
                         * Linux is more than happy not to tinker with irq
 			 * assignments as long as the CRS and STA functions 
 			 * return good values
 			 */
 			Method (_SRS, 1, NotSerialized ) {}
 			/* Disable - dummy function to keep Linux ACPI happy */
 			Method (_DIS, 0, NotSerialized ) {}
 		} // End of LNKB
-		/* Define how interrupt Link C is plumbed in */ 
+	       /* PCI Routing Table */
-		Device (LNKC)
+	       Name (_PRT, Package () {
 		{
 			Name (_HID, EisaId ("PNP0C0F"))
 			Name (_UID, 0x03)
 			/* Status - always return ready */
 			Method (_STA, 0, NotSerialized)
 			{
 				Return (0x0B)
 			}
 			/* Current Resources - return irq set up in BIOS */  
 			Method (_CRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
 				{
 					IRQ (Level, ActiveLow, Shared) {9}
 				})
 				Return (BUFF)
                	}
 			/* Possible Resources - return the range of irqs
 			 * we are using for PCI - only here to keep Linux ACPI
 			 * happy 
 			 */
 			Method (_PRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
                    		{
 					IRQ (Level, ActiveLow, Shared) {5,9,10}
                    		})
                    		Return (BUFF)
                	}
 			/* Set Resources - dummy function to keep Linux ACPI happy
                         * Linux is more than happy not to tinker with irq
 			 * assignments as long as the CRS and STA functions 
 			 * return good values
 			 */
 			Method (_SRS, 1, NotSerialized ) {}
 			/* Disable - dummy function to keep Linux ACPI happy */
 			Method (_DIS, 0, NotSerialized ) {}
 		} // End of LNKC
-		/* Define how interrupt Link D is plumbed in */ 
+        	   Package (0x04) {0x000FFFFF, 0x00, ATAI, 0x00}, // SATA Link A
-		Device (LNKD)
+        	   Package (0x04) {0x000FFFFF, 0x01, ATAI, 0x00}, // SATA Link B
-		{
+        	   Package (0x04) {0x000FFFFF, 0x02, ATAI, 0x00}, // SATA Link C
-			Name (_HID, EisaId ("PNP0C0F"))
+        	   Package (0x04) {0x000FFFFF, 0x03, ATAI, 0x00}, // SATA Link D
 			Name (_UID, 0x04)
 			/* Status - always return ready */
 			Method (_STA, 0, NotSerialized)
 			{
 				Return (0x0B)
 			}
 			/* Current Resources - return irq set up in BIOS */  
 			Method (_CRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
 				{
 					IRQ (Level, ActiveLow, Shared) {5}
 				})
 				Return (BUFF)
                	}
 			/* Possible Resources - return the range of irqs
 			 * we are using for PCI - only here to keep Linux ACPI
 			 * happy 
 			 */
 			Method (_PRS, 0, NotSerialized)
 			{
 				Name (BUFF, ResourceTemplate ()
                    		{
 					IRQ (Level, ActiveLow, Shared) {5,9,10}
                    		})
                    		Return (BUFF)
                	}
 			/* Set Resources - dummy function to keep Linux ACPI happy
                         * Linux is more than happy not to tinker with irq
 			 * assignments as long as the CRS and STA functions 
 			 * return good values
 			 */
 			Method (_SRS, 1, NotSerialized ) {}
 			/* Disable - dummy function to keep Linux ACPI happy */
 			Method (_DIS, 0, NotSerialized ) {}
 		} // End of LNKD 
- 
+        	   Package (0x04) {0x0010FFFF, 0x00, USBI, 0x00}, // USB Link A
-		/* top PCI device */
+        	   Package (0x04) {0x0010FFFF, 0x01, USBI, 0x00}, // USB Link B
-		Device (PCI0)
+        	   Package (0x04) {0x0010FFFF, 0x02, USBI, 0x00}, // USB Link C
-		{
+        	   Package (0x04) {0x0010FFFF, 0x03, USBI, 0x00}, // USB Link D
 			Name (_HID, EisaId ("PNP0A03"))
 			Name (_ADR, 0x00)
 			Name (_UID, 0x00)
 			Name (_BBN, 0x00)
-			/* PCI Routing Table */
+        	   Package (0x04) {0x0011FFFF, 0x00, VT8I, 0x00}, // VT8237 Link A
-			Name (_PRT, Package () {
+        	   Package (0x04) {0x0011FFFF, 0x01, VT8I, 0x00}, // VT8237 Link B
-				/* Epia-MII 6000e cardbus: */
+        	   Package (0x04) {0x0011FFFF, 0x02, VT8I, 0x00}, // VT8237 Link C
-				Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A
+        	   Package (0x04) {0x0011FFFF, 0x03, VT8I, 0x00}, // VT8237 Link D
 				Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B
 				Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C
 				Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
-				Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
+        	   Package (0x04) {0x0012FFFF, 0x00, NICI, 0x00}, // LAN Link A
-				Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
+        	   Package (0x04) {0x0012FFFF, 0x01, NICI, 0x00}, // LAN Link B
-				Package () {0x000DFFFF, 0x02, LNKD, 0x00}, // Firewire Linc D
+        	   Package (0x04) {0x0012FFFF, 0x02, NICI, 0x00}, // LAN Link C
-				Package () {0x000DFFFF, 0x03, LNKA, 0x00}, // Firewire Link A
+        	   Package (0x04) {0x0012FFFF, 0x03, NICI, 0x00}, // LAN Link D
-				Package () {0x0010FFFF, 0x00, LNKA, 0x00}, // USB Link A
+        	   Package (0x04) {0x0001FFFF, 0x00, 0, 0x10}, // VGA Link A (GSI)
-				Package () {0x0010FFFF, 0x01, LNKB, 0x00}, // USB Link B
+        	   Package (0x04) {0x0001FFFF, 0x01, 0, 0x11}, // VGA Link B (GSI)
-				Package () {0x0010FFFF, 0x02, LNKC, 0x00}, // USB Link C
+        	   Package (0x04) {0x0001FFFF, 0x02, 0, 0x12}, // VGA Link C (GSI)
-				Package () {0x0010FFFF, 0x03, LNKD, 0x00}, // USB Link D
+        	   Package (0x04) {0x0001FFFF, 0x03, 0, 0x13}, // VGA Link D (GSI)
-				Package () {0x0011FFFF, 0x00, LNKA, 0x00}, // vt8623 Link A
+        	   Package (0x04) {0x0014FFFF, 0x00, 0, 0x12}, // Slot 1 Link C (GSI)
-				Package () {0x0011FFFF, 0x01, LNKB, 0x00}, // vt8623 Link B
+        	   Package (0x04) {0x0014FFFF, 0x01, 0, 0x13}, // Slot 1 Link D (GSI)
-				Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vt8623 Link C
+        	   Package (0x04) {0x0014FFFF, 0x02, 0, 0x10}, // Slot 1 Link A (GSI)
-				Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vt8623 Link D
+        	   Package (0x04) {0x0014FFFF, 0x03, 0, 0x11}, // Slot 1 Link B (GSI)
-				Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A 
+        	   Package (0x04) {0x0013FFFF, 0x00, 0, 0x13}, // Riser Slot Link D (GSI)
-				Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B
+        	   Package (0x04) {0x0013FFFF, 0x01, 0, 0x12}, // Riser Slot Link C (GSI)
-				Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C
+        	   Package (0x04) {0x0013FFFF, 0x02, 0, 0x11}, // Riser Slot Link B (GSI)
-				Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D
+        	   Package (0x04) {0x0013FFFF, 0x03, 0, 0x10} // Riser Slot Link A (GSI)
-				Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA 
+	       })
 				Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB
 				Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC
 				Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD
-				Package () {0x0014FFFF, 0x00, LNKB, 0x00}, // Slot 1, Link B
+		   /* PCI Devices Included Here */
-				Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C
+		   Include("sb_physical.asl")
 				Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D
 				Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A
 				Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A
 				Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B
 				Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C
 				Package () {0x0001FFFF, 0x03, LNKD, 0x00} // VGA Link D
-            		})
+		   /* Legacy PNP Devices Defined Here */
 		   /* Disable PS2 Mouse Support */
           Device (PS2M)
           {
        	   Name (_HID, EisaId ("PNP0F13"))
        	   Method (_STA, 0, NotSerialized)
        	   {
       			   Return (0x09)
        	   }
-		} // End of PCI0
+        	   Method (_CRS, 0, NotSerialized)
        	   {
        		   Name (BUF1, ResourceTemplate ()
        		   {
        			   IRQNoFlags ()
        				   {12}
        		   })
        		   Return (BUF1)
        	   }
           }
 		   /* Disable Legacy PS2 Keyboard Support */
           Device (PS2K)
           {
         	   Name (_HID, EisaId ("PNP0303"))
         	   Name (_CID, 0x0B03D041)
         	   Method (_STA, 0, NotSerialized)
         	   {
         			Return (0x09)
         	   }
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x0060,  		   // Range Minimum
         			   0x0060,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x01,			   // Length
         			   )
         		   IO (Decode16,
         			   0x0064,  		   // Range Minimum
         			   0x0064,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x01,			   // Length
         			   )
         		   IRQNoFlags ()
         			   {1}
         	   })
           }
 		   /* Legacy PIC Description */
           Device (PIC)
           {
         	   Name (_HID, EisaId ("PNP0000"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x0020,  		   // Range Minimum
         			   0x0020,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x02,			   // Length
         			   )
         		   IO (Decode16,
         			   0x00A0,  		   // Range Minimum
         			   0x00A0,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x02,			   // Length
         			   )
         		   IRQNoFlags ()
         			   {2}
         	   })
           }
 		   /* Legacy DMA Description */
           Device (DMA1)
           {
         	   Name (_HID, EisaId ("PNP0200"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   DMA (Compatibility, BusMaster, Transfer8, )
         			   {4}
         		   IO (Decode16,
         			   0x0000,  		   // Range Minimum
         			   0x0000,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x10,			   // Length
         			   )
         		   IO (Decode16,
         			   0x0080,  		   // Range Minimum
         			   0x0080,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x11,			   // Length
         			   )
         		   IO (Decode16,
         			   0x0094,  		   // Range Minimum
         			   0x0094,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x0C,			   // Length
         			   )
         		   IO (Decode16,
         			   0x00C0,  		   // Range Minimum
         			   0x00C0,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x20,			   // Length
         			   )
         	   })
           }
 		   /* Legacy Timer Description */
           Device (TMR)
           {
         	   Name (_HID, EisaId ("PNP0100"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x0040,  		   // Range Minimum
         			   0x0040,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x04,			   // Length
         			   )
         		   IRQNoFlags ()
         			   {0}
         	   })
           }
 		   /* Legacy RTC Description */
           Device (RTC)
           {
         	   Name (_HID, EisaId ("PNP0B00"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x0070,  		   // Range Minimum
         			   0x0070,  		   // Range Maximum
         			   0x04,			   // Alignment
         			   0x04,			   // Length
         			   )
         		   IRQNoFlags ()
         			   {8}
         	   })
           }
 		   /* Legacy Speaker Description */
           Device (SPKR)
           {
         	   Name (_HID, EisaId ("PNP0800"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x0061,  		   // Range Minimum
         			   0x0061,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x01,			   // Length
         			   )
         	   })
           }
 		   /* Legacy Math Co-Processor Description */
           Device (COPR)
           {
         	   Name (_HID, EisaId ("PNP0C04"))
         	   Name (_CRS, ResourceTemplate ()
         	   {
         		   IO (Decode16,
         			   0x00F0,  		   // Range Minimum
         			   0x00F0,  		   // Range Maximum
         			   0x01,			   // Alignment
         			   0x10,			   // Length
         			   )
         		   IRQNoFlags ()
         			   {13}
         	   })
           }
 		   /* General Legacy IO Reservations                   */
 		   /* Covering items that are not explicitly reserved  */
 		   /* from coreboot.                                   */
           Device (SYSR)
           {
               Name (_HID, EisaId ("PNP0C02"))
               Name (_UID, 0x01)
               Name (_CRS, ResourceTemplate ()
               {
            	   IO (Decode16,
            		   0x0010,  		   // Range Minimum
            		   0x0010,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x10,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0022,  		   // Range Minimum
            		   0x0022,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x1E,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0044,  		   // Range Minimum
            		   0x0044,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x1C,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0062,  		   // Range Minimum
            		   0x0062,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x02,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0065,  		   // Range Minimum
            		   0x0065,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x0B,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0074,  		   // Range Minimum
            		   0x0074,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x0C,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0091,  		   // Range Minimum
            		   0x0091,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x03,			   // Length
            		   )
            	   IO (Decode16,
            		   0x00A2,  		   // Range Minimum
            		   0x00A2,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x1E,			   // Length
            		   )
            	   IO (Decode16,
            		   0x00E0,  		   // Range Minimum
            		   0x00E0,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x10,			   // Length
            		   )
            	   IO (Decode16,
            		   0x04D0,  		   // Range Minimum
            		   0x04D0,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x02,			   // Length
            		   )
            	   IO (Decode16,
            		   0x0294,  		   // Range Minimum
            		   0x0294,  		   // Range Maximum
            		   0x01,			   // Alignment
            		   0x04,			   // Length
            		   )
               })
           }
 		   Include("irq_links.asl")
 		   Include("pci_init.asl")
 	   } //End of PCI0
 	} // End of _SB
--- a/src/mainboard/via/epia-n/dsdt.c
+++ b/src/mainboard/via/epia-n/dsdt.c
@@ -1,142 +0,0 @@
 /*
 * 
 * Intel ACPI Component Architecture
 * ASL Optimizing Compiler version 20060127 [Apr 23 2006]
 * Copyright (C) 2000 - 2006 Intel Corporation
 * Supports ACPI Specification Revision 3.0a
 * 
 * Compilation of "dsdt.asl" - Wed Sep  6 11:36:08 2006
 * 
 * C source code output
 *
 */
 unsigned char AmlCode[] =
 {
    0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00,  /* 00000000    "DSDT...." */
    0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53,  /* 00000008    "..LXBIOS" */
    0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54,  /* 00000010    "LXB-DSDT" */
    0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,  /* 00000018    "....INTL" */
    0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50,  /* 00000020    "'.. .._P" */
    0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55,  /* 00000028    "R_[..CPU" */
    0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08,  /* 00000030    "0......." */
    0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00,  /* 00000038    "_S0_...." */
    0x00,0x00,0x00,0x08,0x5F,0x53,0x35,0x5F,  /* 00000040    "...._S5_" */
    0x12,0x08,0x04,0x0A,0x02,0x0A,0x02,0x00,  /* 00000048    "........" */
    0x00,0x10,0x4E,0x39,0x5F,0x53,0x42,0x5F,  /* 00000050    "..N9_SB_" */
    0x5B,0x82,0x44,0x06,0x4C,0x4E,0x4B,0x41,  /* 00000058    "[.D.LNKA" */
    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 00000060    "._HID.A." */
    0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x01,  /* 00000068    "..._UID." */
    0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,  /* 00000070    ".._STA.." */
    0x0A,0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,  /* 00000078    "...._CRS" */
    0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09,  /* 00000080    "..BUFF.." */
    0x0A,0x06,0x23,0x20,0x00,0x18,0x79,0x00,  /* 00000088    "..# ..y." */
    0xA4,0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,  /* 00000090    ".BUFF.._" */
    0x50,0x52,0x53,0x00,0x08,0x42,0x55,0x46,  /* 00000098    "PRS..BUF" */
    0x46,0x11,0x09,0x0A,0x06,0x23,0x20,0x06,  /* 000000A0    "F....# ." */
    0x18,0x79,0x00,0xA4,0x42,0x55,0x46,0x46,  /* 000000A8    ".y..BUFF" */
    0x14,0x06,0x5F,0x53,0x52,0x53,0x01,0x14,  /* 000000B0    ".._SRS.." */
    0x06,0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,  /* 000000B8    "._DIS.[." */
    0x45,0x06,0x4C,0x4E,0x4B,0x42,0x08,0x5F,  /* 000000C0    "E.LNKB._" */
    0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,  /* 000000C8    "HID.A..." */
    0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14,  /* 000000D0    "._UID..." */
    0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,  /* 000000D8    "._STA..." */
    0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,  /* 000000E0    "..._CRS." */
    0x08,0x42,0x55,0x46,0x46,0x11,0x09,0x0A,  /* 000000E8    ".BUFF..." */
    0x06,0x23,0x00,0x02,0x18,0x79,0x00,0xA4,  /* 000000F0    ".#...y.." */
    0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,  /* 000000F8    "BUFF.._P" */
    0x52,0x53,0x00,0x08,0x42,0x55,0x46,0x46,  /* 00000100    "RS..BUFF" */
    0x11,0x09,0x0A,0x06,0x23,0x20,0x06,0x18,  /* 00000108    "....# .." */
    0x79,0x00,0xA4,0x42,0x55,0x46,0x46,0x14,  /* 00000110    "y..BUFF." */
    0x06,0x5F,0x53,0x52,0x53,0x01,0x14,0x06,  /* 00000118    "._SRS..." */
    0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,0x45,  /* 00000120    "_DIS.[.E" */
    0x06,0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48,  /* 00000128    ".LNKC._H" */
    0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,  /* 00000130    "ID.A...." */
    0x5F,0x55,0x49,0x44,0x0A,0x03,0x14,0x09,  /* 00000138    "_UID...." */
    0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,  /* 00000140    "_STA...." */
    0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,  /* 00000148    ".._CRS.." */
    0x42,0x55,0x46,0x46,0x11,0x09,0x0A,0x06,  /* 00000150    "BUFF...." */
    0x23,0x00,0x02,0x18,0x79,0x00,0xA4,0x42,  /* 00000158    "#...y..B" */
    0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,  /* 00000160    "UFF.._PR" */
    0x53,0x00,0x08,0x42,0x55,0x46,0x46,0x11,  /* 00000168    "S..BUFF." */
    0x09,0x0A,0x06,0x23,0x20,0x06,0x18,0x79,  /* 00000170    "...# ..y" */
    0x00,0xA4,0x42,0x55,0x46,0x46,0x14,0x06,  /* 00000178    "..BUFF.." */
    0x5F,0x53,0x52,0x53,0x01,0x14,0x06,0x5F,  /* 00000180    "_SRS..._" */
    0x44,0x49,0x53,0x00,0x5B,0x82,0x45,0x06,  /* 00000188    "DIS.[.E." */
    0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49,  /* 00000190    "LNKD._HI" */
    0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,  /* 00000198    "D.A...._" */
    0x55,0x49,0x44,0x0A,0x04,0x14,0x09,0x5F,  /* 000001A0    "UID...._" */
    0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,0x14,  /* 000001A8    "STA....." */
    0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,0x42,  /* 000001B0    "._CRS..B" */
    0x55,0x46,0x46,0x11,0x09,0x0A,0x06,0x23,  /* 000001B8    "UFF....#" */
    0x20,0x00,0x18,0x79,0x00,0xA4,0x42,0x55,  /* 000001C0    " ..y..BU" */
    0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,0x53,  /* 000001C8    "FF.._PRS" */
    0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09,  /* 000001D0    "..BUFF.." */
    0x0A,0x06,0x23,0x20,0x06,0x18,0x79,0x00,  /* 000001D8    "..# ..y." */
    0xA4,0x42,0x55,0x46,0x46,0x14,0x06,0x5F,  /* 000001E0    ".BUFF.._" */
    0x53,0x52,0x53,0x01,0x14,0x06,0x5F,0x44,  /* 000001E8    "SRS..._D" */
    0x49,0x53,0x00,0x5B,0x82,0x4B,0x1F,0x50,  /* 000001F0    "IS.[.K.P" */
    0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44,  /* 000001F8    "CI0._HID" */
    0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41,  /* 00000200    ".A...._A" */
    0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44,  /* 00000208    "DR.._UID" */
    0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08,  /* 00000210    ".._BBN.." */
    0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20,  /* 00000218    "_PRT.C. " */
    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00,  /* 00000220    "........" */
    0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 00000228    ".LNKA..." */
    0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C,  /* 00000230    ".......L" */
    0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,  /* 00000238    "NKB....." */
    0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E,  /* 00000240    "......LN" */
    0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,  /* 00000248    "KC......" */
    0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B,  /* 00000250    ".....LNK" */
    0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000258    "D......." */
    0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00,  /* 00000260    "...LNKB." */
    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00,  /* 00000268    "........" */
    0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,  /* 00000270    ".LNKC..." */
    0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x02,  /* 00000278    "........" */
    0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04,  /* 00000280    "LNKD...." */
    0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x03,0x4C,  /* 00000288    ".......L" */
    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 00000290    "NKA....." */
    0xFF,0xFF,0x10,0x00,0x00,0x4C,0x4E,0x4B,  /* 00000298    ".....LNK" */
    0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 000002A0    "A......." */
    0x10,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00,  /* 000002A8    "...LNKB." */
    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,  /* 000002B0    "........" */
    0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12,  /* 000002B8    "..LNKC.." */
    0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,0x0A,  /* 000002C0    "........" */
    0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D,  /* 000002C8    ".LNKD..." */
    0x04,0x0C,0xFF,0xFF,0x11,0x00,0x00,0x4C,  /* 000002D0    ".......L" */
    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 000002D8    "NKA....." */
    0xFF,0xFF,0x11,0x00,0x01,0x4C,0x4E,0x4B,  /* 000002E0    ".....LNK" */
    0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,  /* 000002E8    "B......." */
    0x11,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,  /* 000002F0    "....LNKC" */
    0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x11,  /* 000002F8    "........" */
    0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,  /* 00000300    "...LNKD." */
    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x12,0x00,  /* 00000308    "........" */
    0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 00000310    ".LNKA..." */
    0x04,0x0C,0xFF,0xFF,0x12,0x00,0x01,0x4C,  /* 00000318    ".......L" */
    0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,  /* 00000320    "NKB....." */
    0xFF,0xFF,0x12,0x00,0x0A,0x02,0x4C,0x4E,  /* 00000328    "......LN" */
    0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,  /* 00000330    "KC......" */
    0xFF,0x12,0x00,0x0A,0x03,0x4C,0x4E,0x4B,  /* 00000338    ".....LNK" */
    0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000340    "D......." */
    0x13,0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00,  /* 00000348    "...LNKA." */
    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x13,0x00,  /* 00000350    "........" */
    0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E,  /* 00000358    ".LNKB..." */
    0x04,0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x02,  /* 00000360    "........" */
    0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04,  /* 00000368    "LNKC...." */
    0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x03,0x4C,  /* 00000370    ".......L" */
    0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C,  /* 00000378    "NKD....." */
    0xFF,0xFF,0x14,0x00,0x00,0x4C,0x4E,0x4B,  /* 00000380    ".....LNK" */
    0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000388    "B......." */
    0x14,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00,  /* 00000390    "...LNKC." */
    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,  /* 00000398    "........" */
    0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12,  /* 000003A0    "..LNKD.." */
    0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,0x0A,  /* 000003A8    "........" */
    0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 000003B0    ".LNKA..." */
    0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,  /* 000003B8    ".......L" */
    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 000003C0    "NKA....." */
    0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B,  /* 000003C8    ".....LNK" */
    0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,  /* 000003D0    "B......." */
    0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,  /* 000003D8    "....LNKC" */
    0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,  /* 000003E0    "........" */
    0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,  /* 000003E8    "...LNKD." */
 };
--- a/src/mainboard/via/epia-n/fadt.c
+++ b/src/mainboard/via/epia-n/fadt.c
@@ -1,6 +1,7 @@
 /*
 * ACPI - create the Fixed ACPI Description Tables (FADT)
 * (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com>
 * (C) Copyright 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
 *
 *
 * This program is free software; you can redistribute it and/or
@@ -22,6 +23,7 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include "../../../southbridge/via/vt8237r/vt8237r.h"
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	acpi_header_t *header=&(fadt->header);
@@ -38,7 +40,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	fadt->firmware_ctrl=facs;
 	fadt->dsdt= dsdt;
 	fadt->preferred_pm_profile=0;
-	fadt->sci_int=5;
+	fadt->sci_int=VT8237R_ACPI_IRQ;
 	fadt->smi_cmd = 0;
 	fadt->acpi_enable = 0;
 	fadt->acpi_disable = 0;
--- a/src/mainboard/via/epia-n/irq_tables.c
+++ b/src/mainboard/via/epia-n/irq_tables.c
@@ -1,53 +1,47 @@
-/*
+/* This file was generated by getpir.c, do not modify!
- * This file is part of the coreboot project.
+ * (but if you do, please run checkpir on it to verify)
 *
- * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
+ * Contains the IRQ Routing Table dumped directly from your
 * memory, which BIOS sets up.
 *
- * This program is free software; you can redistribute it and/or modify
+ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 #ifdef GETPIR
 #include "pirq_routing.h"
 #else
 #include <arch/pirq_routing.h>
 #endif
 const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
+	PIRQ_VERSION,    /* u16 version   */
-	32 + 16 * 7,		/* Max. number of devices on the bus */
+	32+16*7,	 /* There can be total 7 devices on the bus */
-	0x00,			/* Interrupt router bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x11 << 3) | 0x0,	/* Interrupt router dev */
+	(0x11<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0x1c00,			/* IRQs devoted exclusively to PCI usage */
+	0x1c00,		 /* IRQs devoted exclusively to PCI usage */
-	0x1106,			/* Vendor */
+	0x1106,		 /* Vendor */
-	0x596,			/* Device */
+	0x3227,		 /* Device */
-	0,			/* Miniport */
+	0,		 /* Miniport */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xf,			/* Checksum (has to be set to some value that
+	0xf,		 /* u8 checksum. This has to be set to some
-				 * would give 0 after the sum of all bytes
+			    value that would give 0 after the sum of all
-				 * for this structure (including checksum).
+			    bytes for this structure (including checksum) */
                                 */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00, (0x14 << 3) | 0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x1, 0x0},
+		{0x00,(0x14<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x1, 0x0},
-		{0x00, (0x13 << 3) | 0x0, {{0x05, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0},
+		{0x00,(0x13<<3)|0x0, {{0x05, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0},
-		{0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
-		{0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
-		{0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
-		{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
+		{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
 	}
 };
 #ifndef GETPIR
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
 	return copy_pirq_routing_table(addr);
 }
 #endif
--- a/src/mainboard/via/epia-n/mainboard.c
+++ b/src/mainboard/via/epia-n/mainboard.c
@@ -20,7 +20,24 @@
 */
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <boot/tables.h>
 #include "chip.h"
 #include "../../../southbridge/via/vt8237r/vt8237r.h"
 int add_mainboard_resources(struct lb_memory *mem)
 {
 #if CONFIG_IOAPIC == 1
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		VT8237R_APIC_BASE, 0x1000);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		0xFEE00000ULL, 0x1000);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		0xFFFF0000ULL, 0x10000);
 #endif
 	return 0;
 }
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("VIA EPIA-N Mainboard")
--- a/src/northbridge/via/cn400/Config.lb
+++ b/src/northbridge/via/cn400/Config.lb
@@ -19,6 +19,7 @@
 ##
 uses CONFIG_HAVE_HIGH_TABLES
 uses CONFIG_IOAPIC
 config chip.h
@@ -27,5 +28,6 @@ object vgabios.o
 driver northbridge.o
 driver agp.o
 driver vga.o
 driver vlink.o
 default CONFIG_HAVE_HIGH_TABLES=1
--- a/src/northbridge/via/cn400/agp.c
+++ b/src/northbridge/via/cn400/agp.c
@@ -32,21 +32,26 @@
 static void agp_init(device_t dev)
 {
 	u32 reg32;
 	u8 reg8;
 	int i, j;
 	/* Some of this may not be necessary (should be handled by the OS). */
 	printk_debug("Enabling AGP.\n");
 	/* Allow R/W access to AGP registers. */
-	pci_write_config8(dev, 0x4d, 0x15);
+	pci_write_config8(dev, 0x4d, 0x05);
 	/* Setup PCI latency timer. */
 	pci_write_config8(dev, 0xd, 0x8);
 	/* Write Secondary Vendor Ids */
 	pci_write_config32(dev, 0x2C, 0xAA071106);
 	/*
 	 * Set to AGP 3.0 Mode, which should theoretically render the rest of
 	 * the registers set here pointless.
 	 */
-	pci_write_config8(dev, 0x84, 0xb);
+	pci_write_config8(dev, 0x84, 0x1b);
 	/* AGP Request Queue Size */
 	pci_write_config8(dev, 0x4a, 0x1f);
@@ -67,41 +72,60 @@ static void agp_init(device_t dev)
 	/* Enable AGP Backdoor */
 	pci_write_config8(dev, 0xb5, 0x03);
-	/* Set aperture to 32 MB. */
+	/* Set aperture to 128 MB. */
 	/* TODO: Use config option, explain how it works. */
-	pci_write_config32(dev, 0x94, 0x00010f38);
+	pci_write_config32(dev, 0x94, 0x00010f20);
 	/* Set GART Table Base Address (31:12). */
-	pci_write_config32(dev, 0x98, (0x1558 << 12));
+	pci_write_config32(dev, 0x98, (0x37b20 << 12));
 	/* Set AGP Aperture Base. */
-	pci_write_config32(dev, 0x10, 0xf8000008);
+	pci_write_config32(dev, 0x10, 0xe8000008);
-	/* Enable CPU/PMSTR GART Access. */
+	/* NMI/AGPBUSY# Function Select */
 	pci_write_config8(dev, 0xbe, 0x80);
 	/* AGP Misc Control 1 */
 	pci_write_config8(dev, 0xc2, 0x40);
 	/* Enable CPU/PMSTR GART Access and DBI function. */
 	reg32 = pci_read_config8(dev, 0xbf);
-	reg32 |= 0x80;
+	reg32 |= 0x8c;
 	pci_write_config8(dev, 0xbf, reg32);
 	/* Enable AGP Aperture. */
-	reg32 = pci_read_config32(dev, 0x94);
+	pci_write_config32(dev, 0x90, 0x0180);
 	reg32 |= (3 << 7);
 	pci_write_config32(dev, 0x90, reg32);
 	/* AGP Control */
-	pci_write_config8(dev, 0xbc, 0x21);
+	pci_write_config8(dev, 0xbc, 0x25);
 	pci_write_config8(dev, 0xbd, 0xd2);
 	/*
 	 * AGP Pad, driving strength, and delay control. All this should be
 	 * constant, seeing as the VGA controller is onboard.
 	 */
-	pci_write_config8(dev, 0x40, 0xc7);
+	pci_write_config8(dev, 0x40, 0xda);
-	pci_write_config8(dev, 0x41, 0xdb);
+	pci_write_config8(dev, 0x41, 0xca);
-	pci_write_config8(dev, 0x42, 0x10);
+	pci_write_config8(dev, 0x42, 0x01);
-	pci_write_config8(dev, 0x43, 0xdb);
+	pci_write_config8(dev, 0x43, 0xca);
-	pci_write_config8(dev, 0x44, 0x24);
+	pci_write_config8(dev, 0x44, 0x04);
 	/* AGPC CKG Control */
-	pci_write_config8(dev, 0xc0, 0x02);
+	pci_write_config8(dev, 0xc0, 0x04);
 	pci_write_config8(dev, 0xc1, 0x02);
 #ifdef DEBUG_CN400
 	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
 	for (i = 0 ; i < 16; i++)
 	{
 		printk_spew("%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
 			printk_spew("%02X ", reg8);
 		}
 		printk_spew("\n");
 	}
 #endif
 }
 static const struct device_operations agp_operations = {
@@ -118,47 +142,89 @@ static const struct pci_driver agp_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_VIA_CN400_AGP,
 };
 static void agp_bridge_read_resources (device_t dev)
 {
 	struct resource *res;
 	res = new_resource(dev, 1);
 	res->base = 0xF0000000ULL;
 	res->size = 0x06000000ULL;
 	res->limit = 0xffffffffULL;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 		     		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 	res = new_resource(dev, 2);
 	res->base = 0xB000UL;
 	res->size = 4096;
 	res->limit = 0xffffUL;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
 		     		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 /*
 * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
 * config in this device takes presidence. We configure both just to be safe.
 */
 static void agp_bridge_init(device_t dev)
 {
-	printk_debug("Setting up AGP bridge device\n");
+	u8 reg8;
 	int i, j;
-	pci_write_config16(dev, 0x4, 0x0007);
+	printk_debug("Entering %s\n", __func__);
 	pci_write_config16(dev, 0x4, 0x0107);
 	/* Secondary Bus Number */
 	pci_write_config8(dev, 0x19, 0x01);
 	/* Subordinate Bus Number */
 	pci_write_config8(dev, 0x1a, 0x01);
 	/* I/O Base */
-	pci_write_config8(dev, 0x1c, 0xd0);
+	pci_write_config8(dev, 0x1c, 0xf0);
 	/* I/O Limit */
-	pci_write_config8(dev, 0x1d, 0xd0);
+	pci_write_config8(dev, 0x1d, 0x00);
 	/* Memory Base */
-	pci_write_config16(dev, 0x20, 0xfb00);
+	pci_write_config16(dev, 0x20, 0xf400);
 	/* Memory Limit */
 	pci_write_config16(dev, 0x22, 0xfcf0);
 	/* Prefetchable Memory Base */
 	pci_write_config16(dev, 0x24, 0xf400);
 	/* Prefetchable Memory Limit */
 	pci_write_config16(dev, 0x26, 0xf7f0);
 	/* Enable VGA Compatible Memory/IO Range */
 	pci_write_config8(dev, 0x3e, 0x08);
-	/* Second PCI Bus Control (see datasheet) */
+	/* Memory Limit */
 	pci_write_config16(dev, 0x22, 0xf5f0);
 	/* Prefetchable Memory Base */
 	pci_write_config16(dev, 0x24, 0xf000);
 	/* Prefetchable Memory Limit */
 	pci_write_config16(dev, 0x26, 0xf3f0);
 	/* Enable VGA Compatible Memory/IO Range */
 	pci_write_config8(dev, 0x3e, 0x0e);
 	/* AGP Bus Control */
 	pci_write_config8(dev, 0x40, 0x83);
-	pci_write_config8(dev, 0x41, 0x43);
+	pci_write_config8(dev, 0x41, 0xC7);
-	pci_write_config8(dev, 0x42, 0xe2);
+	pci_write_config8(dev, 0x42, 0x02);
 	pci_write_config8(dev, 0x43, 0x44);
 	pci_write_config8(dev, 0x44, 0x34);
 	pci_write_config8(dev, 0x45, 0x72);
 	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
 	for (i = 0 ; i < 16; i++)
 	{
 		printk_spew("%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
 			printk_spew("%02X ", reg8);
 		}
 		printk_spew("\n");
 	}
 }
 static const struct device_operations agp_bridge_operations = {
-	.read_resources   = cn400_noop,
+	.read_resources   = agp_bridge_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
 	.init             = agp_bridge_init,
--- a/src/northbridge/via/cn400/cn400.h
+++ b/src/northbridge/via/cn400/cn400.h
@@ -24,6 +24,8 @@ static void cn400_noop()
 }
 #endif
 #define DEBUG_CN400
 /* VGA stuff */
 #define SR_INDEX		0x3c4
 #define SR_DATA			0x3c5
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -38,16 +38,28 @@ static void memctrl_init(device_t dev)
 {
 	device_t vlink_dev;
 	u16 reg16;
-	u8 ranks, pagec, paged, pagee, pagef, shadowreg;
+	u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8;
 	int i, j;
 	printk_spew("Entering cn400 memctrl_init.\n");
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
-	/* Set up the VGA framebuffer size. */
+	/* Setup Low Memory Top 						*/
-	reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
+	/* 0x47 == HA(32:25)						    */
 	/* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
 	ranks = pci_read_config8(dev, 0x47);
 	reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
 	pci_write_config16(dev, 0x84, reg16);
 	printk_spew("Low Top Address = 0x%04X\n", reg16);
 	/* Set up the VGA framebuffer size and Base Address   */
 	/* Note dependencies between agp.c and vga.c and here */
 	reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15) | 0xF00;
 	pci_write_config16(dev, 0xa0, reg16);
 	/* Set up VGA timers. */
 	pci_write_config8(dev, 0xa2, 0x44);
 	for (ranks = 0x4b; ranks >= 0x48; ranks--) {
 		if (pci_read_config8(dev, ranks)) {
@@ -64,6 +76,15 @@ static void memctrl_init(device_t dev)
 	/* AGPCINT Misc. */
 	pci_write_config8(dev, 0xb8, 0x08);
 	/* Arbritation Counters */
 	pci_write_config8(dev, 0xb2, 0xaa);
 	/* Write FIFO Setup */
 	pci_write_config8(dev, 0xb3, 0x5a);
 	/* Graphics control optimisation */
 	pci_write_config8(dev, 0xb4, 0x0f);
 	/* Shadow RAM */
 	pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
 	/* PAGE C, D, E are all read write enable */
@@ -74,10 +95,6 @@ static void memctrl_init(device_t dev)
 	shadowreg = pci_read_config8(dev, 0x82);
 	shadowreg |= pagef;
 	pci_write_config8(dev, 0x82, shadowreg);
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
 	if (vlink_dev) {
 		pci_write_config8(vlink_dev, 0x61, pagec);
 		pci_write_config8(vlink_dev, 0x62, paged);
 		pci_write_config8(vlink_dev, 0x64, pagee);
@@ -85,14 +102,36 @@ static void memctrl_init(device_t dev)
 		shadowreg = pci_read_config8(vlink_dev, 0x63);
 		shadowreg |= pagef;
 		pci_write_config8(vlink_dev, 0x63, shadowreg);
-	}
+
 	/* Activate VGA Frame Buffer */
-	printk_spew("Leaving cn400 memctrl_init.\n");
+	reg8 = pci_read_config8(dev, 0xA0);
 	reg8 |= 0x01;
 	pci_write_config8(dev, 0xA0, reg8);
 #ifdef DEBUG_CN400
 	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
 	for (i = 0 ; i < 16; i++)
 	{
 		printk_spew("%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
 			printk_spew("%02X ", reg8);
 		}
 		printk_spew("\n");
 	}
 #endif
 	printk_spew("Leaving cn400 %s.\n", __func__);
 }
 static const struct device_operations memctrl_operations = {
 	.read_resources = cn400_noop,
 	.set_resources    = cn400_noop,
 	.enable_resources = cn400_noop,
 	.init           = memctrl_init,
 	.ops_pci          = 0,
 };
 static const struct pci_driver memctrl_driver __pci_driver = {
@@ -129,14 +168,27 @@ static void ram_resource(device_t dev, unsigned long index,
 	if (!sizek)
 		return;
 	resource = new_resource(dev, index);
-	resource->base = ((resource_t) basek) << 10;
+	resource->base = (resource_t) (basek << 10);
-	resource->size = ((resource_t) sizek) << 10;
+	resource->size = (resource_t) (sizek << 10);
 	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 static void ram_reservation(device_t dev, unsigned long index,
 			 unsigned long base, unsigned long size)
 {
 	struct resource *res;
 	printk_spew("Configuring Via C3 LAPIC Fixed Resource\n");
 	/* Fixed LAPIC resource */
 	res = new_resource(dev, 1);
 	res->base = (resource_t) base;
 	res->size = size;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;
@@ -150,24 +202,23 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
 static u32 find_pci_tolm(struct bus *bus)
 {
-	struct resource *min;
+	struct resource *min = NULL;
 	u32 tolm;
-	print_debug("Entering CN400 find_pci_tolm\n");
+	printk_spew("Entering CN400 find_pci_tolm\n");
 	min = 0;
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
 			     tolm_test, &min);
 	tolm = 0xffffffffUL;
 	if (min && tolm > min->base)
 		tolm = min->base;
-	print_debug("Leaving find_pci_tolm\n");
+	printk_spew("Leaving CN400 find_pci_tolm\n");
 	return tolm;
 }
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
 /* maximum size of high tables in KB */
 #define HIGH_TABLES_SIZE 64
 extern uint64_t high_tables_base, high_tables_size;
@@ -175,8 +226,6 @@ extern uint64_t high_tables_base, high_tables_size;
 static void cn400_domain_set_resources(device_t dev)
 {
 	/* The order is important to find the correct RAM size. */
 	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 	device_t mc_dev;
 	u32 pci_tolm;
@@ -191,29 +240,21 @@ static void cn400_domain_set_resources(device_t dev)
 		unsigned char rambits;
 		int i, idx;
-		/*
+		rambits = pci_read_config8(mc_dev, 0x47);
-		 * Once the register value is not zero, the RAM size is
+		tomk = rambits * 32 * 1024;
 		 * this register's value multiply 64 * 1024 * 1024.
 		 */
 		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			rambits = pci_read_config8(mc_dev, ramregs[i]);
 			if (rambits != 0)
 				break;
 		}
 		tomk = rambits * 64 * 1024;
 		printk_spew("tomk is 0x%x\n", tomk);
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
 		printk_spew("tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
 		if (tolmk >= tomk) {
 			/* The PCI hole does does not overlap the memory. */
 			tolmk = tomk;
 		}
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
-		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+		/* Locate the High Tables at the Top of Low Memory below the Video RAM */
-		high_tables_size = HIGH_TABLES_SIZE* 1024;
+		high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024;
 		printk_spew("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 		/* Report the memory regions. */
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -1,5 +1,6 @@
 /*
 * (C) Copyright 2005 Nick Barker <nick.barker9@btinternet.com>
 * (C) Copyright 2009 Jon Harrison <bothlyn@blueyonder.co.uk
 *
 *
 * This program is free software; you can redistribute it and/or
@@ -19,16 +20,13 @@
 */
 /* 
-  Automatically detect and set up ddr dram on the CLE266 chipset.
+  Automatically detect and set up ddr dram on the CN400 chipset.
-  Assumes DDR memory, though chipset also supports SDRAM
+  Assumes DDR400 memory as no attempt is made to clock
  Assumes at least 266Mhz memory as no attempt is made to clock
  the chipset down if slower memory is installed.
  So far tested on:
-	256 Mb 266Mhz 1 Bank (i.e. single sided)
+	512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
 	256 Mb 266Mhz 2 Bank (i.e. double sided)
 	512 Mb 266Mhz 2 Bank (i.e. double sided)
 */
-/* ported and enhanced from assembler level code in coreboot v1 */
+/* ported from Via VT8263 Code*/
 #include <spd.h>
 #include <sdram_mode.h>
@@ -68,6 +66,7 @@ static void c3_cpu_setup(device_t dev)
 {
 	/* Host bus interface registers (D0F2 0x50-0x67) */
 	/* Taken from CN700 and updated from running CN400 */
 	uint8_t reg8;
 	/* Host Bus I/O Circuit (see datasheet) */
 	/* Host Address Pullup/down Driving */
@@ -87,6 +86,7 @@ static void c3_cpu_setup(device_t dev)
 	/* AGTL+ Auto Compensation Offest */
 	pci_write_config8(dev, 0x77, 0x00);
 	pci_write_config8(dev, 0x78, 0x94);
 	/* Request phase control */
 	pci_write_config8(dev, 0x50, 0xA8);
@@ -135,7 +135,13 @@ static void c3_cpu_setup(device_t dev)
 	/* CPU Miscellaneous Control */
 	pci_write_config8(dev, 0x55, 0x28);
 	pci_write_config8(dev, 0x57, 0x69);
 	/* CPU Host Bus Final Setup */
 	reg8 = pci_read_config8(dev, 0x54);
 	reg8 |= 0x08;
 	pci_write_config8(dev, 0x54, reg8);
 }
 static void ddr_ram_setup(void) 
@@ -177,7 +183,7 @@ static void ddr_ram_setup(void)
 		/*
    		Read SPD byte 3, Number of row addresses.
 		*/
-		c = 0;
+		c = 0x01;
 		bank = 0x40;
 		b = smbus_read_byte(0x50, SPD_NUM_ROWS);
 		//print_val("\r\nNumber of Rows ", b);
@@ -195,7 +201,7 @@ static void ddr_ram_setup(void)
 			b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
 			//print_val("\r\nPrimary DRAM width", b);
 			if( b != 4 )   // not 64/128Mb (x4)
-				c = 0x80;  // 256Mb
+				c = 0x81;  // 256Mb
 		}
 		/*
@@ -211,6 +217,10 @@ static void ddr_ram_setup(void)
 		pci_write_config8(ctrl.d0f3, 0x50, c);
 	}
 	/* Disable Upper Banks */
 	pci_write_config8(ctrl.d0f3, 0x51, 0x00);
 /*	else
 	{
 		die("DRAM module size is not supported by CN400\r\n");
@@ -265,8 +275,6 @@ static void ddr_ram_setup(void)
 	else if( b & 0x08) c = 0x01;    	// 32MB
 	else c = 0x01;                  	// Error, use default
 	//print_val("\r\nBank 0 (*32 Mb) ",c);
 	// set bank zero size
 	pci_write_config8(ctrl.d0f3, 0x40, c);
@@ -278,7 +286,6 @@ static void ddr_ram_setup(void)
 	{
 		c <<=1;
 		bank |= 0x80;
 		//print_val("\r\nTotal Memory (*32 Mb) ",c);
 	}
 /*	else
 	{
@@ -294,6 +301,10 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0x46,c);
 	pci_write_config8(ctrl.d0f3, 0x47,c);
 	/* Top Rank Address Mirrored to the South Bridge */
 	/* over the VLink								 */
 	pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
 	ma = bank;
 	/* Read SPD byte 18 CAS Latency */
@@ -313,13 +324,11 @@ static void ddr_ram_setup(void)
 	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
 	print_val("\r\nCycle time at CL X-1   (nS)", c);
 */	
 	/* Scaling of Cycle Time SPD data */
 	/* 7      4 3       0             */
 	/*    ns     x0.1ns               */
 	bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 	/* Setup DRAM Cycle Time */
 	if ( bank <= 0x50 ) bank = 0x14;
 	else if (bank <= 0x60) bank = 0x18;
 	else bank = 0x1E;
 	if( b & 0x10 ){             // DDR offering optional CAS 3
 		//print_debug("\r\nStarting at CAS 3");
 		c = 0x30;
@@ -347,6 +356,13 @@ static void ddr_ram_setup(void)
 		}
 	}	
 	/* Scale DRAM Cycle Time to tRP/tRCD */
 	/* 7      2 1       0             */
 	/*    ns     x0.25ns               */
 	if ( bank <= 0x50 ) bank = 0x14;
 	else if (bank <= 0x60) bank = 0x18;
 	else bank = 0x1E;
 /*
    DRAM Timing  Device 0  Fn 3 Offset 56
@@ -401,8 +417,12 @@ static void ddr_ram_setup(void)
    Read SPD byte 30, device min active to pre-charge time.
 */
 	/* tRAS is in whole ns */
 	bank = bank >> 2;
 	b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 	//print_val("\r\ntRAS ",b);
 	//print_val("\r\nBank ", bank);
 	if ( b >= (9 * bank)) c |= 0xC0;		// set tRAS = 9T
 	else if ( b >= (8 * bank)) c |= 0x80;	// set tRAS = 8T
 	else if ( b >= (7 * bank)) c |= 0x40;	// set tRAS = 7T
@@ -457,15 +477,20 @@ static void ddr_ram_setup(void)
 	/* 4-Way Interleave With Multi-Paging (From Running System)*/
 	pci_write_config8(ctrl.d0f3, 0x69, c);
 	/*DRAM Controller Internal Options */
 	pci_write_config8(ctrl.d0f3, 0x54, 0x01);
 	/* DRAM Arbitration Control */
 	pci_write_config8(ctrl.d0f3, 0x66, 0x82);
 	/* DRAM Control */
-	pci_write_config8(ctrl.d0f3, 0x6e, 0x00);
+	pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
 	/* Disable refresh for now */
 	pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
 	/* DDR Clock Gen Duty Cycle Control */
 	pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
 	/* DRAM Clock Control */
@@ -484,8 +509,9 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
 	/* DRAM signal timing control */
-	pci_write_config8(ctrl.d0f3, 0x74, 0x99);	
+	pci_write_config8(ctrl.d0f3, 0x74, 0x99);
 	pci_write_config8(ctrl.d0f3, 0x76, 0x09);
 	pci_write_config8(ctrl.d0f3, 0x77, 0x12);
 	pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
 	pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
@@ -500,6 +526,9 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0xb0, c);
 	/* Set RAM Decode method */
 	pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
 	/* Enable DIMM Ranks */
 	pci_write_config8(ctrl.d0f3, 0x48, ma);
 	udelay(200);
@@ -528,7 +557,7 @@ static void ddr_ram_setup(void)
 		i = 0x008; 		// Used later to set SDRAM MSR
 	}
-		
+
 	for( bank = 0 , bank_address=0; bank <= b ; bank++) {
 /*
    DDR init described in Via VT8623 BIOS Porting Guide.  Pg 28 (4.2.3.1)
@@ -641,6 +670,9 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
 	pci_write_config8(ctrl.d0f3, 0x7B, 0x62);	
 	/* DQS Duty Cycle Control */
 	pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 	/* SPD byte 5  # of physical banks */
 	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
@@ -650,7 +682,7 @@ static void ddr_ram_setup(void)
 	else
 		bank_address = 0;
-	for(i = 0x40 ; i < 0x0ff; i++){
+	for(i = 0x30 ; i < 0x0ff; i++){
 		pci_write_config8(ctrl.d0f3,0x70,i);
 		// clear
 		*(volatile unsigned long*)(0x4000) = 0;
@@ -741,13 +773,15 @@ static void ddr_ram_setup(void)
 		pci_write_config8(ctrl.d0f3,0x70,0x67);
 	}
-	/* Set DQS ChB Output to the default */
+	/* Set DQS ChA Data Output Delay to the default */
-	pci_write_config8(ctrl.d0f3, 0x71, 0x6c);
+	pci_write_config8(ctrl.d0f3, 0x71, 0x65);
-	/* Set DQS Input Delays */
+	/* Set Ch B DQS Output Delays */
-	pci_write_config8(ctrl.d0f3, 0x72, 0x29);
+	pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
-	pci_write_config8(ctrl.d0f3, 0x73, 0x99);	
+	pci_write_config8(ctrl.d0f3, 0x73, 0x29);
 	pci_write_config8(ctrl.d0f3, 0x78, 0x03);
 	/* Mystery Value */
 	pci_write_config8(ctrl.d0f3, 0x67, 0x50);
@@ -765,14 +799,14 @@ static void ddr_ram_setup(void)
 	//b = smbus_read_byte(0x50, SPD_REFRESH);
 	//print_val("SPD_REFRESH = ", b);
-	pci_write_config8(ctrl.d0f3,0x6a,0x6C);
+	pci_write_config8(ctrl.d0f3,0x6a,0x65);
 	/* SMM and APIC decoding, we do not use SMM */
 	b = 0x29;
 	pci_write_config8(ctrl.d0f3, 0x86, b);
 	/* SMM and APIC decoding mirror */
 	pci_write_config8(ctrl.d0f7, 0xe6, b);
 	/* Enable TLB Auto refresh */
 	b = pci_read_config8(ctrl.d0f3, 0x69);
 	b |= 0x10;
 	pci_write_config8(ctrl.d0f3, 0x69, b);
 	/* Open Up the Rest of the Shadow RAM */
 	pci_write_config8(ctrl.d0f3,0x80,0xff);
 	pci_write_config8(ctrl.d0f3,0x81,0xff);
@@ -784,26 +818,9 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f7,0x71,0xc8);
    print_debug("CN400 Init done\r\n");
 	/* VGA device. */
 	pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 	pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
-	
+    print_debug("CN400 raminit.c done\r\n");
 	/* Graphics Control Basic Init. */
 	//pci_write_config8(ctrl.d0f3, 0xb0, 0xFf);
 	//pci_write_config8(ctrl.d0f3, 0xb1, 0xAA);
 	//pci_write_config8(ctrl.d0f3, 0xb2, 0xAA);
 	//pci_write_config8(ctrl.d0f3, 0xb3, 0x5A);
 	//pci_write_config8(ctrl.d0f3, 0xb4, 0x0f);
 	/* AGP Controller Interface Basic Init */
 	//pci_write_config8(ctrl.d0f3, 0xc0, 0x3b);
 	/* VGA device, Basic frame Buffer Init. */
 	//pci_write_config8(ctrl.d0f3, 0xa0, 0x01);
 	/* Bit 7 = Enable VGA When Set to 1 */
 	//pci_write_config8(ctrl.d0f3, 0xa1, 0xef);
 	//pci_write_config8(ctrl.d0f3, 0xa4, 0x00);
 }	
--- a/src/northbridge/via/cn400/vga.c
+++ b/src/northbridge/via/cn400/vga.c
@@ -47,6 +47,9 @@ static void vga_init(device_t dev)
 {
 	u8 reg8;
 	u32 temp;
 #ifdef DEBUG_CN400
 	int i, j;
 #endif
 	temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
 	printk_debug("Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
@@ -73,8 +76,8 @@ static void vga_init(device_t dev)
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x0d, 0x20);
-	pci_write_config32(dev, 0x10, 0xf4000008);
+	pci_write_config32(dev, 0x10, 0xf0000008);
-	pci_write_config32(dev, 0x14, 0xfb000000);
+	pci_write_config32(dev, 0x14, 0xf4000000);
 	printk_debug("INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
@@ -101,6 +104,21 @@ static void vga_init(device_t dev)
 	/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
 	memset(0xf0000, 0, 0x10000);
 #ifdef DEBUG_CN400
 	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
 	for (i = 0 ; i < 16; i++)
 	{
 		printk_spew("%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
 			printk_spew("%02X ", reg8);
 		}
 		printk_spew("\n");
 	}
 #endif
 }
 static void vga_read_resources(device_t dev)
--- a/src/southbridge/via/vt8237r/Config.lb
+++ b/src/southbridge/via/vt8237r/Config.lb
@@ -26,6 +26,8 @@ driver vt8237_ctrl.o
 driver vt8237r_ide.o
 driver vt8237r_lpc.o
 driver vt8237r_sata.o
 driver vt8237r_usb.o
 driver vt8237r_nic.o
 if CONFIG_HAVE_ACPI_TABLES
 	object vt8237_fadt.o
 end
--- a/src/southbridge/via/vt8237r/vt8237r_ide.c
+++ b/src/southbridge/via/vt8237r/vt8237r_ide.c
@@ -35,8 +35,10 @@ static void ide_init(struct device *dev)
 	struct southbridge_via_vt8237r_config *sb =
 	    (struct southbridge_via_vt8237r_config *)dev->chip_info;
-	u8 enables;
+	u8 enables, reg8;
 	u32 cablesel;
 	device_t lpc_dev;
 	int i, j;
 	printk_info("%s IDE interface %s\n", "Primary",
 		    sb->ide0_enable ? "enabled" : "disabled");
@@ -49,6 +51,10 @@ static void ide_init(struct device *dev)
 	printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
 	/* Enable only compatibility mode. */
 	enables = pci_read_config8(dev, 0x09);
 	enables &= 0xFA;
 	pci_write_config8(dev, 0x09, enables);
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	enables &= ~0xc0;
 	pci_write_config8(dev, IDE_CONF_II, enables);
@@ -74,6 +80,7 @@ static void ide_init(struct device *dev)
 	/* Use memory read multiple, Memory-Write-and-Invalidate. */
 	enables = pci_read_config8(dev, IDE_MISC_II);
 	enables &= 0xEF;
 	enables |= (1 << 2) | (1 << 3);
 	pci_write_config8(dev, IDE_MISC_II, enables);
@@ -89,6 +96,14 @@ static void ide_init(struct device *dev)
 		    (sb->ide1_80pin_cable << 12) |
 		    (sb->ide1_80pin_cable << 4);
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	/* Set PATA Output Drive Strength */
 	lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 	if (lpc_dev)
 		pci_write_config8(lpc_dev, 0x7C, 0x20);
 #endif
 }
 static const struct device_operations ide_ops = {
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -2,6 +2,7 @@
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
 * Copyright (C) 2009       Jon Harrison <bothlyn@blueyonder.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License v2 as published by
@@ -48,6 +49,31 @@
 #define INT		(1 << 8)
 extern void dump_south(device_t dev);
 static void southbridge_init_common(struct device *dev);
 #ifdef CONFIG_EPIA_VT8237R_INIT
                   /* Interrupts for  INT# A   B   C   D */
 static const unsigned char pciIrqs[4]  = { 10, 11, 12, 0};
            /* Interrupt Assignments for Pins   1   2   3   4  */
 static const unsigned char sataPins[4] =     { 'A','B','C','D'};
 static const unsigned char vgaPins[4] =      { 'A','B','C','D'};
 static const unsigned char usbPins[4] =      { 'A','B','C','D'};
 static const unsigned char enetPins[4] =     { 'A','B','C','D'};
 static const unsigned char vt8237Pins[4] =   { 'A','B','C','D'};
 static const unsigned char slotPins[4] =     { 'C','D','A','B'};
 static const unsigned char riserPins[4] =    { 'D','C','B','A'};
 static unsigned char *pin_to_irq(const unsigned char *pin)
 {
 	static unsigned char Irqs[4];
 	int i;
 	for (i = 0 ; i < 4 ; i++)
 		Irqs[i] = pciIrqs[ pin[i] - 'A' ];
 	return Irqs;
 }
 #endif
 static struct ioapicreg {
 	u32 reg;
@@ -93,10 +119,16 @@ static void setup_ioapic(u32 ioapic_base)
 	ioapic_table[0].value_high = (lapicid()) << (56 - 32);
 	l = (u32 *)ioapic_base;
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	/* Set APIC to APIC Serial bus. */
 	l[0] = 0x3;
 	l[4] = 0;
 #else
 	/* Set APIC to FSB message bus. */
 	l[0] = 0x3;
 	val = l[4];
 	l[4] = (val & 0xFFFFFE) | 1;
 #endif
 	/* Set APIC ADDR - this will be VT8237R_APIC_ID. */
 	l[0] = 0;
@@ -109,26 +141,82 @@ static void setup_ioapic(u32 ioapic_base)
 		value_low = l[4];
 		l[0] = (ioapic_table[i].reg * 2) + 0x11;
 		l[4] = ioapic_table[i].value_high;
-		value_high = l[4];
+		if (i == 0) {
-
+			l[0] = (ioapic_table[i].reg * 2) + 0x10;
-		if ((i == 0) && (value_low == 0xffffffff)) {
+			value_low = l[4];
-			printk_warning("IO APIC not responding.\n");
+			if (value_low == 0xffffffff)
-			return;
+			{
 				printk_warning("IO APIC not responding.\n");
 				return;
 			}
 		}
 	}
 }
 static void southbridge_init_common(struct device *dev);
 /** Set up PCI IRQ routing, route everything through APIC. */
 static void pci_routing_fixup(struct device *dev)
 {
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	device_t pdev;
 	u8 reg;
 #endif
 	/* PCI PNP Interrupt Routing INTE/F - disable */
 	pci_write_config8(dev, 0x44, 0x00);
 	/* PCI PNP Interrupt Routing INTG/H - disable */
 	pci_write_config8(dev, 0x45, 0x00);
 	/* Gate Interrupts until RAM Writes are flushed */
 	pci_write_config8(dev, 0x49, 0x20);
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
 	pci_write_config8(dev, 0x46, 0x00);
 	/* setup PCI IRQ routing (For PCI Slot)*/
 	pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
 	pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
 	pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
 	/* PCI Routing Fixup */
 	//Setup MiniPCI Slot
 	pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
 	// Via 2 slot riser card 2nd slot
 	pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
 	//Setup USB
 	pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 	//Setup VT8237R Sound
 	pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins));
 	//Setup Ethernet
 	pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
 	//Setup VGA
 	pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
 	/* APIC Routing Fixup */
 	// Setup SATA
 	pdev = dev_find_device(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_VT6420_SATA, 0);
 	pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02);
 	pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins));
 	// Setup PATA Override
 	pdev = dev_find_device(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_82C586_1, 0);
 	pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01);
 	pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF);
 #else
 	/* Route INTE-INTH through registers above, no map to INTA-INTD. */
 	pci_write_config8(dev, 0x46, 0x10);
@@ -143,8 +231,11 @@ static void pci_routing_fixup(struct device *dev)
 	/* PCI INTD# Routing */
 	pci_write_config8(dev, 0x57, 0x00);
 #endif
 }
 /**
 * Set up the power management capabilities directly into ACPI mode.
 * This avoids having to handle any System Management Interrupts (SMIs).
@@ -165,9 +256,14 @@ static void setup_pm(device_t dev)
 	/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
 	pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 	pci_write_config16(dev, 0x84, 0x3052);
 #else
 	/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 	pci_write_config16(dev, 0x84, 0x30b2);
 #endif
 	/* SMI output level to low, 7.5us throttle clock */
 	pci_write_config8(dev, 0x8d, 0x18);
@@ -184,11 +280,19 @@ static void setup_pm(device_t dev)
 	/*
 	 * 7 = stp to sust delay 1msec
 	 * 6 = SUSST# Deasserted Before PWRGD for STD
 	 * 5 = Keyboard/Mouse Swap
 	 * 4 = PWRGOOD reset on VT8237A/S
 	 * 3 = GPO26/GPO27 is GPO 
 	 * 2 = Disable Alert on Lan
 	 * 1 = SUSCLK/GPO4
 	 * 0 = USB Wakeup
 	 */
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	pci_write_config8(dev, 0x95, 0xc2);
 #else
 	pci_write_config8(dev, 0x95, 0xcc);
 #endif
 	/* Disable GP3 timer. */
 	pci_write_config8(dev, 0x98, 0);
@@ -233,20 +337,14 @@ static void setup_pm(device_t dev)
 	tmp &= ~(7 << 10);
 	tmp |= 1;
 	outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
 }
 static void vt8237r_init(struct device *dev)
 {
-	u8 enables;
+	u8 enables, reg8;
 	printk_spew("Entering vt8237r_init.\n");
 #ifdef CONFIG_EPIA_VT8237R_INIT
-	printk_spew("vt8237r_init SATA LED.\n");
+	printk_spew("Entering vt8237r_init, for EPIA.\n");
 	/*
 	 * TODO: Looks like stock BIOS can do this but causes a hang
 	 * Enable SATA LED, disable special CPU Frequency Change -
@@ -255,10 +353,9 @@ static void vt8237r_init(struct device *dev)
 	 * PCS0# on Pin U1
 	 */
 	enables = pci_read_config8(dev, 0xe5);
-	enables |= 0x02;
+	enables |= 0x23;
 	pci_write_config8(dev, 0xe5, enables);
 	printk_spew("vt8237r_init PCI Req.\n");
 	/* 
 	 * Enable Flash Write Access. 
 	 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
@@ -267,7 +364,13 @@ static void vt8237r_init(struct device *dev)
 	enables |= 0x2B;
 	pci_write_config8(dev, 0xe4, enables);
 	/* Enables Extra RTC Ports */
 	enables = pci_read_config8(dev, 0x4E);
 	enables |= 0x80;
 	pci_write_config8(dev, 0x4E, enables);
 #else 
 	printk_spew("Entering vt8237r_init.\n");
 	/*
 	 * Enable SATA LED, disable special CPU Frequency Change -
 	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
@@ -278,23 +381,27 @@ static void vt8237r_init(struct device *dev)
 	pci_write_config8(dev, 0xe4, 0x4);
 #endif
 	printk_spew("vt8237r_init CPU Rst.\n");
 	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
 	enables = pci_read_config8(dev, 0x4f);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
-	printk_spew("vt8237r_init Read Pass Write Ctrl.\n");
+#ifdef CONFIG_EPIA_VT8237R_INIT
 	/*
 	 * Set Read Pass Write Control Enable
 	 */
 	pci_write_config8(dev, 0x48, 0x0c);
 #else
 	/*
 	 * Set Read Pass Write Control Enable
 	 * (force A2 from APIC FSB to low).
 	 */
 	pci_write_config8(dev, 0x48, 0x8c);
 #endif
 	printk_spew("vt8237r_init calling southbridge_init_common.\n");
 	southbridge_init_common(dev);
 #ifndef CONFIG_EPIA_VT8237R_INIT
 	/* FIXME: Intel needs more bit set for C2/C3. */
 	/*
@@ -302,8 +409,9 @@ static void vt8237r_init(struct device *dev)
 	 * Will work for C3 and for FID/VID change.
 	 */
 	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
-	
+#endif
-	printk_spew("Leaving vt8237r_init.\n");
+
 	printk_spew("Leaving %s.\n", __func__);
 }
 static void vt8237s_init(struct device *dev)
@@ -351,6 +459,8 @@ static void vt8237_common_init(struct device *dev)
 	byte |= PCI_COMMAND_WAIT;
 	pci_write_config8(dev, PCI_COMMAND, byte);
 /* EPIA-N(L) Uses CN400 for BIOS Access */
 #ifndef CONFIG_EPIA_VT8237R_INIT
 	/* Enable the internal I/O decode. */
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
@@ -370,6 +480,7 @@ static void vt8237_common_init(struct device *dev)
 	 * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
 	 */
 	pci_write_config8(dev, 0x41, 0x7f);
 #endif
 	/*
 	 * Set bit 6 of 0x40 (I/O recovery time).
@@ -388,6 +499,29 @@ static void vt8237_common_init(struct device *dev)
 	/* Delay transaction control */
 	pci_write_config8(dev, 0x43, 0xb);
 #ifdef CONFIG_EPIA_VT8237R_INIT
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x04);
 	/* ROM memory cycles go to LPC. */
 	pci_write_config8(dev, 0x59, 0x80);
 	/*
 	 * Bit | Meaning
 	 * -------------
 	 *   3 | Bypass APIC De-Assert Message (1=Enable)
 	 *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
 	 *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 	 *   0 | Dynamic Clock Gating Main Switch (1=Enable)
 	 */
 	pci_write_config8(dev, 0x5b, 0x9);
 	/* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/
 	pci_write_config8(dev, 0x58, 0x42);
 	/* Enable serial IRQ, 6PCI clocks. */
 	pci_write_config8(dev, 0x52, 0x9);
 #else
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x44);
@@ -410,6 +544,8 @@ static void vt8237_common_init(struct device *dev)
 	/* Enable serial IRQ, 6PCI clocks. */
 	pci_write_config8(dev, 0x52, 0x9);
 #endif
 	/* Power management setup */
 	setup_pm(dev);
@@ -422,11 +558,38 @@ static void vt8237r_read_resources(device_t dev)
 	struct resource *res;
 	pci_dev_read_resources(dev);
 	/* Fixed ACPI Base IO Base*/
 	res = new_resource(dev, 0x88);
 	res->base = VT8237R_ACPI_IO_BASE;
 	res->size = 128;
 	res->limit = 0xffffUL;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 	/* Fixed EISA ECLR I/O Regs	*/
 	res = new_resource(dev, 3);
 	res->base = 0x4d0;
 	res->size = 2;
 	res->limit = 0xffffUL;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 	/* Fixed System Management Bus I/O Resource */
 	res = new_resource(dev, 0xD0);
 	res->base = VT8237R_SMBUS_IO_BASE;
 	res->size = 16;
 	res->limit = 0xffffUL;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 	/* Fixed APIC resource */
 	res = new_resource(dev, 0x44);
 	res->base = VT8237R_APIC_BASE;
 	res->size = 256;
 	res->limit = 0xffffffffUL;
 	res->align = 8;
 	res->gran = 8;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;