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Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"

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This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881.

This was originally assumed to be an FSP/Descriptor/PMC mismatch
but it turns out that the problem was coreboot incorrectly
detecting ASPM support on devices.

Revert so that a proper fix can be applied.

Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2024-03-21 14:36:58 +00:00 committed by Felix Held
parent 5827ffcdaf
commit 185652e273
4 changed files with 8 additions and 10 deletions
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8
src/mainboard/starlabs/starbook/variants/adl/gpio.c
View File

@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
// PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D7: Clock Request 2 Wireless LAN */
// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
// PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */

1
src/mainboard/starlabs/starbook/variants/adl/romstage.c
View File

@ -35,5 +35,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
};

8
src/mainboard/starlabs/starbook/variants/rpl/gpio.c
View File

@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
// PAD_NC(GPP_D6, NONE),
PAD_NC(GPP_D6, NONE),
/* D7: Clock Request 2 Wireless LAN */
// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
// PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */

1
src/mainboard/starlabs/starbook/variants/rpl/romstage.c
View File

@ -44,5 +44,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
}
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
};