mb/google/nissa: Create teliks variant

Create the teliks variant of the nissa reference board by copying
the anraggar files to a new directory named for the variant.

BUG=b:352263941
BRANCH=None
TEST=1. util/abuild/abuild -p none -t google/brya -x -a
        make sure the build includes GOOGLE_TELIKS
     2. Run part_id_gen tool without any errors

Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/mainboard/google/brya/Kconfig

@@ -529,6 +529,17 @@ config BOARD_GOOGLE_TANIKS
 	select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX
 	select INTEL_GMA_HAVE_VBT
 
+config BOARD_GOOGLE_TELIKS
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select BOARD_ROMSIZE_KB_16384
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select HAVE_WWAN_POWER_SEQUENCE
+	select SOC_INTEL_TWINLAKE
+
 config BOARD_GOOGLE_TEREID
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_32768
@@ -706,6 +717,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_TAEKO
 	default 0x3 if BOARD_GOOGLE_TAEKO4ES
 	default 0x1 if BOARD_GOOGLE_TANIKS
+	default 0x0 if BOARD_GOOGLE_TELIKS
 	default 0x0 if BOARD_GOOGLE_TEREID
 	default 0x0 if BOARD_GOOGLE_TIVVIKS
 	default 0x0 if BOARD_GOOGLE_TRULO
@@ -857,6 +869,7 @@ config MAINBOARD_PART_NUMBER
 	default "Taeko" if BOARD_GOOGLE_TAEKO
 	default "Taeko4ES" if BOARD_GOOGLE_TAEKO4ES
 	default "Taniks" if BOARD_GOOGLE_TANIKS
+	default "Teliks" if BOARD_GOOGLE_TELIKS
 	default "Tereid" if BOARD_GOOGLE_TEREID
 	default "Tivviks" if BOARD_GOOGLE_TIVVIKS
 	default "Trulo" if BOARD_GOOGLE_TRULO
@@ -925,6 +938,7 @@ config VARIANT_DIR
 	default "taeko" if BOARD_GOOGLE_TAEKO
 	default "taeko4es" if BOARD_GOOGLE_TAEKO4ES
 	default "taniks" if BOARD_GOOGLE_TANIKS
+	default "teliks" if BOARD_GOOGLE_TELIKS
 	default "trulo" if BOARD_GOOGLE_TRULO
 	default "uldren" if BOARD_GOOGLE_ULDREN
 	default "vell" if BOARD_GOOGLE_VELL

src/mainboard/google/brya/Kconfig.name

@@ -143,6 +143,9 @@ config BOARD_GOOGLE_TAEKO4ES
 config BOARD_GOOGLE_TANIKS
 	bool "->  Taniks"
 
+config BOARD_GOOGLE_TELIKS
+	bool "->  Teliks"
+
 config BOARD_GOOGLE_TEREID
 	bool "->  Tereid"
 

src/mainboard/google/brya/variants/teliks/Makefile.mk

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+
+ramstage-y += variant.c

src/mainboard/google/brya/variants/teliks/gpio.c

@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A7  : NC ==> LTE_Present */
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+	/* A8  : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A11 : GPP_A11 ==> EN_SPK_PA */
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	/* A18 : NC ==> HDMI_HPD_SRC*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
+	/* A21 : GPP_A21 ==> NC */
+	PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
+	/* A22 : GPP_A22 ==> NC */
+	PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
+
+	/* B5  : I2C2_SDA ==> MIPI_WCAM_SDA */
+	PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
+	/* B6  : I2C2_SCL ==> MIPI_WCAM_SCL */
+	PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
+
+	/* B11 : NC ==> EN_PP3300_WLAN_X*/
+	PAD_CFG_GPO(GPP_B11, 0, DEEP),
+
+	/* D6 : NC ==> WWAN_PWR_ENABLE */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D8  : SRCCLKREQ3# ==> NC */
+	PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
+	/* D13 : NC ==> EN_PP1800_WCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),
+
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
+	/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
+	PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
+
+	/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+
+	/* F11 : NC ==> WWAN_PWR_ON */
+	PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
+	PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH),
+	/* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	/* F23 : V1P05_CTRL ==> NC*/
+	PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
+
+
+	/* H12 : UART0_RTS# ==> NC*/
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : UART0_CTS# ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+	/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+
+	/* R6 : DMIC_CLK_A_1A ==> NC */
+	PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
+	/* R7 : DMIC_DATA_1A ==> NC */
+	PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+
+	/* F11 : NC ==> WWAN_PWR_ON */
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* D6 : NC ==> WWAN_PWR_ENABLE */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}

src/mainboard/google/brya/variants/teliks/include/variant/ec.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/brya/variants/teliks/include/variant/gpio.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_F11 /* FULL_CARD_POWER_OFF# */
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
+#endif

src/mainboard/google/brya/variants/teliks/memory/Makefile.mk

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-4.hex      # ID = 2(0b0010)  Parts = H9JCNNNFA5MLYR-N6E, MT62F2G32D8DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067

src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT62F512M32D2DR-031 WT:B       0 (0000)
+H9JCNNNBK3MLYR-N6E             0 (0000)
+H9JCNNNCP3MLYR-N6E             1 (0001)
+MT62F1G32D4DR-031 WT:B         1 (0001)
+H9JCNNNFA5MLYR-N6E             2 (0010)
+MT62F2G32D8DR-031 WT:B         2 (0010)
+K3KL6L60GM-MGCT                3 (0011)
+MT62F1G32D2DS-026 WT:B         4 (0100)
+K3KL8L80CM-MGCT                4 (0100)
+H58G56BK7BX068                 4 (0100)
+MT62F2G32D4DS-026 WT:B         5 (0101)
+K3KL9L90CM-MGCT                5 (0101)
+H58G66BK7BX067                 5 (0101)

src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt

@@ -0,0 +1,24 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+MT62F512M32D2DR-031 WT:B
+H9JCNNNBK3MLYR-N6E
+H9JCNNNCP3MLYR-N6E
+MT62F1G32D4DR-031 WT:B
+H9JCNNNFA5MLYR-N6E
+MT62F2G32D8DR-031 WT:B
+K3KL6L60GM-MGCT
+MT62F1G32D2DS-026 WT:B
+K3KL8L80CM-MGCT
+H58G56BK7BX068
+MT62F2G32D4DS-026 WT:B
+K3KL9L90CM-MGCT
+H58G66BK7BX067

src/mainboard/google/brya/variants/teliks/overridetree.cb

@@ -0,0 +1,542 @@
+fw_config
+	field WIFI 8 9
+		option UNKNOWN		0
+		option WIFI_6		1
+		option WIFI_6E		2
+	end
+	field CAMERA 10 11
+		option UF_720P_WF		0
+		option UF_1080P			1
+		option UF_720P			2
+		option UF_1080P_WF		3
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10051"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+
+	# FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 0,
+	}"
+
+	# Enable the Cnvi BT Audio Offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	# Intel Common SoC Config
+	#+-------------+------------------------------+
+	#| Field	|  Value			|
+	#+-------------+------------------------------+
+	#| I2C0	| TPM. Early init is		|
+	#|		| required to set up a BAR	|
+	#|		| for TPM communication	|
+	#| I2C1	| Touchscreen			|
+	#| I2C2	| Sub-board(PSensor)/WCAM	|
+	#| I2C3	| Audio			|
+	#| I2C5	| Trackpad			|
+	#+-------------+------------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 160,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 152,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	# Power limit config
+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""CPU""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,    	CPU,    	95, 5000),
+					[1] = DPTF_PASSIVE(CPU,    	TEMP_SENSOR_0,	75, 5000),
+					[2] = DPTF_PASSIVE(CPU,    	TEMP_SENSOR_1,	75, 5000),
+					[3] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_2,	75, 5000),
+					[4] = DPTF_PASSIVE(CHARGER,  	TEMP_SENSOR_3,	75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,	100, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,	80, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 6000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 3000 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
+				register "cio2_prt[0]" = "1"
+				device generic 0 on
+					probe CAMERA UF_720P_WF
+					probe CAMERA UF_1080P_WF
+				end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ILTK0001""
+				register "generic.desc" = ""ILITEK Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "200"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "200"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 41 on end
+			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
+				register "key.wake_gpe" = "GPE0_DW2_15"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_ANY"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1200_WCAM_X
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe CAMERA UF_720P_WF
+					probe CAMERA UF_1080P_WF
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "2"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW9714 VCM ""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_AFVDD
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe CAMERA UF_720P_WF
+					probe CAMERA UF_1080P_WF
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""GT24P64E""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_size" = "0x2000"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c64""
+
+				device i2c 50 on
+					probe CAMERA UF_720P_WF
+					probe CAMERA UF_1080P_WF
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/rt5645
+				register "hid" = ""10EC5650""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5650""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "jd_mode" = "2"
+				device i2c 1a on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""PRIMAX Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on
+					probe WIFI WIFI_6E
+				end
+			end
+		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on
+					probe WIFI WIFI_6
+				end
+			end
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C MB (7.5 inch)
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C DB (7.1 inch)
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A MB (6.4 inch)
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A DB (6.2 inch)
+			register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# LTE (3.3 inch)
+			register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"	# UFC (3.7 inch)
+			register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
+			register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A0(MLB))
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A1(DB)
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WWAN(LTE)
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 LTE""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""PCIe Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on
+							probe WIFI WIFI_6
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on
+							probe WIFI WIFI_6E
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WLAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref pcie_rp7 off end # SDCard
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "rt5650_sp"
+				register "jack_tplg" = "rt5650_hp"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+	end
+end

src/mainboard/google/brya/variants/teliks/variant.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+#include <soc/gpio_soc_defs.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
+
+static const struct pad_config wifi_pcie_enable_pad[] = {
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+	/* B11 : NC ==> EN_PP3300_WLAN_X*/
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),
+};
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) {
+		printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
+		config->cnvi_bt_core = false;
+		printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n");
+		config->cnvi_bt_audio_offload = false;
+	}
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6))) {
+		printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n");
+		gpio_padbased_override(padbased_table, wifi_pcie_enable_pad,
+						ARRAY_SIZE(wifi_pcie_enable_pad));
+	}
+}