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Sync lemp10 CPU power config with lemp9

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Change-Id: Ia326f80113c1d19c18d492d5387057fe939b3809
This commit is contained in:
Jeremy Soller
2020-11-18 12:50:34 -07:00
parent 2267ee62e4
commit 18cb9b5ab0
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/system76/lemp10/devicetree.cb
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@@ -23,15 +23,15 @@ chip soc/intel/tigerlake
# Power limits # Power limits
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28, .tdp_pl1_override = 20,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 46, .tdp_pl2_override = 30,
}" }"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28, .tdp_pl1_override = 20,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 46, .tdp_pl2_override = 30,
}" }"
# eSPI (soc/intel/tigerlake/espi.c) # eSPI (soc/intel/tigerlake/espi.c)
@@ -212,7 +212,7 @@ chip soc/intel/tigerlake
# Thermal # Thermal
# rdmsr --bitfield 31:24 --decimal 0x1A2 # rdmsr --bitfield 31:24 --decimal 0x1A2
register "tcc_offset" = "8" register "tcc_offset" = "12"
# Graphics (soc/intel/tigerlake/graphics.c) # Graphics (soc/intel/tigerlake/graphics.c)
register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gfx" = "GMA_STATIC_DISPLAYS(0)"