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Fix up the VT8623 northbridge support.

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jonathan McDowell
2005-08-08 08:15:22 +00:00
parent 885b267594
commit 1950783e00
4 changed files with 33 additions and 22 deletions
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2
src/include/device/pci_ids.h
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@@ -1060,6 +1060,8 @@
#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
#define PCI_DEVICE_ID_VIA_8361 0x3112
#define PCI_DEVICE_ID_VIA_8233A 0x3147
#define PCI_DEVICE_ID_VIA_CLE266_VGA 0x3122
#define PCI_DEVICE_ID_VIA_8623 0x3123
#define PCI_DEVICE_ID_VIA_86C100A 0x6100
#define PCI_DEVICE_ID_VIA_8231 0x8231
#define PCI_DEVICE_ID_VIA_8231_4 0x8235

2
src/northbridge/via/vt8623/chip.h
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@@ -2,4 +2,4 @@ struct northbridge_via_vt8623_config
{
};
extern struct chip_operations northbridge_via_vt8623_control;
extern struct chip_operations northbridge_via_vt8623_ops;

47
src/northbridge/via/vt8623/northbridge.c
View File

@@ -8,7 +8,8 @@
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include <cpu/p6/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include "chip.h"
#include "northbridge.h"
@@ -18,7 +19,7 @@
* slower than normal, ethernet drops packets).
* Apparently these registers govern some sort of bus master behavior.
*/
static void norhbrige_init(device_t dev)
static void northbridge_init(device_t dev)
{
device_t fb_dev;
unsigned long fb;
@@ -60,15 +61,13 @@ static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.scan_bus = pci_scan_bridge,
.ops_pci = 0,
.init = northbridge_init
};
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_ops,
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0x3123,
.device = PCI_DEVICE_ID_VIA_8623,
};
static void agp_init(device_t dev)
@@ -93,23 +92,25 @@ static struct device_operations agp_operations = {
};
static struct pci_driver agp_driver __pci_driver = {
.ops = &agp_ops,
.ops = &agp_operations,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0xb091,
.device = PCI_DEVICE_ID_VIA_8633_1,
};
static void vga_init(device_t dev)
{
unsigned long fb;
// unsigned long fb;
printk_debug("VGA random fixup ...\n");
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x0d, 0x20);
/* Set the vga mtrrs */
/* Set the vga mtrrs - disable for the moment */
#if 0
add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
fb = pci_read_config32(dev,0x10); // get the fb address
add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
#endif
}
static struct device_operations vga_operations = {
@@ -121,7 +122,7 @@ static struct device_operations vga_operations = {
};
static struct pci_driver vga_driver __pci_driver = {
.ops = &vga_ops,
.ops = &vga_operations,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0x3122,
};
@@ -132,17 +133,22 @@ static struct pci_driver vga_driver __pci_driver = {
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
printk_spew("Entering vt8623 pci_domain_read_resources.\n");
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
}
static void ram_resource(device_t dev, unsigned long index,
@@ -187,10 +193,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
printk_spew("Entering vt8623 pci_domain_set_resources.\n");
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
@@ -214,7 +221,7 @@ static void pci_domain_set_resources(device_t dev)
ramregs[i]);
}
printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
tomk = ramreg*16*1024 - 32768;
tomk = rambits*16*1024 - 32768;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
@@ -232,6 +239,8 @@ static void pci_domain_set_resources(device_t dev)
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
@@ -263,7 +272,7 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(struct device *dev)
{
struct device_path path;
printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
@@ -275,7 +284,7 @@ static void enable_dev(struct device *dev)
}
}
struct chip_operations northbridge_via_vt8623_control = {
struct chip_operations northbridge_via_vt8623_ops = {
CHIP_NAME("VIA vt8623 Northbridge")
.enable_dev = enable_dev,
};

4
src/northbridge/via/vt8623/raminit.c
View File

@@ -110,7 +110,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug(" is the north\r\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
@@ -250,7 +250,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
print_debug_hex8(val); print_debug(" is the computed timing\n");
print_debug_hex8(val); print_debug(" is the computed timing\r\n");
/* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing.
* pci_write_config8(0, 0x64, val);