arch/riscv: provide a monotonic timer

The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.

Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.

Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/lowrisc/lowrisc/Kconfig

@@ -6,6 +6,9 @@ config SOC_LOWRISC_LOWRISC
 	select ARCH_RAMSTAGE_RISCV
 	select BOOTBLOCK_CONSOLE
 	select DRIVERS_UART_8250MEM_32
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select RISCV_USE_ARCH_TIMER
 	bool
 	default n
 

src/soc/sifive/fu540/Kconfig

@@ -20,7 +20,11 @@ config SOC_SIFIVE_FU540
 	select ARCH_RAMSTAGE_RISCV
 	select BOOTBLOCK_CONSOLE
 	select DRIVERS_UART_SIFIVE
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select RISCV_USE_ARCH_TIMER
 	select UART_OVERRIDE_REFCLK
+
 if SOC_SIFIVE_FU540
 
 config RISCV_ARCH

src/soc/ucb/riscv/Kconfig

@@ -5,6 +5,9 @@ config SOC_UCB_RISCV
 	select ARCH_ROMSTAGE_RISCV
 	select ARCH_RAMSTAGE_RISCV
 	select BOOTBLOCK_CONSOLE
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+	select RISCV_USE_ARCH_TIMER
 	bool
 	default n