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sb/intel/i82801jx: Get rid of device_t

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Use of device_t has been abandoned in ramstage.

Change-Id: I37be7672c88b28180d7d4b46928ebed8472ec020
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS
2018-05-13 13:36:44 +02:00
committed by Nico Huber
parent ac350f82cd
commit 1a8c1df55b
9 changed files with 40 additions and 32 deletions
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3
src/southbridge/intel/i82801jx/hdaudio.c
View File

@ -287,7 +287,8 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void azalia_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

10
src/southbridge/intel/i82801jx/i82801jx.c
View File

@ -25,7 +25,7 @@
typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801jx_enable_device(device_t dev)
static void i82801jx_enable_device(struct device *dev)
{
u32 reg32;
@ -51,7 +51,7 @@ static void i82801jx_early_settings(const config_t *const info)
static void i82801jx_pcie_init(const config_t *const info)
{
device_t pciePort[6];
struct device *pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
u32 reg32;
@ -86,7 +86,7 @@ static void i82801jx_pcie_init(const config_t *const info)
/* Set slot implemented, slot number and slot power limits. */
for (i = 0; i < 6; ++i) {
const device_t dev = pciePort[i];
struct device *const dev = pciePort[i];
u32 xcap = pci_read_config32(dev, D28Fx_XCAP);
if (info->pcie_slot_implemented & (1 << i))
xcap |= PCI_EXP_FLAGS_SLOT;
@ -115,10 +115,10 @@ static void i82801jx_pcie_init(const config_t *const info)
static void i82801jx_ehci_init(void)
{
const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
if (!pciEHCI1)
die("EHCI controller (00:1d.7) not listed in devicetree.\n");
const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));
struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));
if (!pciEHCI2)
die("EHCI controller (00:1a.7) not listed in devicetree.\n");

22
src/southbridge/intel/i82801jx/lpc.c
View File

@ -91,9 +91,9 @@ static void i82801jx_enable_serial_irqs(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
static void i82801jx_pirq_init(device_t dev)
static void i82801jx_pirq_init(struct device *dev)
{
device_t irq_dev;
struct device *irq_dev;
/* Interrupt 11 is not used by legacy devices and so can always be used
* for PCI interrupts. Full legacy IRQ routing is complicated and hard
@ -134,7 +134,7 @@ static void i82801jx_pirq_init(device_t dev)
}
}
static void i82801jx_gpi_routing(device_t dev)
static void i82801jx_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@ -163,7 +163,7 @@ static void i82801jx_gpi_routing(device_t dev)
pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
}
static void i82801jx_power_options(device_t dev)
static void i82801jx_power_options(struct device *dev)
{
u8 reg8;
u16 reg16, pmbase;
@ -295,7 +295,7 @@ static void i82801jx_power_options(device_t dev)
outl(reg32, pmbase + 0x10);
}
static void i82801jx_configure_cstates(device_t dev)
static void i82801jx_configure_cstates(struct device *dev)
{
u8 reg8;
@ -501,7 +501,7 @@ unsigned long acpi_fill_madt(unsigned long current)
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@ -616,7 +616,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}
static void i82801jx_lpc_read_resources(device_t dev)
static void i82801jx_lpc_read_resources(struct device *dev)
{
int i, io_index = 0;
/*
@ -687,7 +687,7 @@ static void i82801jx_lpc_read_resources(device_t dev)
}
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@ -698,7 +698,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
static void southbridge_inject_dsdt(device_t dev)
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@ -720,9 +720,9 @@ static void southbridge_inject_dsdt(device_t dev)
}
}
static void southbridge_fill_ssdt(device_t device)
static void southbridge_fill_ssdt(struct device *device)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);

2
src/southbridge/intel/i82801jx/pci.c
View File

@ -43,7 +43,7 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, PCI_SEC_STATUS, reg16);
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: 0x54 is not the default position! */
if (!vendor || !device) {

5
src/southbridge/intel/i82801jx/pcie.c
View File

@ -94,7 +94,8 @@ static void pci_init(struct device *dev)
}
}
static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void pcie_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
/* NOTE: 0x94 is not the default position! */
if (!vendor || !device) {
@ -106,7 +107,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
static void pch_pciexp_scan_bridge(device_t dev)
static void pch_pciexp_scan_bridge(struct device *dev)
{
struct southbridge_intel_i82801jx_config *config = dev->chip_info;

8
src/southbridge/intel/i82801jx/sata.c
View File

@ -208,7 +208,8 @@ static void sata_init(struct device *const dev)
pci_write_config32(dev, 0x94, sclkcg);
if (is_mobile && config->sata_traffic_monitor) {
const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
struct device *const lpc_dev = dev_find_slot(0,
PCI_DEVFN(0x1f, 0));
if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)
>> 3) & 3) == 3) {
u8 reg8 = pci_read_config8(dev, 0x9c);
@ -224,7 +225,7 @@ static void sata_init(struct device *const dev)
sata_program_indexed(dev, is_mobile);
}
static void sata_enable(device_t dev)
static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
const config_t *const config = dev->chip_info;
@ -251,7 +252,8 @@ static void sata_enable(device_t dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void sata_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

16
src/southbridge/intel/i82801jx/smbus.c
View File

@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "i82801jx.h"
static void pch_smbus_init(device_t dev)
static void pch_smbus_init(struct device *dev)
{
u16 reg16;
@ -35,7 +35,7 @@ static void pch_smbus_init(device_t dev)
pci_write_config16(dev, 0x80, reg16);
}
static int lsmbus_read_byte(device_t dev, u8 address)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@ -48,7 +48,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u16 device;
struct resource *res;
@ -61,7 +61,8 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
return do_smbus_write_byte(res->base, device, address, val);
}
static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes,
const u8 *buf)
{
u16 device;
struct resource *res;
@ -73,7 +74,7 @@ static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)
static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
{
u16 device;
struct resource *res;
@ -92,7 +93,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
.block_write = lsmbus_block_write,
};
static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void smbus_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@ -107,7 +109,7 @@ static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
};
static void smbus_read_resources(device_t dev)
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;

3
src/southbridge/intel/i82801jx/thermal.c
View File

@ -50,7 +50,8 @@ static void thermal_init(struct device *dev)
pci_write_config32(dev, 0x10, 0);
}
static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void thermal_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

3
src/southbridge/intel/i82801jx/usb_ehci.c
View File

@ -33,7 +33,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
u8 access_cntl;