mb/gigabyte/ga-b75m-d3{h,v}: Switch to variant setup
The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate code, and can serve as a base for porting other Gigabyte 7 series motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h. Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Alex James
committed by
Patrick Georgi
Patrick Georgi
parent
edbcd057e6
commit
1bffc4bda3
@@ -1,4 +1,4 @@
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if BOARD_GIGABYTE_GA_B75M_D3H
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if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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@@ -30,12 +30,23 @@ config MAINBOARD_DIR
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string
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string
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default gigabyte/ga-b75m-d3h
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default gigabyte/ga-b75m-d3h
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config VARIANT_DIR
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string
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default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H
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default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "GA-B75M-D3H"
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default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H
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default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V
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config MAX_CPUS
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config MAX_CPUS
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int
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int
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default 8
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default 8
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endif # BOARD_GIGABYTE_GA_B75M_D3H
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# Override the default variant behavior, since the data.vbt is the same
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config INTEL_GMA_VBT_FILE
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string
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default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
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endif # BOARD_GIGABYTE_GA_B75M*
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@@ -1,2 +1,5 @@
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config BOARD_GIGABYTE_GA_B75M_D3H
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config BOARD_GIGABYTE_GA_B75M_D3H
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bool "GA-B75M-D3H"
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bool "GA-B75M-D3H"
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config BOARD_GIGABYTE_GA_B75M_D3V
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bool "GA-B75M-D3V"
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@@ -13,5 +13,10 @@
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## GNU General Public License for more details.
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## GNU General Public License for more details.
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##
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##
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romstage-y += gpio.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@@ -13,9 +13,7 @@
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#include <device/azalia_device.h>
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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#include <variant/hda_verb.h>
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/* FIXME: Add configuration for sound */
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};
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const u32 pc_beep_verbs[] = {};
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const u32 pc_beep_verbs[] = {};
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@@ -88,6 +88,7 @@ void mainboard_early_init(int s3resume)
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{
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{
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}
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}
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/* FIXME: The GA-B75M-D3V only has two DIMM slots! */
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[0], 0x50, id_only);
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@@ -1,9 +1,6 @@
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/*
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/*
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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* the Free Software Foundation; version 2 of the License.
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@@ -14,13 +11,11 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#ifndef GAB75MD3H_THERMAL_H
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#ifndef GA_B75M_D3H_HDA_VERB_H
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#define GAB75MD3H_THERMAL_H
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#define GA_B75M_D3H_HDA_VERB_H
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/* Temperature which OS will shutdown at */
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const u32 cim_verb_data[] = {
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#define CRITICAL_TEMPERATURE 100
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/* FIXME: Add configuration for sound */
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};
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/* Temperature which OS will throttle CPU */
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#define PASSIVE_TEMPERATURE 90
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#endif
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#endif
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@@ -11,7 +11,8 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <device/azalia_device.h>
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#ifndef GA_B75M_D3V_HDA_VERB_H
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#define GA_B75M_D3V_HDA_VERB_H
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const u32 cim_verb_data[] = {
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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/* coreboot specific header */
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@@ -36,6 +37,4 @@ const u32 cim_verb_data[] = {
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AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
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AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
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};
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};
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const u32 pc_beep_verbs[] = {};
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#endif
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AZALIA_ARRAY_SIZES;
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@@ -1,41 +0,0 @@
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if BOARD_GIGABYTE_GA_B75M_D3V
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_ITE_IT8728F
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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config DRAM_RESET_GATE_GPIO
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int
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default 25
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config MAINBOARD_DIR
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string
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default gigabyte/ga-b75m-d3v
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config MAINBOARD_PART_NUMBER
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string
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default "GA-B75M-D3V"
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config MAX_CPUS
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int
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default 8
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endif # BOARD_GIGABYTE_GA_B75M_D3V
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@@ -1,2 +0,0 @@
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config BOARD_GIGABYTE_GA_B75M_D3V
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bool "GA-B75M-D3V"
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@@ -1,17 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@@ -1,23 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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@@ -1,29 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return (Package () {0, 0})
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}
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@@ -1,63 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Thermal Zone
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External (\PPKG, MethodObj)
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Scope (\_TZ)
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{
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ThermalZone (THRM)
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{
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Name (_TC1, 0x02)
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Name (_TC2, 0x03)
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// Thermal zone polling frequency: 10 seconds
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Name (_TZP, 100)
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// Thermal sampling period for passive cooling: 10 seconds
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Name (_TSP, 100)
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// Convert from Degrees C to 1/10 Kelvin for ACPI
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Method (CTOK, 1)
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{
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// 10th of Degrees C
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Multiply (Arg0, 10, Local0)
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// Convert to Kelvin
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Add (Local0, 2732, Local0)
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Return (Local0)
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}
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// Threshold for OS to shutdown
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Method (_CRT, 0, Serialized)
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{
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Return (CTOK (\TCRT))
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}
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// Threshold for passive cooling
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Method (_PSV, 0, Serialized)
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{
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Return (CTOK (\TPSV))
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}
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// Processors used for passive cooling
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Method (_PSL, 0, Serialized)
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{
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Return (\PPKG ())
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}
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}
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}
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@@ -1,39 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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acpi_update_thermal_table(gnvs);
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}
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@@ -1,6 +0,0 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Enable
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nmi=Enable
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sata_mode=AHCI
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gfx_uma_size=32M
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@@ -1,107 +0,0 @@
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##
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## This file is part of the coreboot project.
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||||||
##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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|
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## This program is free software; you can redistribute it and/or modify
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|
||||||
## it under the terms of the GNU General Public License as published by
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|
||||||
## the Free Software Foundation; version 2 of the License.
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|
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##
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|
||||||
## This program is distributed in the hope that it will be useful,
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|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||||
## GNU General Public License for more details.
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||||||
##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
388 4 h 0 reboot_counter
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
#392 3 r 0 unused
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
|
|
||||||
#411 10 r 0 unused
|
|
||||||
421 1 e 9 sata_mode
|
|
||||||
#422 2 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
#425 7 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
|
||||||
432 3 e 11 gfx_uma_size
|
|
||||||
#435 549 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
9 0 AHCI
|
|
||||||
9 1 IDE
|
|
||||||
11 0 32M
|
|
||||||
11 1 64M
|
|
||||||
11 2 96M
|
|
||||||
11 3 128M
|
|
||||||
11 4 160M
|
|
||||||
11 5 192M
|
|
||||||
11 6 224M
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 439 984
|
|
||||||
Binary file not shown.
@@ -1,124 +0,0 @@
|
|||||||
chip northbridge/intel/sandybridge
|
|
||||||
# IGD Displays
|
|
||||||
register "gfx.ndid" = "3"
|
|
||||||
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
|
|
||||||
|
|
||||||
device cpu_cluster 0 on
|
|
||||||
chip cpu/intel/model_206ax
|
|
||||||
register "c1_acpower" = "1"
|
|
||||||
register "c2_acpower" = "3"
|
|
||||||
register "c3_acpower" = "5"
|
|
||||||
register "c1_battery" = "1"
|
|
||||||
register "c2_battery" = "3"
|
|
||||||
register "c3_battery" = "5"
|
|
||||||
# Magic APIC ID to locate this chip
|
|
||||||
device lapic 0x0 on end
|
|
||||||
device lapic 0xacac off end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
register "pci_mmio_size" = "2048"
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
subsystemid 0x1458 0x5000 inherit
|
|
||||||
device pci 00.0 on # Host bridge
|
|
||||||
subsystemid 0x1458 0x5000
|
|
||||||
end
|
|
||||||
device pci 01.0 on end # PCIe Bridge for discrete graphics
|
|
||||||
device pci 02.0 on # Integrated VGA controller
|
|
||||||
subsystemid 0x1458 0xd000
|
|
||||||
end
|
|
||||||
|
|
||||||
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
|
|
||||||
# GPI routing
|
|
||||||
register "alt_gp_smi_en" = "0x0000"
|
|
||||||
register "gen1_dec" = "0x003c0a01"
|
|
||||||
|
|
||||||
# Set max SATA speed to 6.0 Gb/s
|
|
||||||
register "sata_port_map" = "0x3f"
|
|
||||||
register "sata_interface_speed_support" = "0x3"
|
|
||||||
|
|
||||||
register "pcie_port_coalesce" = "0"
|
|
||||||
register "p_cnt_throttling_supported" = "0"
|
|
||||||
register "docking_supported" = "0"
|
|
||||||
register "c2_latency" = "0x0065"
|
|
||||||
|
|
||||||
device pci 14.0 on # USB 3.0 Controller
|
|
||||||
subsystemid 0x1458 0x5007
|
|
||||||
end
|
|
||||||
device pci 16.0 on end # Management Engine Interface 1
|
|
||||||
device pci 16.1 off end # Management Engine Interface 2
|
|
||||||
device pci 16.2 off end # Management Engine IDE-R
|
|
||||||
device pci 16.3 off end # Management Engine KT
|
|
||||||
device pci 19.0 off end # Intel Gigabit Ethernet
|
|
||||||
device pci 1a.0 on # USB2 EHCI #2
|
|
||||||
subsystemid 0x1458 0x5006
|
|
||||||
end
|
|
||||||
device pci 1b.0 on # High Definition Audio
|
|
||||||
subsystemid 0x1458 0xa002
|
|
||||||
end
|
|
||||||
device pci 1c.0 on end # PCIe Port #1
|
|
||||||
device pci 1c.1 off end # PCIe Port #2
|
|
||||||
device pci 1c.2 off end # PCIe Port #3
|
|
||||||
device pci 1c.3 off end # PCIe Port #4
|
|
||||||
device pci 1c.4 on # PCIe Port #5
|
|
||||||
device pci 00.0 on # PCI 10ec:8168
|
|
||||||
subsystemid 0x1458 0xe000
|
|
||||||
end
|
|
||||||
end
|
|
||||||
device pci 1c.5 off end # PCIe Port #6
|
|
||||||
device pci 1c.6 off end # PCIe Port #7
|
|
||||||
device pci 1c.7 off end # PCIe Port #8
|
|
||||||
device pci 1d.0 on # USB2 EHCI #1
|
|
||||||
subsystemid 0x1458 0x5006
|
|
||||||
end
|
|
||||||
device pci 1e.0 on end # PCI bridge
|
|
||||||
device pci 1f.0 on # ISA/LPC bridge
|
|
||||||
subsystemid 0x1458 0x5001
|
|
||||||
chip superio/ite/it8728f
|
|
||||||
device pnp 2e.0 off end # FDC
|
|
||||||
device pnp 2e.1 on # Serial Port 1
|
|
||||||
io 0x60 = 0x3f8
|
|
||||||
irq 0x70 = 4
|
|
||||||
end
|
|
||||||
device pnp 2e.2 on
|
|
||||||
io 0x60 = 0x2f8
|
|
||||||
irq 0x70 = 3
|
|
||||||
end
|
|
||||||
device pnp 2e.3 on
|
|
||||||
io 0x60 = 0x378
|
|
||||||
irq 0x70 = 7
|
|
||||||
drq 0x74 = 4
|
|
||||||
end
|
|
||||||
device pnp 2e.4 on # EC
|
|
||||||
io 0x60 = 0xa30
|
|
||||||
irq 0x70 = 9
|
|
||||||
io 0x62 = 0xa20
|
|
||||||
end
|
|
||||||
device pnp 2e.5 on # Keyboard
|
|
||||||
io 0x60 = 0x60
|
|
||||||
irq 0x70 = 1
|
|
||||||
io 0x62 = 0x64
|
|
||||||
end
|
|
||||||
device pnp 2e.6 on # Mouse
|
|
||||||
irq 0x70 = 12
|
|
||||||
end
|
|
||||||
device pnp 2e.7 off end # GPIO
|
|
||||||
device pnp 2e.a off end # IR
|
|
||||||
end
|
|
||||||
|
|
||||||
chip drivers/pc80/tpm
|
|
||||||
device pnp 0c31.0 on end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
device pci 1f.2 on # SATA Controller 1
|
|
||||||
subsystemid 0x1458 0xb005
|
|
||||||
end
|
|
||||||
device pci 1f.3 on # SMBus
|
|
||||||
subsystemid 0x1458 0x5001
|
|
||||||
end
|
|
||||||
device pci 1f.4 off end
|
|
||||||
device pci 1f.5 off end # SATA Controller 2
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@@ -1,43 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20141018 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
|
||||||
|
|
||||||
// Some generic macros
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
#include "acpi/platform.asl"
|
|
||||||
#include "acpi/thermal.asl"
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
/* global NVS and variables. */
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
|
||||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,34 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2011-2012 Google Inc.
|
|
||||||
* Copyright (C) 2014 Vladimir Serbinenko
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <drivers/intel/gma/int15.h>
|
|
||||||
#include <southbridge/intel/bd82x6x/pch.h>
|
|
||||||
|
|
||||||
// mainboard_enable is executed as first thing after
|
|
||||||
// enumerate_buses().
|
|
||||||
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
|
||||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
|
||||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable
|
|
||||||
};
|
|
||||||
@@ -1,104 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/pci_ops.h>
|
|
||||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
|
||||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
|
||||||
#include <southbridge/intel/bd82x6x/pch.h>
|
|
||||||
#include <superio/ite/common/ite.h>
|
|
||||||
#include <superio/ite/it8728f/it8728f.h>
|
|
||||||
|
|
||||||
#define SUPERIO_BASE 0x2e
|
|
||||||
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
|
|
||||||
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
|
|
||||||
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
|
|
||||||
|
|
||||||
void pch_enable_lpc(void)
|
|
||||||
{
|
|
||||||
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
|
|
||||||
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
|
|
||||||
|
|
||||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
|
|
||||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
|
|
||||||
|
|
||||||
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
|
|
||||||
}
|
|
||||||
|
|
||||||
void mainboard_config_superio(void)
|
|
||||||
{
|
|
||||||
/* Initialize SuperIO */
|
|
||||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
|
||||||
|
|
||||||
ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
|
|
||||||
|
|
||||||
/* FIXME: These values could be configured in ramstage */
|
|
||||||
ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
|
|
||||||
ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
|
|
||||||
ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
|
|
||||||
ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
|
|
||||||
ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
|
|
||||||
ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
|
|
||||||
ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
|
|
||||||
ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
|
|
||||||
ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
|
|
||||||
ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
|
|
||||||
ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
|
|
||||||
|
|
||||||
/* EC SIO settings */
|
|
||||||
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
|
|
||||||
ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
|
|
||||||
ite_reg_write(IT8728F_EC, 0xf9, 0x48);
|
|
||||||
ite_reg_write(IT8728F_EC, 0x60, 0x0a);
|
|
||||||
ite_reg_write(IT8728F_EC, 0x61, 0x30);
|
|
||||||
ite_reg_write(IT8728F_EC, 0x62, 0x0a);
|
|
||||||
ite_reg_write(IT8728F_EC, 0x63, 0x20);
|
|
||||||
ite_reg_write(IT8728F_EC, 0x30, 0x01);
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
|
||||||
{ 1, 5, 0 },
|
|
||||||
{ 1, 5, 0 },
|
|
||||||
{ 1, 5, 1 },
|
|
||||||
{ 1, 5, 1 },
|
|
||||||
{ 1, 5, 2 },
|
|
||||||
{ 1, 5, 2 },
|
|
||||||
{ 1, 5, 3 },
|
|
||||||
{ 1, 5, 3 },
|
|
||||||
{ 1, 5, 4 },
|
|
||||||
{ 1, 5, 4 },
|
|
||||||
{ 1, 5, 6 },
|
|
||||||
{ 1, 5, 5 },
|
|
||||||
{ 1, 5, 5 },
|
|
||||||
{ 1, 5, 6 },
|
|
||||||
};
|
|
||||||
|
|
||||||
void mainboard_early_init(int s3resume)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/* FIXME: This board only has two DIMM slots! */
|
|
||||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
|
||||||
{
|
|
||||||
read_spd(&spd[0], 0x50, id_only);
|
|
||||||
read_spd(&spd[1], 0x51, id_only);
|
|
||||||
read_spd(&spd[2], 0x52, id_only);
|
|
||||||
read_spd(&spd[3], 0x53, id_only);
|
|
||||||
}
|
|
||||||
|
|
||||||
void mainboard_rcba_config(void)
|
|
||||||
{
|
|
||||||
/* Enable HECI */
|
|
||||||
RCBA32(FD2) &= ~0x2;
|
|
||||||
}
|
|
||||||
Reference in New Issue
Block a user