cpu: microcode: Use microcode stored in binary format
Using a copiler to compile something that's already a binary is pretty stupid. Now that Stefan converted most microcode in blobs to a plain binary, use the binary version. Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Alexandru Gagniuc
committed by
Patrick Georgi
Patrick Georgi
parent
b20a600ba7
commit
1d85700503
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
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cbfs_include_ucode = y
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endif
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# In case we have more than one "source" (cough) files containing microcode, we
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# link them together in one large blob, so that we get all the microcode updates
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# in one file. This makes it easier for objcopy in the final step.
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# The --entry=0 is just here to suppress the LD warning. It does not affect the
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# final microcode file.
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$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
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@printf " LD $(subst $(obj)/,,$(@))\n"
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$(LD_cpu_microcode) -static --entry=0 $+ -o $@
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# We have a lot of useless data in the large blob, and we are only interested in
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# the data section, so we only copy that part to the final microcode file
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$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
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# We just mash all microcode binaries together into one binary to rule them all.
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# This approach assumes that the microcode binaries are properly padded, and
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# their headers specify the correct size. This works fairly well on isolatied
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# updates, such as Intel and some AMD microcode, but won't work very well if the
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# updates are wrapped in a container, like AMD's microcode update container. If
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# there is only one microcode binary (i.e. one container), then we don't have
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# this issue, and this rule will continue to work.
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$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
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@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
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@echo $(cpu_microcode_bins)
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cat $+ > $@
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cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
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cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
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@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
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ramstage-y += monotonic_timer.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned char microcode[] __attribute__ ((aligned(16))) = {
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#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
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};
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@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
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ramstage-y += processor_name.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
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@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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@@ -1,8 +0,0 @@
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/*
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* We support updating microcode from CBFS, but do not have any microcode
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* updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
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* CBFS, but this file can be later replaced without needing to recompile the
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* coreboot.rom image.
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*/
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unsigned microcode_updates_ep80579[] = {
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};
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@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
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depends on SUPPORT_CPU_UCODE_IN_CBFS
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default 0xfff70000
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config MICROCODE_INCLUDE_PATH
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string "Location of the intel microcode patches"
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default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
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default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
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endif
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@@ -6,11 +6,6 @@ ramstage-y += acpi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
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ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
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ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
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CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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endif
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endif
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
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@@ -1,22 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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unsigned microcode[] = {
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#include "microcode_blob.h"
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};
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@@ -1,33 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
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/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
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#include <microcode-m12206a7_00000029.h>
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#endif
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#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
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/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
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#include <microcode-m12306a2_00000008.h>
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#include <microcode-m12306a4_00000007.h>
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#include <microcode-m12306a5_00000007.h>
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#include <microcode-m12306a8_00000010.h>
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#include <microcode-m12306a9_00000019.h>
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#endif
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@@ -1,7 +0,0 @@
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/* Maximum size of the area that the FSP will search for the correct microcode */
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#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
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#define MICROCODE_REGION_LENGTH 0xC000
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#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
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#define MICROCODE_REGION_LENGTH 0x2800
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#endif
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@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
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depends on SUPPORT_CPU_UCODE_IN_CBFS
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default 0xfff60040
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config MICROCODE_INCLUDE_PATH
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string "Location of the intel microcode patches"
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default "../intel/cpu/rangeley/microcode"
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endif #CPU_INTEL_FSP_MODEL_406DX
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@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
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ramstage-y += acpi.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
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ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
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ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
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CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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endif
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endif
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# We don't have microcode for this CPU
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# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
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# cpu_microcode_bins += ???
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@@ -1,29 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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unsigned microcode[] = {
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#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
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/* Size is 0x14400 - update in microcode_size.h when the file changes */
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#include <microcode-m01406d000e.h>
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#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
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/* Size is 0x14800 - update in microcode_size.h when the file changes */
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#include <microcode-m01406d811d.h>
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#endif
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};
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@@ -1,7 +0,0 @@
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/* Maximum size of the area that the FSP will search for the correct microcode */
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#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
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#define MICROCODE_REGION_LENGTH 0x14400
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#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
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#define MICROCODE_REGION_LENGTH 0x14800
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#endif
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@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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smm-y += monotonic_timer.c
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@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../turbo
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
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@@ -1,30 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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unsigned microcode[] = {
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/*
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* FIXME: Can we just include both microcodes regardless, or is there
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* a very good reason why we only use one at a time?
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*/
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#if CONFIG_INTEL_LYNXPOINT_LP
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#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
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#else
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#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
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#endif
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};
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@@ -1,4 +1,4 @@
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ramstage-y += model_1067x_init.c
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subdirs-y += ../../x86/name
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned microcode_updates_1067ax[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
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};
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@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
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subdirs-y += ../../x86/name
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned microcode_updates_106cx[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
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};
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@@ -17,6 +17,6 @@ ramstage-y += acpi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
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cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
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@@ -1,22 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc.
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*/
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unsigned microcode[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
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};
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@@ -6,6 +6,7 @@ ramstage-y += acpi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
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cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
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@@ -1,23 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
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*/
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unsigned microcode[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
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};
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@@ -20,4 +20,4 @@
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ramstage-y += model_65x_init.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned microcode_updates_65x[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
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};
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@@ -20,4 +20,4 @@
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ramstage-y += model_67x_init.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned microcode_updates_67x[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
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};
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@@ -21,4 +21,4 @@
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ramstage-y += model_68x_init.c
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subdirs-y += ../../x86/name
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
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@@ -1,3 +0,0 @@
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unsigned microcode_updates_68x[] = {
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#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
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};
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@@ -1,3 +1,3 @@
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ramstage-y += model_69x_init.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_69x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
|
||||
};
|
||||
@@ -1,4 +1,4 @@
|
||||
ramstage-y += model_6bx_init.c
|
||||
subdirs-y += ../../x86/name
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_6bx[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_6dx_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_6dx[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
|
||||
};
|
||||
@@ -1,4 +1,4 @@
|
||||
ramstage-y += model_6ex_init.c
|
||||
subdirs-y += ../../x86/name
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_6ex[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
|
||||
};
|
||||
@@ -1,4 +1,4 @@
|
||||
ramstage-y += model_6fx_init.c
|
||||
subdirs-y += ../../x86/name
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_6fx[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_6xx_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_6xx[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_f0x_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
/* 256KB cache */
|
||||
unsigned microcode_updates_f0x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_f1x_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
/* 256KB cache */
|
||||
unsigned microcode_updates_f1x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_f2x_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
/* 512KB cache */
|
||||
unsigned microcode_updates_f2x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_f3x_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_f3x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
|
||||
};
|
||||
@@ -1,3 +1,3 @@
|
||||
ramstage-y += model_f4x_init.c
|
||||
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode_updates_f4x[] = {
|
||||
#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
|
||||
};
|
||||
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
|
||||
ramstage-y += nano_init.c
|
||||
ramstage-y += update_ucode.c
|
||||
|
||||
# This microcode is included as a separate CBFS file. It is never linked in to
|
||||
# the rest of coreboot.
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
|
||||
|
||||
cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
|
||||
|
||||
@@ -25,7 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
|
||||
|
||||
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
|
||||
|
||||
ifneq ($(cpu_microcode-objs),)
|
||||
ifneq ($(cpu_microcode_bins),)
|
||||
$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
|
||||
printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
|
||||
&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
|
||||
|
||||
subdirs-y += microcode
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/x86/lapic
|
||||
subdirs-y += ../../../cpu/x86/mtrr
|
||||
@@ -53,6 +52,8 @@ ramstage-y += hda.c
|
||||
# Remove as ramstage gets fleshed out
|
||||
ramstage-y += placeholders.c
|
||||
|
||||
cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
|
||||
|
||||
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
|
||||
|
||||
# If an MRC file is an ELF file determine the entry address and first loadable
|
||||
|
||||
@@ -1 +0,0 @@
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
@@ -1,3 +0,0 @@
|
||||
unsigned microcode[] = {
|
||||
#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
|
||||
};
|
||||
@@ -1,6 +1,5 @@
|
||||
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
|
||||
|
||||
subdirs-y += microcode
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/x86/lapic
|
||||
subdirs-y += ../../../cpu/x86/mtrr
|
||||
@@ -51,6 +50,8 @@ smm-y += smihandler.c
|
||||
smm-y += spi.c
|
||||
smm-y += tsc_freq.c
|
||||
|
||||
# cpu_microcode_bins += ???
|
||||
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
|
||||
|
||||
|
||||
@@ -1,2 +0,0 @@
|
||||
# Add CPU uCode source to list of files to build.
|
||||
cpu_microcode-y += microcode_blob.c
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
unsigned microcode[] = {
|
||||
#include <microcode/microcode_blob.h>
|
||||
};
|
||||
@@ -1,6 +1,5 @@
|
||||
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
|
||||
|
||||
subdirs-y += microcode
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/x86/lapic
|
||||
subdirs-y += ../../../cpu/x86/mtrr
|
||||
@@ -73,6 +72,8 @@ romstage-y += usbdebug.c
|
||||
smm-y += usbdebug.c
|
||||
endif
|
||||
|
||||
cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
|
||||
|
||||
CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
|
||||
|
||||
# If an MRC file is an ELF file determine the entry address and first loadable
|
||||
|
||||
@@ -1 +0,0 @@
|
||||
cpu_microcode-y += microcode_blob.c
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
unsigned microcode[] = {
|
||||
#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
|
||||
};
|
||||
@@ -20,7 +20,6 @@
|
||||
|
||||
ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
|
||||
|
||||
subdirs-y += microcode
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/x86/lapic
|
||||
subdirs-y += ../../../cpu/x86/mtrr
|
||||
@@ -59,6 +58,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
|
||||
ramstage-y += placeholders.c
|
||||
ramstage-y += i2c.c
|
||||
|
||||
cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
|
||||
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
|
||||
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc.
|
||||
#
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
|
||||
|
||||
ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
|
||||
ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
|
||||
CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
|
||||
endif
|
||||
endif
|
||||
@@ -1,38 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
unsigned microcode[] = {
|
||||
|
||||
/*
|
||||
* The problem is that these microcode files are not in the tree. They come
|
||||
* with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
|
||||
* is enabled.
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
|
||||
#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
|
||||
/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
|
||||
#include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1
|
||||
#include "M0130673322.h" // M0130673: Bay Trail I B2 / B3
|
||||
#include "M0130679901.h" // M0130679: Bay Trail I D0
|
||||
#else
|
||||
/* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
|
||||
#include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping
|
||||
#endif /* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
|
||||
#endif /* CONFIG_HAVE_FSP_BIN */
|
||||
};
|
||||
@@ -1,6 +0,0 @@
|
||||
/* Maximum size of the area that the FSP will search for the correct microcode */
|
||||
#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
|
||||
#define MICROCODE_REGION_LENGTH 0x30000
|
||||
#else
|
||||
#define MICROCODE_REGION_LENGTH 0x10000
|
||||
#endif
|
||||
@@ -1,6 +1,5 @@
|
||||
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
|
||||
|
||||
subdirs-y += microcode
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/intel/microcode
|
||||
subdirs-y += ../../../cpu/intel/turbo
|
||||
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
|
||||
smm-y += tsc_freq.c
|
||||
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
|
||||
|
||||
# cpu_microcode_bins += ???
|
||||
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/skylake
|
||||
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
|
||||
|
||||
|
||||
@@ -1,2 +0,0 @@
|
||||
# Add CPU uCode source to list of files to build.
|
||||
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
unsigned int microcode[] = {
|
||||
#include <microcode/microcode_blob.h>
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user